@misc{10650, author = {{Dridger, Denis}}, publisher = {{Paderborn University}}, title = {{{Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}}}, year = {{2012}}, } @phdthesis{10652, abstract = {{The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.}}, author = {{Giefers, Heiner}}, isbn = {{978-3-8325-3165-2}}, pages = {{159}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Design and Programming of Reconfigurable Mesh based Many-Cores}}}, year = {{2012}}, } @misc{10658, author = {{Graf, Tobias}}, publisher = {{Paderborn University}}, title = {{{Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}}}, year = {{2012}}, } @misc{10667, author = {{Hangmann, Hendrik}}, publisher = {{Paderborn University}}, title = {{{Generating Adjustable Temperature Gradients on modern FPGAs}}}, year = {{2012}}, } @article{10685, author = {{Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}}, journal = {{International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}}, number = {{4}}, pages = {{17--31}}, publisher = {{IGI Global}}, title = {{{Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}}}, doi = {{10.4018/jaras.2012100102}}, volume = {{3}}, year = {{2012}}, } @misc{10723, author = {{Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}}, pages = {{6--11}}, title = {{{Wieder natürlich gehen und greifen}}}, year = {{2012}}, } @misc{10734, author = {{Schmitz, Henning}}, publisher = {{Paderborn University}}, title = {{{Stereo Matching on a HC-1 Hybrid Core Computer}}}, year = {{2012}}, } @misc{10747, author = {{Topmöller, Christoph}}, publisher = {{Paderborn University}}, title = {{{Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}}}, year = {{2012}}, } @misc{10754, author = {{Wistuba, Martin}}, publisher = {{Paderborn University}}, title = {{{Analysis of Pattern Based Model Design and Learning in Computer-Go}}}, year = {{2012}}, } @misc{13462, author = {{Lewis, Peter and Platzner, Marco and Yao, Xin}}, publisher = {{Awareness Magazine}}, title = {{{An outlook for self-awareness in computing systems}}}, year = {{2012}}, } @inproceedings{2106, abstract = {{Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.}}, author = {{Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{funding-upb-forschungspreis, funding-maxup, tet_topic_hpc}}, pages = {{189--196}}, publisher = {{IEEE}}, title = {{{Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @article{2108, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, issn = {{0141-9331}}, journal = {{Microprocessors and Microsystems}}, keywords = {{funding-altera}}, number = {{2}}, pages = {{110--126}}, title = {{{IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}}}, doi = {{10.1016/j.micpro.2011.04.002}}, volume = {{36}}, year = {{2012}}, } @inproceedings{615, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.}}, author = {{Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}}}, doi = {{10.1109/ReConFig.2012.6416745}}, year = {{2012}}, } @inproceedings{591, abstract = {{One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.}}, author = {{Kenter, Tobias and Plessl, Christian and Schmitz, Henning}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Pragma based parallelization - Trading hardware efficiency for ease of use?}}}, doi = {{10.1109/ReConFig.2012.6416773}}, year = {{2012}}, } @inproceedings{609, abstract = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}}, pages = {{8--9}}, title = {{{Hardware/Software Platform for Self-aware Compute Nodes}}}, year = {{2012}}, } @inproceedings{567, abstract = {{Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.}}, author = {{Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}}, pages = {{559--565}}, publisher = {{IEEE}}, title = {{{Turning control flow graphs into function calls: Code generation for heterogeneous architectures}}}, doi = {{10.1109/HPCSim.2012.6266973}}, year = {{2012}}, } @inproceedings{612, abstract = {{While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.}}, author = {{Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, pages = {{559--562}}, publisher = {{IEEE}}, title = {{{Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @inproceedings{2180, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}}, keywords = {{funding-enhance}}, title = {{{Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}}}, year = {{2012}}, } @article{2177, author = {{Grad, Mariusz and Plessl, Christian}}, journal = {{Int. Journal of Reconfigurable Computing (IJRC)}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}}}, doi = {{10.1155/2012/418315}}, year = {{2012}}, } @inproceedings{2191, author = {{Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}}, booktitle = {{Intel European Research and Innovation Conference}}, keywords = {{funding-intel}}, title = {{{Estimation and Partitioning for CPU-Accelerator Architectures}}}, year = {{2011}}, } @inbook{2202, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}}, editor = {{Khalgui, Mohamed and Hanisch, Hans-Michael}}, isbn = {{978-1-60960-086-0}}, publisher = {{IGI Global}}, title = {{{Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}}}, doi = {{10.4018/978-1-60960-086-0}}, year = {{2011}}, } @inproceedings{2204, author = {{Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}}, booktitle = {{Proc. European Conf. on Parallel Processing (Euro-Par)}}, publisher = {{Springer}}, title = {{{Parallel Monte-Carlo Tree Search for HPC Systems}}}, doi = {{10.1007/978-3-642-23397-5_36}}, volume = {{6853}}, year = {{2011}}, } @inproceedings{666, abstract = {{Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach.}}, author = {{Drzevitzky, Stephanie and Platzner, Marco}}, booktitle = {{Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, pages = {{58--65}}, title = {{{Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}}}, doi = {{10.1109/ReCoSoC.2011.5981499}}, year = {{2011}}, } @inproceedings{10637, author = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT)}}, title = {{{Accurate gait phase detection using surface electromyographic signals and support vector machines}}}, year = {{2011}}, } @inproceedings{10638, author = {{Boschmann, Alexander and Platzner, Marco and Robrecht, Michael and Hahn, Martin and Winkler, Michael}}, booktitle = {{Proc. MyoElectric Controls Symposium (MEC)}}, title = {{{Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems}}}, year = {{2011}}, } @misc{10678, author = {{Ikonomakis, Nikolaos}}, publisher = {{Paderborn University}}, title = {{{PinSim: Schnelle Simulation mit Pintools}}}, year = {{2011}}, } @misc{10680, author = {{Kassner, Hendrik}}, publisher = {{Paderborn University}}, title = {{{MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern}}}, year = {{2011}}, } @inbook{10687, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Organic Computing---A Paradigm Shift for Complex Systems}}, editor = {{Müller-Schloer, Christian and Schmeck, Hartmut and Ungerer, Theo}}, pages = {{193--206}}, publisher = {{Springer Basel}}, title = {{{Multi-objective Intrinsic Evolution of Embedded Systems}}}, volume = {{1}}, year = {{2011}}, } @misc{10736, author = {{Schwabe, Arne}}, publisher = {{Paderborn University}}, title = {{{Analysis of Algorithmic Approaches for Temporal Partitioning}}}, year = {{2011}}, } @inbook{10737, author = {{Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{125--179}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Evolution of Electronic Circuits}}}, year = {{2011}}, } @inbook{10748, author = {{Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{35--99}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Problem Decomposition in Cartesian Genetic Programming}}}, year = {{2011}}, } @misc{10750, author = {{Welp, Daniel}}, publisher = {{Paderborn University}}, title = {{{User Space Scheduling for Heterogeneous Systems}}}, year = {{2011}}, } @inproceedings{13643, author = {{Agne, Andreas and Platzner, Marco and Lübbers, Enno}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781457714849}}, pages = {{185--188}}, publisher = {{IEEE}}, title = {{{Memory Virtualization for Multithreaded Reconfigurable Hardware}}}, doi = {{10.1109/fpl.2011.42}}, year = {{2011}}, } @inproceedings{13644, author = {{Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and Tahoori, Mehdi and Bauer, Lars and Teich, Jürgen and Wehn, Norbert and Wunderlich, Hans-Joachim and Becker, Joachim and Bringmann, Oliver and Brinkschulte, Uwe and Chakraborty, Samarjit and Engel, Michael and Ernst, Rolf and Härtig, Hermann}}, booktitle = {{Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11}}, isbn = {{9781450307154}}, title = {{{Design and architectures for dependable embedded systems}}}, doi = {{10.1145/2039370.2039384}}, year = {{2011}}, } @inproceedings{2194, author = {{Meyer, Björn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Symp. on Application Accelerators in High Performance Computing (SAAHPC)}}, keywords = {{tet_topic_hpc}}, pages = {{60--63}}, publisher = {{IEEE Computer Society}}, title = {{{Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}}}, doi = {{10.1109/SAAHPC.2011.12}}, year = {{2011}}, } @inproceedings{2193, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, pages = {{223--226}}, publisher = {{IEEE Computer Society}}, title = {{{Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}}}, doi = {{10.1109/ASAP.2011.6043273}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @article{2201, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, journal = {{Int. Journal of Recon- figurable Computing (IJRC)}}, keywords = {{funding-altera}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}}}, doi = {{10.1155/2011/760954}}, year = {{2011}}, } @inproceedings{2198, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Reconfigurable Architectures Workshop (RAW)}}, pages = {{278--285}}, publisher = {{IEEE Computer Society}}, title = {{{Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}}}, doi = {{10.1109/IPDPS.2011.153}}, year = {{2011}}, } @article{10605, author = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}}, journal = {{International Journal of Reconfigurable Computing}}, publisher = {{Hindawi Publishing Corporation}}, title = {{{Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}}}, doi = {{10.1155/2010/180242}}, volume = {{2010}}, year = {{2010}}, } @misc{10614, author = {{Agne, Andreas}}, publisher = {{Paderborn University}}, title = {{{Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}}}, year = {{2010}}, } @misc{10629, author = {{Boschmann, Alexander}}, publisher = {{Paderborn University}}, title = {{{EMG-basierte Ganganalyse}}}, year = {{2010}}, } @misc{10642, author = {{Breitlauch, Daniel}}, publisher = {{Paderborn University}}, title = {{{Evolvable Cache Controller}}}, year = {{2010}}, } @misc{10649, author = {{Dridger, Denis}}, publisher = {{Paderborn University}}, title = {{{Soft Microprocessors with tightly coupled Application-Specific Coprocessors}}}, year = {{2010}}, } @misc{10657, author = {{Graf, Tobias}}, publisher = {{Paderborn University}}, title = {{{Parallelization of the UCT Algorithm on HPC-Clusters}}}, year = {{2010}}, } @inproceedings{10683, author = {{Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}}, booktitle = {{International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}}, pages = {{6357--6360}}, publisher = {{IEEE}}, title = {{{Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}}}, year = {{2010}}, } @inproceedings{10686, author = {{Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}}, booktitle = {{IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}}, pages = {{541--548}}, publisher = {{IEEE}}, title = {{{A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}}}, year = {{2010}}, } @article{10694, author = {{Kebschull, Udo and Platzner, Marco and Teich, Jürgen}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, number = {{3}}, pages = {{157--158}}, title = {{{Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}}}, doi = {{10.1049/iet-cdt.2010.9044}}, volume = {{4}}, year = {{2010}}, } @misc{10697, author = {{Knieper, Tobias}}, publisher = {{Paderborn University}}, title = {{{Hybridization of Global Multi-Objective and Local Search Techniques}}}, year = {{2010}}, }