@inbook{10748, author = {{Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{35--99}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Problem Decomposition in Cartesian Genetic Programming}}}, year = {{2011}}, } @misc{10750, author = {{Welp, Daniel}}, publisher = {{Paderborn University}}, title = {{{User Space Scheduling for Heterogeneous Systems}}}, year = {{2011}}, } @inproceedings{13643, author = {{Agne, Andreas and Platzner, Marco and Lübbers, Enno}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781457714849}}, pages = {{185--188}}, publisher = {{IEEE}}, title = {{{Memory Virtualization for Multithreaded Reconfigurable Hardware}}}, doi = {{10.1109/fpl.2011.42}}, year = {{2011}}, } @inproceedings{13644, author = {{Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and Tahoori, Mehdi and Bauer, Lars and Teich, Jürgen and Wehn, Norbert and Wunderlich, Hans-Joachim and Becker, Joachim and Bringmann, Oliver and Brinkschulte, Uwe and Chakraborty, Samarjit and Engel, Michael and Ernst, Rolf and Härtig, Hermann}}, booktitle = {{Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11}}, isbn = {{9781450307154}}, title = {{{Design and architectures for dependable embedded systems}}}, doi = {{10.1145/2039370.2039384}}, year = {{2011}}, } @inproceedings{2194, author = {{Meyer, Björn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Symp. on Application Accelerators in High Performance Computing (SAAHPC)}}, keywords = {{tet_topic_hpc}}, pages = {{60--63}}, publisher = {{IEEE Computer Society}}, title = {{{Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}}}, doi = {{10.1109/SAAHPC.2011.12}}, year = {{2011}}, } @inproceedings{2193, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, pages = {{223--226}}, publisher = {{IEEE Computer Society}}, title = {{{Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}}}, doi = {{10.1109/ASAP.2011.6043273}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @article{2201, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, journal = {{Int. Journal of Recon- figurable Computing (IJRC)}}, keywords = {{funding-altera}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}}}, doi = {{10.1155/2011/760954}}, year = {{2011}}, } @inproceedings{2198, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Reconfigurable Architectures Workshop (RAW)}}, pages = {{278--285}}, publisher = {{IEEE Computer Society}}, title = {{{Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}}}, doi = {{10.1109/IPDPS.2011.153}}, year = {{2011}}, } @article{10605, author = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}}, journal = {{International Journal of Reconfigurable Computing}}, publisher = {{Hindawi Publishing Corporation}}, title = {{{Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}}}, doi = {{10.1155/2010/180242}}, volume = {{2010}}, year = {{2010}}, } @misc{10614, author = {{Agne, Andreas}}, publisher = {{Paderborn University}}, title = {{{Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}}}, year = {{2010}}, } @misc{10629, author = {{Boschmann, Alexander}}, publisher = {{Paderborn University}}, title = {{{EMG-basierte Ganganalyse}}}, year = {{2010}}, } @misc{10642, author = {{Breitlauch, Daniel}}, publisher = {{Paderborn University}}, title = {{{Evolvable Cache Controller}}}, year = {{2010}}, } @misc{10649, author = {{Dridger, Denis}}, publisher = {{Paderborn University}}, title = {{{Soft Microprocessors with tightly coupled Application-Specific Coprocessors}}}, year = {{2010}}, } @misc{10657, author = {{Graf, Tobias}}, publisher = {{Paderborn University}}, title = {{{Parallelization of the UCT Algorithm on HPC-Clusters}}}, year = {{2010}}, } @inproceedings{10683, author = {{Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}}, booktitle = {{International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}}, pages = {{6357--6360}}, publisher = {{IEEE}}, title = {{{Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}}}, year = {{2010}}, } @inproceedings{10686, author = {{Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}}, booktitle = {{IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}}, pages = {{541--548}}, publisher = {{IEEE}}, title = {{{A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}}}, year = {{2010}}, } @article{10694, author = {{Kebschull, Udo and Platzner, Marco and Teich, Jürgen}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, number = {{3}}, pages = {{157--158}}, title = {{{Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}}}, doi = {{10.1049/iet-cdt.2010.9044}}, volume = {{4}}, year = {{2010}}, } @misc{10697, author = {{Knieper, Tobias}}, publisher = {{Paderborn University}}, title = {{{Hybridization of Global Multi-Objective and Local Search Techniques}}}, year = {{2010}}, } @inproceedings{10699, author = {{Knieper, Tobias and Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{250--261}}, publisher = {{Springer}}, title = {{{Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture}}}, volume = {{6274}}, year = {{2010}}, } @inbook{10704, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}}, editor = {{Platzner, Marco and Teich, Jürgen and Wehn, Norbert}}, pages = {{269--290}}, publisher = {{Springer-Verlag GmbH}}, title = {{{ReconOS: An Operating System for Dynamically Reconfigurable Hardware}}}, doi = {{10.1007/978-90-481-3485-4_13}}, year = {{2010}}, } @misc{10710, author = {{Meiche, Robert}}, publisher = {{Paderborn University}}, title = {{{FPGA/CPU Multicore-Plattform für ReconOS/eCos}}}, year = {{2010}}, } @misc{10717, author = {{Niekamp, Manuel}}, publisher = {{Paderborn University}}, title = {{{Transparente Hardwarebeschleunigung durch Shared Library Interposing}}}, year = {{2010}}, } @misc{10731, author = {{Runde, Bodo}}, publisher = {{Paderborn University}}, title = {{{A Token-Ring Network-On-Chip for Message Passing in ReconOS}}}, year = {{2010}}, } @misc{10752, author = {{Wiersema, Tobias}}, publisher = {{Paderborn University}}, title = {{{Scheduling Support for Heterogeneous Hardware Accelerators under Linux}}}, year = {{2010}}, } @book{10763, editor = {{Platzner, Marco and Teich, Jürgen and Wehn, Norbert}}, isbn = {{9048134846}}, publisher = {{Springer-Verlag GmbH}}, title = {{{Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}}}, doi = {{10.1007/978-90-481-3485-4}}, year = {{2010}}, } @inproceedings{10776, author = {{Khatir, Mehrdad and Ghasemzadeh Mohammadi, Hassan and Ejlali, Alireza}}, booktitle = {{Computer Design (ICCD), 2010 IEEE International Conference on}}, pages = {{138--144}}, publisher = {{IEEE}}, title = {{{Sub-threshold charge recovery circuits}}}, doi = {{10.1109/ICCD.2010.5647815}}, year = {{2010}}, } @inproceedings{13640, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)}}, publisher = {{IEEE}}, title = {{{A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier}}}, year = {{2010}}, } @inproceedings{13641, author = {{Schäfer, Wilhelm and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O'Grady, Rehan and Platzner, Marco and Rammig, Franz-Josef and Reif, Wolfgang and Trächtler, Ansgar}}, booktitle = {{Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)}}, pages = {{321--324}}, title = {{{Engineering Self-Coordinating Software Intensive Systems}}}, year = {{2010}}, } @inproceedings{13642, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics}}}, year = {{2010}}, } @inproceedings{2223, author = {{Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{225--231}}, publisher = {{CSREA Press}}, title = {{{Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}}}, year = {{2010}}, } @inproceedings{2216, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{67--72}}, publisher = {{IEEE Computer Society}}, title = {{{Pruning the Design Space for Just-In-Time Processor Customization}}}, doi = {{10.1109/ReConFig.2010.19}}, year = {{2010}}, } @inproceedings{2224, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{144--150}}, publisher = {{CSREA Press}}, title = {{{An Open Source Circuit Library with Benchmarking Facilities}}}, year = {{2010}}, } @inproceedings{2220, author = {{Andrews, David and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{165}}, publisher = {{CSREA Press}}, title = {{{Configurable Processor Architectures: History and Trends}}}, year = {{2010}}, } @proceedings{2222, editor = {{Plaks, Toomas P. and Andrews, David and DeMara, Ronald and Lam, Herman and Lee, Jooheung and Plessl, Christian and Stitt, Greg}}, isbn = {{1-60132-140-6}}, publisher = {{CSREA Press}}, title = {{{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}}, year = {{2010}}, } @inproceedings{2226, author = {{Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, isbn = {{978-1-4244-6965-9}}, pages = {{65--72}}, publisher = {{IEEE Computer Society}}, title = {{{Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}}}, doi = {{10.1109/ASAP.2010.5540798}}, year = {{2010}}, } @inproceedings{2206, author = {{Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}}, booktitle = {{Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}}, isbn = {{978-1-4244-8864-3}}, pages = {{372--376}}, publisher = {{IEEE}}, title = {{{Reconfigurable Nodes for Future Networks}}}, doi = {{10.1109/GLOCOMW.2010.5700341}}, year = {{2010}}, } @inproceedings{2228, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}}, editor = {{Hammami, Omar and Larrabee, Sandra}}, title = {{{Performance Estimation for the Exploration of CPU-Accelerator Architectures}}}, year = {{2010}}, } @inproceedings{10639, author = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}}, booktitle = {{Proc. Technically Assisted Rehabilitation (TAR)}}, title = {{{Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}}}, year = {{2009}}, } @misc{10702, author = {{Kostin, Alexander}}, publisher = {{Paderborn University}}, title = {{{Evolvable Robot Controller}}}, year = {{2009}}, } @article{10703, author = {{Lübbers, Enno and Platzner, Marco}}, issn = {{1539-9087}}, journal = {{ACM Transactions on Embedded Computing Systems}}, keywords = {{Reconfigurable computing, multithreading, operating systems}}, number = {{1}}, pages = {{8:1--8:33}}, title = {{{ReconOS: Multithreaded Programming for Reconfigurable Computers}}}, doi = {{10.1145/1596532.1596540}}, volume = {{9}}, year = {{2009}}, } @misc{10746, author = {{Tofall, Martin}}, publisher = {{Paderborn University}}, title = {{{Compiler for a Custom Instruction Set CPU}}}, year = {{2009}}, } @misc{10749, author = {{Warkentin, Alexander}}, publisher = {{Paderborn University}}, title = {{{Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}}}, year = {{2009}}, } @misc{10753, author = {{Wildenhain, Benedikt}}, publisher = {{Paderborn University}}, title = {{{Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}}}, year = {{2009}}, } @inproceedings{10777, author = {{Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}}, booktitle = {{Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}}, pages = {{252--255}}, publisher = {{IEEE}}, title = {{{Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}}}, doi = {{10.1109/PRDC.2009.69}}, year = {{2009}}, } @inproceedings{13632, author = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}}, publisher = {{Springer}}, title = {{{A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}}}, year = {{2009}}, } @inproceedings{13634, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}}, title = {{{Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}}}, year = {{2009}}, } @inproceedings{13635, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}}, publisher = {{IEEE}}, title = {{{ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}}}, year = {{2009}}, } @inproceedings{13636, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }}, publisher = {{IEEE}}, title = {{{Cooperative Multithreading in Dynamically Reconfigurable Systems}}}, year = {{2009}}, }