@misc{15920, abstract = {{Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.}}, author = {{Keerthipati, Monica}}, publisher = {{Universität Paderborn}}, title = {{{A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}}}, year = {{2019}}, } @misc{14831, author = {{Sabu, Nithin S.}}, publisher = {{Paderborn University}}, title = {{{FPGA Acceleration of String Search Techniques in Huge Data Sets}}}, year = {{2019}}, } @misc{15946, author = {{Mehta, Jinay}}, title = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip}}}, year = {{2019}}, } @misc{14546, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}}}, year = {{2019}}, } @inproceedings{31067, author = {{Guettatfi, Zakarya and Platzner, Marco and Kermia, Omar and Khouas, Abdelhakim}}, booktitle = {{2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, publisher = {{IEEE}}, title = {{{An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}}}, doi = {{10.1109/ipdpsw.2019.00027}}, year = {{2019}}, } @inproceedings{9913, abstract = {{Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.}}, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Applied Reconfigurable Computing}}, editor = {{Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}}, isbn = {{978-3-030-17227-5}}, location = {{Darmstadt, Germany}}, pages = {{127--136}}, publisher = {{Springer International Publishing}}, title = {{{Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}}}, doi = {{10.1007/978-3-030-17227-5_10}}, volume = {{11444}}, year = {{2019}}, } @misc{15874, author = {{Lienen, Christian}}, publisher = {{Universität Paderborn}}, title = {{{Implementing a Real-time System on a Platform FPGA operated with ReconOS}}}, year = {{2019}}, } @article{12871, author = {{Platzner, Marco and Plessl, Christian}}, issn = {{0170-6012}}, journal = {{Informatik Spektrum}}, title = {{{FPGAs im Rechenzentrum}}}, doi = {{10.1007/s00287-019-01187-w}}, year = {{2019}}, } @misc{52478, author = {{Mehta, Jinay D}}, title = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}}}, year = {{2019}}, } @inproceedings{3362, abstract = {{Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node.}}, author = {{Lösch, Achim and Wiens, Alex and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}}, isbn = {{9783319776095}}, issn = {{0302-9743}}, pages = {{73--84}}, publisher = {{Springer International Publishing}}, title = {{{Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}}}, doi = {{10.1007/978-3-319-77610-1_6}}, volume = {{10793}}, year = {{2018}}, } @misc{3365, author = {{Schnuer, Jan-Philip}}, publisher = {{Universität Paderborn}}, title = {{{Static Scheduling Algorithms for Heterogeneous Compute Nodes}}}, year = {{2018}}, } @misc{3366, author = {{Croce, Marcel}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation of OpenCL-based Compilation for FPGAs}}}, year = {{2018}}, } @inproceedings{3373, abstract = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}}, author = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}}, booktitle = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}}, isbn = {{9783319788890}}, issn = {{0302-9743}}, location = {{Santorini, Greece}}, pages = {{153--165}}, publisher = {{Springer International Publishing}}, title = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}}, doi = {{10.1007/978-3-319-78890-6_13}}, volume = {{10824}}, year = {{2018}}, } @unpublished{3586, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, booktitle = {{Third Workshop on Approximate Computing (AxC 2018)}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{6}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, year = {{2018}}, } @phdthesis{3720, abstract = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}}, author = {{Ho, Nam}}, pages = {{139}}, publisher = {{Universität Paderborn}}, title = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}}, doi = {{10.17619/UNIPB/1-376}}, year = {{2018}}, } @unpublished{1165, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{4th Workshop On Approximate Computing (WAPCO 2018)}}, title = {{{Making the Case for Proof-carrying Approximate Circuits}}}, year = {{2018}}, } @inproceedings{5547, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, isbn = {{9781538674796}}, location = {{Milan, Italy}}, publisher = {{IEEE}}, title = {{{A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}}}, doi = {{10.1109/asap.2018.8445098}}, year = {{2018}}, } @inproceedings{10598, abstract = {{Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints.}}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}}, keywords = {{Approximate computing, High-level synthesis, Accuracy, Monte-Carlo tree search, Circuit simulation}}, pages = {{219--224}}, title = {{{An MCTS-based Framework for Synthesis of Approximate Circuits}}}, doi = {{10.1109/VLSI-SoC.2018.8645026}}, year = {{2018}}, } @misc{10782, author = {{Clausing, Lennart}}, publisher = {{Ruhr-University Bochum}}, title = {{{Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}}}, year = {{2018}}, } @misc{1097, author = {{Jentzsch, Felix Paul}}, keywords = {{Approximate Computing, Proof-Carrying Hardware, Formal Verification}}, publisher = {{Universität Paderborn}}, title = {{{Enforcing IP Core Connection Properties with Verifiable Security Monitors}}}, year = {{2018}}, } @article{12965, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}}, issn = {{2169-3536}}, journal = {{IEEE Access}}, pages = {{14078--14092}}, title = {{{R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}}}, doi = {{10.1109/access.2018.2799852}}, year = {{2018}}, } @misc{3580, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{An FPGA Accelerator for Checking Resolution Proofs}}}, year = {{2017}}, } @misc{1157, author = {{Witschen, Linus Matthias}}, publisher = {{Universität Paderborn}}, title = {{{A Framework for the Synthesis of Approximate Circuits}}}, year = {{2017}}, } @misc{74, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}}}, year = {{2017}}, } @article{9919, abstract = {{This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.}}, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, keywords = {{Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations}}, pages = {{287--299}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, doi = {{10.1016/j.ijepes.2017.07.007}}, volume = {{94}}, year = {{2017}}, } @inproceedings{65, abstract = {{Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.}}, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, title = {{{reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}}}, doi = {{10.1109/ASAP.2017.7995272}}, year = {{2017}}, } @article{68, abstract = {{Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.}}, author = {{Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{ACM Transactions on Design Automation of Electronic Systems}}, number = {{4}}, pages = {{61:1----61:23}}, publisher = {{ACM}}, title = {{{Proof-Carrying Hardware via Inductive Invariants}}}, doi = {{10.1145/3054743}}, year = {{2017}}, } @article{10600, author = {{H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, title = {{{The First 25 Years of the FPL Conference – Significant Papers}}}, doi = {{10.1145/2996468}}, year = {{2017}}, } @article{10601, author = {{F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}}, journal = {{IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}}, title = {{{Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}}}, doi = {{10.1109/TETC.2016.2641599}}, year = {{2017}}, } @article{10611, author = {{Anwer, Jahanzeb and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, pages = {{160--172}}, publisher = {{Elsevier}}, title = {{{Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}}}, doi = {{10.1016/j.micpro.2017.06.002}}, year = {{2017}}, } @misc{10613, author = {{Kaltschmidt, Christian}}, publisher = {{Paderborn University}}, title = {{{An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}}}, year = {{2017}}, } @inproceedings{10630, author = {{Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, title = {{{A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}}}, doi = {{10.23919/DATE.2017.7927137}}, year = {{2017}}, } @misc{10666, author = {{Riaz, Umair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of Industrial Analytics Functions on a Platform FPGA}}}, year = {{2017}}, } @inproceedings{10672, author = {{Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, title = {{{Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}}}, doi = {{10.23919/DATE.2017.7927096}}, year = {{2017}}, } @inproceedings{10676, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2017 International Conference on Field Programmable Technology (ICFPT)}}, keywords = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}}, pages = {{215--218}}, title = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}}, doi = {{10.1109/FPT.2017.8280144}}, year = {{2017}}, } @article{10692, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, year = {{2017}}, } @misc{10708, author = {{Dietrich, Andreas}}, publisher = {{Paderborn University}}, title = {{{Reconfigurable Cryptographic Services}}}, year = {{2017}}, } @article{10740, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{The Journal of Engineering}}, pages = {{19pp}}, title = {{{Fast Network Restoration by Partitioning of Parallel Black Start Zones}}}, doi = {{10.1049/joe.2017.0032}}, year = {{2017}}, } @book{10759, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 20th European Conference, EvoApplications}}}, year = {{2017}}, } @inproceedings{10760, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}}, publisher = {{Springer International Publishing}}, title = {{{Parametrizing Cartesian Genetic Programming: An Empirical Study}}}, doi = {{10.1007/978-3-319-67190-1_26}}, year = {{2017}}, } @inproceedings{10761, author = {{Kaufmann, Paul and Ho, Nam and Platzner, Marco}}, booktitle = {{Adaptive Hardware and Systems (AHS)}}, publisher = {{IEEE}}, title = {{{Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}}}, doi = {{10.1109/AHS.2017.8046380}}, year = {{2017}}, } @inproceedings{10762, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{Genetic and Evolutionary Computation (GECCO), Compendium}}, publisher = {{ACM}}, title = {{{An Empirical Study on the Parametrization of Cartesian Genetic Programming}}}, doi = {{10.1145/3067695.3075980}}, year = {{2017}}, } @inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{14893, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Communications in Computer and Information Science}}, isbn = {{9783319625683}}, issn = {{1865-0929}}, publisher = {{Springer }}, title = {{{I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}}}, doi = {{10.1007/978-3-319-62569-0_8}}, year = {{2017}}, } @article{222, abstract = {{Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, journal = {{Computers & Electrical Engineering}}, pages = {{112----122}}, publisher = {{Elsevier}}, title = {{{An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}}}, doi = {{10.1016/j.compeleceng.2016.04.005}}, year = {{2016}}, } @inproceedings{5812, author = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}}, booktitle = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{9781467394062}}, publisher = {{IEEE}}, title = {{{FPGA-based acceleration of high density myoelectric signal processing}}}, doi = {{10.1109/reconfig.2015.7393312}}, year = {{2016}}, } @misc{10612, author = {{Cedric Mertens, Jan}}, publisher = {{Paderborn University}}, title = {{{Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion}}}, year = {{2016}}, } @misc{10616, author = {{Nassery, Abdul Sami}}, publisher = {{Paderborn University}}, title = {{{Implementation of Bilinear Pairings on Reconfigurable Hardware}}}, year = {{2016}}, } @misc{10617, author = {{Amin, Omair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}}}, year = {{2016}}, } @inproceedings{10622, author = {{Anwer, Jahanzeb and Platzner, Marco}}, booktitle = {{Euromicro Conference on Digital System Design (DSD)}}, title = {{{Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}}}, doi = {{10.1109/DSD.2016.35}}, year = {{2016}}, }