@article{12967,
  abstract     = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}},
  author       = {{Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}},
  issn         = {{1939-8018}},
  journal      = {{Journal of Signal Processing Systems}},
  number       = {{11}},
  pages        = {{1259 -- 1272}},
  title        = {{{An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}}},
  doi          = {{10.1007/s11265-018-1435-y}},
  volume       = {{91}},
  year         = {{2019}},
}

@inproceedings{15422,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{World Congress on Nature and Biologically Inspired Computing (NaBIC)}},
  publisher    = {{Springer}},
  title        = {{{Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}}},
  year         = {{2019}},
}

@misc{15883,
  author       = {{Kumar Jeyakumar, Shankar}},
  title        = {{{Incremental learning with Support Vector Machine on embedded platforms}}},
  year         = {{2019}},
}

@misc{15920,
  abstract     = {{Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime.
Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs.
This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.}},
  author       = {{Keerthipati, Monica}},
  publisher    = {{Universität Paderborn}},
  title        = {{{A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}}},
  year         = {{2019}},
}

@misc{14831,
  author       = {{Sabu, Nithin S.}},
  publisher    = {{Paderborn University}},
  title        = {{{FPGA Acceleration of String Search Techniques in Huge Data Sets}}},
  year         = {{2019}},
}

@misc{15946,
  author       = {{Mehta, Jinay}},
  title        = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip}}},
  year         = {{2019}},
}

@misc{14546,
  author       = {{Hansmeier, Tim}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}}},
  year         = {{2019}},
}

@inproceedings{31067,
  author       = {{Guettatfi, Zakarya and Platzner, Marco and Kermia, Omar and Khouas, Abdelhakim}},
  booktitle    = {{2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}},
  publisher    = {{IEEE}},
  title        = {{{An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}}},
  doi          = {{10.1109/ipdpsw.2019.00027}},
  year         = {{2019}},
}

@misc{52478,
  author       = {{Mehta, Jinay D}},
  title        = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}}},
  year         = {{2019}},
}

@inproceedings{9913,
  abstract     = {{Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.}},
  author       = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}},
  booktitle    = {{Applied Reconfigurable Computing}},
  editor       = {{Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}},
  isbn         = {{978-3-030-17227-5}},
  location     = {{Darmstadt, Germany}},
  pages        = {{127--136}},
  publisher    = {{Springer International Publishing}},
  title        = {{{Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}}},
  doi          = {{10.1007/978-3-030-17227-5_10}},
  volume       = {{11444}},
  year         = {{2019}},
}

@misc{15874,
  author       = {{Lienen, Christian}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Implementing a Real-time System on a Platform FPGA operated with ReconOS}}},
  year         = {{2019}},
}

@article{12871,
  author       = {{Platzner, Marco and Plessl, Christian}},
  issn         = {{0170-6012}},
  journal      = {{Informatik Spektrum}},
  title        = {{{FPGAs im Rechenzentrum}}},
  doi          = {{10.1007/s00287-019-01187-w}},
  year         = {{2019}},
}

@inproceedings{3362,
  abstract     = {{Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node.}},
  author       = {{Lösch, Achim and Wiens, Alex and Platzner, Marco}},
  booktitle    = {{Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}},
  isbn         = {{9783319776095}},
  issn         = {{0302-9743}},
  pages        = {{73--84}},
  publisher    = {{Springer International Publishing}},
  title        = {{{Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}}},
  doi          = {{10.1007/978-3-319-77610-1_6}},
  volume       = {{10793}},
  year         = {{2018}},
}

@misc{3365,
  author       = {{Schnuer, Jan-Philip}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Static Scheduling Algorithms for Heterogeneous Compute Nodes}}},
  year         = {{2018}},
}

@misc{3366,
  author       = {{Croce, Marcel}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Evaluation of OpenCL-based Compilation for FPGAs}}},
  year         = {{2018}},
}

@inproceedings{3373,
  abstract     = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}},
  author       = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}},
  booktitle    = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}},
  isbn         = {{9783319788890}},
  issn         = {{0302-9743}},
  location     = {{Santorini, Greece}},
  pages        = {{153--165}},
  publisher    = {{Springer International Publishing}},
  title        = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}},
  doi          = {{10.1007/978-3-319-78890-6_13}},
  volume       = {{10824}},
  year         = {{2018}},
}

@unpublished{3586,
  abstract     = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}},
  author       = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}},
  booktitle    = {{Third Workshop on Approximate Computing (AxC 2018)}},
  keywords     = {{Approximate Computing, Framework, Pareto Front, Accuracy}},
  pages        = {{6}},
  title        = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}},
  year         = {{2018}},
}

@phdthesis{3720,
  abstract     = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}},
  author       = {{Ho, Nam}},
  pages        = {{139}},
  publisher    = {{Universität Paderborn}},
  title        = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}},
  doi          = {{10.17619/UNIPB/1-376}},
  year         = {{2018}},
}

@unpublished{1165,
  author       = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}},
  booktitle    = {{4th Workshop On Approximate Computing (WAPCO 2018)}},
  title        = {{{Making the Case for Proof-carrying Approximate Circuits}}},
  year         = {{2018}},
}

@inproceedings{5547,
  author       = {{Lösch, Achim and Platzner, Marco}},
  booktitle    = {{2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}},
  isbn         = {{9781538674796}},
  location     = {{Milan, Italy}},
  publisher    = {{IEEE}},
  title        = {{{A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}}},
  doi          = {{10.1109/asap.2018.8445098}},
  year         = {{2018}},
}