@inproceedings{65, abstract = {{Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.}}, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, title = {{{reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}}}, doi = {{10.1109/ASAP.2017.7995272}}, year = {{2017}}, } @article{68, abstract = {{Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.}}, author = {{Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{ACM Transactions on Design Automation of Electronic Systems}}, number = {{4}}, pages = {{61:1----61:23}}, publisher = {{ACM}}, title = {{{Proof-Carrying Hardware via Inductive Invariants}}}, doi = {{10.1145/3054743}}, year = {{2017}}, } @article{10600, author = {{H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, title = {{{The First 25 Years of the FPL Conference – Significant Papers}}}, doi = {{10.1145/2996468}}, year = {{2017}}, } @article{10601, author = {{F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}}, journal = {{IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}}, title = {{{Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}}}, doi = {{10.1109/TETC.2016.2641599}}, year = {{2017}}, } @article{10611, author = {{Anwer, Jahanzeb and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, pages = {{160--172}}, publisher = {{Elsevier}}, title = {{{Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}}}, doi = {{10.1016/j.micpro.2017.06.002}}, year = {{2017}}, } @misc{10613, author = {{Kaltschmidt, Christian}}, publisher = {{Paderborn University}}, title = {{{An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}}}, year = {{2017}}, } @inproceedings{10630, author = {{Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, title = {{{A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}}}, doi = {{10.23919/DATE.2017.7927137}}, year = {{2017}}, } @misc{10666, author = {{Riaz, Umair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of Industrial Analytics Functions on a Platform FPGA}}}, year = {{2017}}, } @inproceedings{10672, author = {{Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, title = {{{Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}}}, doi = {{10.23919/DATE.2017.7927096}}, year = {{2017}}, } @inproceedings{10676, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2017 International Conference on Field Programmable Technology (ICFPT)}}, keywords = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}}, pages = {{215--218}}, title = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}}, doi = {{10.1109/FPT.2017.8280144}}, year = {{2017}}, } @article{10692, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, year = {{2017}}, } @misc{10708, author = {{Dietrich, Andreas}}, publisher = {{Paderborn University}}, title = {{{Reconfigurable Cryptographic Services}}}, year = {{2017}}, } @article{10740, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{The Journal of Engineering}}, pages = {{19pp}}, title = {{{Fast Network Restoration by Partitioning of Parallel Black Start Zones}}}, doi = {{10.1049/joe.2017.0032}}, year = {{2017}}, } @book{10759, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 20th European Conference, EvoApplications}}}, year = {{2017}}, } @inproceedings{10760, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}}, publisher = {{Springer International Publishing}}, title = {{{Parametrizing Cartesian Genetic Programming: An Empirical Study}}}, doi = {{10.1007/978-3-319-67190-1_26}}, year = {{2017}}, } @inproceedings{10761, author = {{Kaufmann, Paul and Ho, Nam and Platzner, Marco}}, booktitle = {{Adaptive Hardware and Systems (AHS)}}, publisher = {{IEEE}}, title = {{{Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}}}, doi = {{10.1109/AHS.2017.8046380}}, year = {{2017}}, } @inproceedings{10762, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{Genetic and Evolutionary Computation (GECCO), Compendium}}, publisher = {{ACM}}, title = {{{An Empirical Study on the Parametrization of Cartesian Genetic Programming}}}, doi = {{10.1145/3067695.3075980}}, year = {{2017}}, } @inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{14893, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Communications in Computer and Information Science}}, isbn = {{9783319625683}}, issn = {{1865-0929}}, publisher = {{Springer }}, title = {{{I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}}}, doi = {{10.1007/978-3-319-62569-0_8}}, year = {{2017}}, } @article{222, abstract = {{Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, journal = {{Computers & Electrical Engineering}}, pages = {{112----122}}, publisher = {{Elsevier}}, title = {{{An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}}}, doi = {{10.1016/j.compeleceng.2016.04.005}}, year = {{2016}}, }