@misc{10707, author = {{Ibne Ashraf, Ishraq}}, publisher = {{Paderborn University}}, title = {{{Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}}}, year = {{2016}}, } @inproceedings{10712, author = {{Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}}, pages = {{1--8}}, title = {{{Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}}}, doi = {{10.1109/ReConFig.2016.7857193}}, year = {{2016}}, } @misc{10755, author = {{Schmidt, Marco}}, publisher = {{Paderborn University}}, title = {{{Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}}}, year = {{2016}}, } @book{10758, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 19th European Conference, EvoApplications}}}, volume = {{9597}}, year = {{2016}}, } @inproceedings{10766, author = {{Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Proceedings of the 30th European Simulation and Modelling Conference (ESM)}}, title = {{{RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}}}, year = {{2016}}, } @inproceedings{10768, author = {{Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}}, pages = {{185--195}}, title = {{{New Co-design Methodology for Real-time Embedded Systems}}}, year = {{2016}}, } @article{10769, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}, number = {{99}}, pages = {{1--1}}, publisher = {{IEEE}}, title = {{{Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}}}, doi = {{10.1109/TCAD.2016.2547908}}, volume = {{PP}}, year = {{2016}}, } @misc{10781, author = {{Hermansen, Sven}}, publisher = {{Paderborn University}}, title = {{{Custom Memory Controller for ReconOS}}}, year = {{2016}}, } @book{12972, abstract = {{Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering.}}, editor = {{Lewis, Peter R. and Platzner, Marco and Rinner, Bernhard and Tørresen, Jim and Yao, Xin}}, isbn = {{9783319396743}}, issn = {{1619-7127}}, publisher = {{Springer}}, title = {{{Self-aware Computing Systems: An Engineering Approach}}}, doi = {{10.1007/978-3-319-39675-0}}, year = {{2016}}, } @inproceedings{15873, author = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}}, booktitle = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{9781467394062}}, keywords = {{Electromyography, Feature extraction, Delays, Hardware Pattern recognition, Prosthetics, High definition video}}, location = {{Mexiko City, Mexiko}}, publisher = {{IEEE}}, title = {{{FPGA-based acceleration of high density myoelectric signal processing}}}, doi = {{10.1109/reconfig.2015.7393312}}, year = {{2016}}, } @inproceedings{13151, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{Computer and Games}}, title = {{{Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}}}, year = {{2016}}, } @inproceedings{13152, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{IEEE Computational Intelligence and Games}}, title = {{{Monte-Carlo Simulation Balancing Revisited}}}, year = {{2016}}, } @inproceedings{132, abstract = {{Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.}}, author = {{Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}}, pages = {{1----8}}, title = {{{Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}}}, doi = {{10.1109/ReCoSoC.2016.7533910}}, year = {{2016}}, } @inbook{29, abstract = {{In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.}}, author = {{Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}}, booktitle = {{FPGAs for Software Programmers}}, editor = {{Koch, Dirk and Hannig, Frank and Ziener, Daniel}}, isbn = {{978-3-319-26406-6}}, pages = {{227--244}}, publisher = {{Springer International Publishing}}, title = {{{ReconOS}}}, doi = {{10.1007/978-3-319-26408-0_13}}, year = {{2016}}, } @inbook{156, abstract = {{Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Self-aware Computing Systems}}, pages = {{145--165}}, publisher = {{Springer International Publishing}}, title = {{{Self-aware Compute Nodes}}}, doi = {{10.1007/978-3-319-39675-0_8}}, year = {{2016}}, } @inproceedings{168, abstract = {{The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.}}, author = {{Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}}, pages = {{912--917}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}}}, year = {{2016}}, } @inproceedings{269, abstract = {{Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.}}, author = {{Wiersema, Tobias and Wu, Sen and Platzner, Marco}}, booktitle = {{Proceedings of the International Symposium in Reconfigurable Computing (ARC)}}, pages = {{365----372}}, title = {{{On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}}}, doi = {{10.1007/978-3-319-16214-0_32}}, year = {{2015}}, } @misc{3364, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}}}, year = {{2015}}, } @article{1772, author = {{Torresen, Jim and Plessl, Christian and Yao, Xin}}, journal = {{IEEE Computer}}, keywords = {{self-awareness, self-expression}}, number = {{7}}, pages = {{18--20}}, publisher = {{IEEE Computer Society}}, title = {{{Self-Aware and Self-Expressive Systems – Guest Editor's Introduction}}}, doi = {{10.1109/MC.2015.205}}, volume = {{48}}, year = {{2015}}, } @misc{10615, author = {{Ahmed, Abdullah Fathi}}, publisher = {{Paderborn University}}, title = {{{Self-Optimizing Organic Cache}}}, year = {{2015}}, }