@inproceedings{238, abstract = {{In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.}}, author = {{Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}}, pages = {{1078--1083}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Transparent offloading of computational hotspots from binary code to Xeon Phi}}}, doi = {{10.7873/DATE.2015.1124}}, year = {{2015}}, } @inproceedings{347, abstract = {{Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead.}}, author = {{Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}}, editor = {{Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, Koen}}, pages = {{283--290}}, publisher = {{Springer}}, title = {{{Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}}}, doi = {{10.1007/978-3-319-05960-0_30}}, year = {{2014}}, } @inproceedings{1782, author = {{Graf, Tobias and Schaefers, Lars and Platzner, Marco}}, booktitle = {{Proc. Conf. on Computers and Games (CG)}}, number = {{8427}}, pages = {{14--25}}, publisher = {{Springer}}, title = {{{On Semeai Detection in Monte-Carlo Go}}}, doi = {{10.1007/978-3-319-09165-5_2}}, year = {{2014}}, } @inproceedings{399, abstract = {{Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.}}, author = {{Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Field-Programmable Technology (FPT)}}, pages = {{167--174}}, title = {{{Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}}}, doi = {{10.1109/FPT.2014.7082771}}, year = {{2014}}, } @inproceedings{408, abstract = {{Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.}}, author = {{Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}}, booktitle = {{Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}}, editor = {{Albert, Elvira and Sekerinski, Emil}}, pages = {{307--322}}, title = {{{Integrating Software and Hardware Verification}}}, doi = {{10.1007/978-3-319-10181-1_19}}, year = {{2014}}, } @inproceedings{433, abstract = {{Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--6 }}, title = {{{Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}}}, doi = {{10.1109/ReConFig.2014.7032514}}, year = {{2014}}, } @article{10602, author = {{Schaefers, Lars and Platzner, Marco}}, journal = {{IEEE Transactions on Computational Intelligence and AI in Games}}, number = {{3}}, pages = {{361--374}}, title = {{{A Novel Technique and its Application to Computer Go}}}, doi = {{10.1109/TCIAIG.2014.2346997}}, volume = {{6}}, year = {{2014}}, } @article{10603, author = {{Giefers, Heiner and Platzner, Marco}}, journal = {{IEEE Transactions on Computers}}, number = {{12}}, pages = {{2919 -- 2932}}, title = {{{An FPGA-based Reconfigurable Mesh Many-Core}}}, doi = {{10.1109/TC.2013.174}}, volume = {{63}}, year = {{2014}}, } @inproceedings{10621, author = {{Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}}, booktitle = {{Reconfigurable Architectures Workshop (RAW)}}, title = {{{FPGA Redundancy Configurations: An Automated Design Space Exploration}}}, doi = {{10.1109/IPDPSW.2014.37}}, year = {{2014}}, } @misc{10627, author = {{Bockhorn, Arne}}, publisher = {{Paderborn University}}, title = {{{Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}}}, year = {{2014}}, } @inproceedings{10632, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. MyoElectric Controls Symposium (MEC)}}, title = {{{A computer vision-based approach to high density EMG pattern recognition using structural similarity}}}, year = {{2014}}, } @inproceedings{10633, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity}}}, year = {{2014}}, } @misc{10640, author = {{Brand, Marcel}}, publisher = {{Paderborn University}}, title = {{{A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}}}, year = {{2014}}, } @misc{10645, author = {{Damschen, Marvin}}, publisher = {{Paderborn University}}, title = {{{Easy-to-use-on-the-fly binary program acceleration on many-cores}}}, year = {{2014}}, } @inproceedings{10654, author = {{Glette, Kyrre and Kaufmann, Paul}}, booktitle = {{IEEE Congress on Evolutionary Computation (CEC)}}, title = {{{Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System}}}, year = {{2014}}, } @misc{10665, author = {{Hagedorn, Christoph}}, publisher = {{Paderborn University}}, title = {{{Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}}}, year = {{2014}}, } @inproceedings{10674, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}}, pages = {{1--4}}, title = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}}, doi = {{10.1109/FPL.2014.6927437}}, year = {{2014}}, } @inproceedings{10677, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}}, keywords = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}}, pages = {{31--37}}, title = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}}, doi = {{10.1109/ICES.2014.7008719}}, year = {{2014}}, } @misc{10679, author = {{König, Fabian}}, publisher = {{Paderborn University}}, title = {{{EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}}}, year = {{2014}}, } @misc{10701, author = {{Koch, Benjamin}}, publisher = {{Paderborn University}}, title = {{{Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}}}, year = {{2014}}, }