@misc{10727, author = {{Pudelko, Daniel}}, publisher = {{Paderborn University}}, title = {{{Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs}}}, year = {{2013}}, } @misc{10730, author = {{Riebler, Heinrich}}, publisher = {{Paderborn University}}, title = {{{Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}}}, year = {{2013}}, } @misc{10741, author = {{Sprenger, Alexander}}, publisher = {{Paderborn University}}, title = {{{MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung}}}, year = {{2013}}, } @misc{10743, author = {{Steppeler, Philipp}}, publisher = {{Paderborn University}}, title = {{{Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen}}}, year = {{2013}}, } @inproceedings{10745, author = {{Toebermann, Christian and Geibel, Daniel and Hau, Manuel and Brandl, Ron and Kaufmann, Paul and Ma, Chenjie and Braun, Martin and Degner, Tobias}}, booktitle = {{Real-Time Conference}}, publisher = {{OPAL RT Paris}}, title = {{{Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation}}}, year = {{2013}}, } @inproceedings{10774, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}}, booktitle = {{2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)}}, pages = {{83--88}}, publisher = {{IEEE}}, title = {{{A fast TCAD-based methodology for Variation analysis of emerging nano-devices}}}, doi = {{10.1109/DFT.2013.6653587}}, year = {{2013}}, } @inproceedings{10775, author = {{Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}}, booktitle = {{2013 14th Latin American Test Workshop-LATW}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}}}, doi = {{10.1109/LATW.2013.6562673}}, year = {{2013}}, } @inproceedings{13645, author = {{Graf, Tobias and Schäfers, Lars and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Computers and Games (CG)}}, publisher = {{Springer}}, title = {{{On Semeai Detection in Monte-Carlo Go.}}}, year = {{2013}}, } @inproceedings{528, abstract = {{Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.}}, author = {{Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field-Programmable Technology (FPT)}}, keywords = {{coldboot}}, pages = {{386--389}}, publisher = {{IEEE}}, title = {{{FPGA-accelerated Key Search for Cold-Boot Attacks against AES}}}, doi = {{10.1109/FPT.2013.6718394}}, year = {{2013}}, } @inproceedings{505, abstract = {{In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.}}, author = {{Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}}, booktitle = {{Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}}, publisher = {{IEEE}}, title = {{{On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}}}, doi = {{10.1109/ISORC.2013.6913232}}, year = {{2013}}, } @inproceedings{1787, author = {{Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}}, isbn = {{978-0-7695-4979-8}}, pages = {{64--73}}, publisher = {{IEEE Computer Society}}, title = {{{Parallel Macro Pipelining on the Intel SCC Many-Core Computer}}}, doi = {{10.1109/IPDPSW.2013.136}}, year = {{2013}}, } @inproceedings{2097, author = {{Kasap, Server and Redif, Soydan}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, pages = {{135--140}}, publisher = {{IEEE Computer Society}}, title = {{{FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}}}, doi = {{10.1109/FPT.2012.6412125}}, year = {{2012}}, } @inproceedings{2100, author = {{Kasap, Server and Redif, Soydan}}, booktitle = {{Int. Architecture and Engineering Symp. (ARCHENG)}}, title = {{{FPGA implementation of a second-order convolutive blind signal separation algorithm}}}, year = {{2012}}, } @inproceedings{2103, author = {{Wistuba, Martin and Schaefers, Lars and Platzner, Marco}}, booktitle = {{Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}}, pages = {{91--99}}, publisher = {{IEEE}}, title = {{{Comparison of Bayesian Move Prediction Systems for Computer Go}}}, doi = {{10.1109/CIG.2012.6374143}}, year = {{2012}}, } @article{2172, author = {{Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}}, journal = {{Physics in Medicine and Biology}}, number = {{4}}, pages = {{867--883}}, publisher = {{IOP Publishing}}, title = {{{STIR: Software for Tomographic Image Reconstruction Release 2}}}, doi = {{10.1088/0031-9155/57/4/867}}, volume = {{57}}, year = {{2012}}, } @article{2173, author = {{Redif, Soydan and Kasap, Server}}, journal = {{Int. Journal of Electronics}}, number = {{12}}, pages = {{1646--1651}}, publisher = {{Taylor & Francis}}, title = {{{Parallel algorithm for computation of second-order sequential best rotations}}}, doi = {{10.1080/00207217.2012.751343}}, volume = {{100}}, year = {{2012}}, } @article{2174, author = {{Kasap, Server and Benkrid, Khaled}}, journal = {{Journal of Computers}}, number = {{6}}, pages = {{1312--1328}}, publisher = {{Academy Publishers}}, title = {{{Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}}}, volume = {{7}}, year = {{2012}}, } @phdthesis{586, abstract = {{FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.}}, author = {{Drzevitzky, Stephanie}}, pages = {{114}}, publisher = {{Universität Paderborn}}, title = {{{Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}}}, year = {{2012}}, } @misc{587, author = {{Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}}, publisher = {{Awareness Magazine}}, title = {{{Programming models for reconfigurable heterogeneous multi-cores}}}, year = {{2012}}, } @inproceedings{10636, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}}}, year = {{2012}}, }