@inproceedings{2193, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, pages = {{223--226}}, publisher = {{IEEE Computer Society}}, title = {{{Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}}}, doi = {{10.1109/ASAP.2011.6043273}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @article{2201, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, journal = {{Int. Journal of Recon- figurable Computing (IJRC)}}, keywords = {{funding-altera}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}}}, doi = {{10.1155/2011/760954}}, year = {{2011}}, } @inproceedings{2198, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Reconfigurable Architectures Workshop (RAW)}}, pages = {{278--285}}, publisher = {{IEEE Computer Society}}, title = {{{Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}}}, doi = {{10.1109/IPDPS.2011.153}}, year = {{2011}}, } @article{10605, author = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}}, journal = {{International Journal of Reconfigurable Computing}}, publisher = {{Hindawi Publishing Corporation}}, title = {{{Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}}}, doi = {{10.1155/2010/180242}}, volume = {{2010}}, year = {{2010}}, } @misc{10614, author = {{Agne, Andreas}}, publisher = {{Paderborn University}}, title = {{{Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}}}, year = {{2010}}, } @misc{10629, author = {{Boschmann, Alexander}}, publisher = {{Paderborn University}}, title = {{{EMG-basierte Ganganalyse}}}, year = {{2010}}, } @misc{10642, author = {{Breitlauch, Daniel}}, publisher = {{Paderborn University}}, title = {{{Evolvable Cache Controller}}}, year = {{2010}}, } @misc{10649, author = {{Dridger, Denis}}, publisher = {{Paderborn University}}, title = {{{Soft Microprocessors with tightly coupled Application-Specific Coprocessors}}}, year = {{2010}}, } @misc{10657, author = {{Graf, Tobias}}, publisher = {{Paderborn University}}, title = {{{Parallelization of the UCT Algorithm on HPC-Clusters}}}, year = {{2010}}, } @inproceedings{10683, author = {{Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}}, booktitle = {{International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}}, pages = {{6357--6360}}, publisher = {{IEEE}}, title = {{{Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}}}, year = {{2010}}, } @inproceedings{10686, author = {{Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}}, booktitle = {{IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}}, pages = {{541--548}}, publisher = {{IEEE}}, title = {{{A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}}}, year = {{2010}}, } @article{10694, author = {{Kebschull, Udo and Platzner, Marco and Teich, Jürgen}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, number = {{3}}, pages = {{157--158}}, title = {{{Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}}}, doi = {{10.1049/iet-cdt.2010.9044}}, volume = {{4}}, year = {{2010}}, } @misc{10697, author = {{Knieper, Tobias}}, publisher = {{Paderborn University}}, title = {{{Hybridization of Global Multi-Objective and Local Search Techniques}}}, year = {{2010}}, } @inproceedings{10699, author = {{Knieper, Tobias and Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{250--261}}, publisher = {{Springer}}, title = {{{Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture}}}, volume = {{6274}}, year = {{2010}}, } @inbook{10704, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}}, editor = {{Platzner, Marco and Teich, Jürgen and Wehn, Norbert}}, pages = {{269--290}}, publisher = {{Springer-Verlag GmbH}}, title = {{{ReconOS: An Operating System for Dynamically Reconfigurable Hardware}}}, doi = {{10.1007/978-90-481-3485-4_13}}, year = {{2010}}, } @misc{10710, author = {{Meiche, Robert}}, publisher = {{Paderborn University}}, title = {{{FPGA/CPU Multicore-Plattform für ReconOS/eCos}}}, year = {{2010}}, } @misc{10717, author = {{Niekamp, Manuel}}, publisher = {{Paderborn University}}, title = {{{Transparente Hardwarebeschleunigung durch Shared Library Interposing}}}, year = {{2010}}, } @misc{10731, author = {{Runde, Bodo}}, publisher = {{Paderborn University}}, title = {{{A Token-Ring Network-On-Chip for Message Passing in ReconOS}}}, year = {{2010}}, }