@proceedings{2222,
  editor       = {{Plaks, Toomas P. and Andrews, David and DeMara, Ronald and Lam, Herman and Lee, Jooheung and Plessl, Christian and Stitt, Greg}},
  isbn         = {{1-60132-140-6}},
  publisher    = {{CSREA Press}},
  title        = {{{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}},
  year         = {{2010}},
}

@inproceedings{2226,
  author       = {{Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}},
  booktitle    = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}},
  isbn         = {{978-1-4244-6965-9}},
  pages        = {{65--72}},
  publisher    = {{IEEE Computer Society}},
  title        = {{{Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}}},
  doi          = {{10.1109/ASAP.2010.5540798}},
  year         = {{2010}},
}

@inproceedings{2206,
  author       = {{Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}},
  booktitle    = {{Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}},
  isbn         = {{978-1-4244-8864-3}},
  pages        = {{372--376}},
  publisher    = {{IEEE}},
  title        = {{{Reconfigurable Nodes for Future Networks}}},
  doi          = {{10.1109/GLOCOMW.2010.5700341}},
  year         = {{2010}},
}

@inproceedings{2228,
  author       = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}},
  booktitle    = {{Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}},
  editor       = {{Hammami, Omar and Larrabee, Sandra}},
  title        = {{{Performance Estimation for the Exploration of CPU-Accelerator Architectures}}},
  year         = {{2010}},
}

@inproceedings{10639,
  author       = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}},
  booktitle    = {{Proc. Technically Assisted Rehabilitation (TAR)}},
  title        = {{{Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}}},
  year         = {{2009}},
}

@misc{10702,
  author       = {{Kostin, Alexander}},
  publisher    = {{Paderborn University}},
  title        = {{{Evolvable Robot Controller}}},
  year         = {{2009}},
}

@article{10703,
  author       = {{Lübbers, Enno and Platzner, Marco}},
  issn         = {{1539-9087}},
  journal      = {{ACM Transactions on Embedded Computing Systems}},
  keywords     = {{Reconfigurable computing, multithreading, operating systems}},
  number       = {{1}},
  pages        = {{8:1--8:33}},
  title        = {{{ReconOS: Multithreaded Programming for Reconfigurable Computers}}},
  doi          = {{10.1145/1596532.1596540}},
  volume       = {{9}},
  year         = {{2009}},
}

@misc{10746,
  author       = {{Tofall, Martin}},
  publisher    = {{Paderborn University}},
  title        = {{{Compiler for a Custom Instruction Set CPU}}},
  year         = {{2009}},
}

@misc{10749,
  author       = {{Warkentin, Alexander}},
  publisher    = {{Paderborn University}},
  title        = {{{Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}}},
  year         = {{2009}},
}

@misc{10753,
  author       = {{Wildenhain, Benedikt}},
  publisher    = {{Paderborn University}},
  title        = {{{Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}}},
  year         = {{2009}},
}

@inproceedings{10777,
  author       = {{Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}},
  booktitle    = {{Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}},
  pages        = {{252--255}},
  publisher    = {{IEEE}},
  title        = {{{Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}}},
  doi          = {{10.1109/PRDC.2009.69}},
  year         = {{2009}},
}

@inproceedings{13632,
  author       = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}},
  booktitle    = {{Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}},
  publisher    = {{Springer}},
  title        = {{{A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}}},
  year         = {{2009}},
}

@inproceedings{13634,
  author       = {{Giefers, Heiner and Platzner, Marco}},
  booktitle    = {{Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}},
  title        = {{{Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}}},
  year         = {{2009}},
}

@inproceedings{13635,
  author       = {{Giefers, Heiner and Platzner, Marco}},
  booktitle    = {{Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}},
  publisher    = {{IEEE}},
  title        = {{{ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}}},
  year         = {{2009}},
}

@inproceedings{13636,
  author       = {{Lübbers, Enno and Platzner, Marco}},
  booktitle    = {{Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }},
  publisher    = {{IEEE}},
  title        = {{{Cooperative Multithreading in Dynamically Reconfigurable Systems}}},
  year         = {{2009}},
}

@inproceedings{13637,
  author       = {{Giefers, Heiner and Platzner, Marco}},
  booktitle    = {{Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }},
  publisher    = {{IEEE}},
  title        = {{{Program-driven Fine-grained Power Management for the Reconfigurable Mesh}}},
  year         = {{2009}},
}

@inproceedings{13638,
  author       = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}},
  booktitle    = {{Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}},
  isbn         = {{9781424443758}},
  publisher    = {{IEEE}},
  title        = {{{An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}}},
  doi          = {{10.1109/fpt.2009.5377645}},
  year         = {{2009}},
}

@inproceedings{13639,
  author       = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}},
  booktitle    = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}},
  publisher    = {{IEEE}},
  title        = {{{Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}}},
  year         = {{2009}},
}

@inproceedings{2350,
  abstract     = {{Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. }},
  author       = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}},
  booktitle    = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}},
  isbn         = {{978-1-4244-4450-2}},
  keywords     = {{IMORC, interconnect, performance}},
  pages        = {{275--278}},
  publisher    = {{IEEE Computer Society}},
  title        = {{{IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}}},
  doi          = {{10.1109/FCCM.2009.25}},
  year         = {{2009}},
}

@inproceedings{2262,
  abstract     = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }},
  author       = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}},
  booktitle    = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}},
  keywords     = {{EvoCache, evolvable hardware, computer architecture}},
  pages        = {{11--18}},
  publisher    = {{IEEE Computer Society}},
  title        = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}},
  year         = {{2009}},
}