@inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2263, abstract = {{In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. }}, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-101-5}}, pages = {{319--322}}, publisher = {{CSREA Press}}, title = {{{Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}}}, year = {{2009}}, } @inproceedings{2358, author = {{Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}}, booktitle = {{IEEE Nuclear Science Symposium Conference Record (NSS)}}, pages = {{4161--4168}}, publisher = {{IEEE}}, title = {{{A method for OSEM PET reconstruction on parallel architectures using STIR}}}, doi = {{10.1109/NSSMIC.2008.4774198}}, year = {{2008}}, } @inproceedings{2365, author = {{Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{The GOmputer: Accelerating GO with FPGAs}}}, year = {{2008}}, } @misc{10628, author = {{Boschmann, Alexander}}, publisher = {{Paderborn University}}, title = {{{Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}}}, year = {{2008}}, } @misc{10641, author = {{Breitlauch, Daniel}}, publisher = {{Paderborn University}}, title = {{{Selbstoptimierender Cache-Kontroller}}}, year = {{2008}}, } @misc{10644, author = {{Ceylan, Toni and Yalcin, Coni}}, publisher = {{Paderborn University}}, title = {{{Verteilte Simulation von mobilen Robotern mit EyeSim}}}, year = {{2008}}, } @inproceedings{10653, author = {{Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}}, booktitle = {{IEEE Adaptive Hardware and Systems (AHS)}}, pages = {{32--39}}, publisher = {{IEEE}}, title = {{{Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}}}, year = {{2008}}, } @inproceedings{10656, author = {{Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{22--33}}, publisher = {{Springer}}, title = {{{A Comparison of Evolvable Hardware Architectures for Classification Tasks}}}, volume = {{5216}}, year = {{2008}}, } @misc{10669, author = {{Happe, Markus}}, publisher = {{Paderborn University}}, title = {{{Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}}}, year = {{2008}}, } @unpublished{10690, author = {{Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}}, title = {{{Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}}}, year = {{2008}}, } @inproceedings{10691, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Genetic and Evolutionary Computation (GECCO)}}, pages = {{1219 -- 1226}}, publisher = {{ACM Press}}, title = {{{Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}}}, year = {{2008}}, } @misc{10696, author = {{Knieper, Tobias}}, publisher = {{Paderborn University}}, title = {{{Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}}}, year = {{2008}}, } @misc{10718, author = {{Niklas, Jörg}}, publisher = {{Paderborn University}}, title = {{{Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}}}, year = {{2008}}, } @misc{10721, author = {{Östermann, Marco}}, publisher = {{Paderborn University}}, title = {{{Raytracing on a Custom Instruction Set CPU}}}, year = {{2008}}, } @misc{10751, author = {{Westerheide, Nico}}, publisher = {{Paderborn University}}, title = {{{Design and Evaluation of MicroBlaze Multi-core Architectures}}}, year = {{2008}}, } @inproceedings{10778, author = {{Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}}, booktitle = {{2008 International Conference on Microelectronics}}, pages = {{444--447}}, publisher = {{IEEE}}, title = {{{A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}}}, doi = {{10.1109/ICM.2008.5393497}}, year = {{2008}}, } @inproceedings{13629, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}}, publisher = {{IEEE}}, title = {{{Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}}}, year = {{2008}}, } @inproceedings{13630, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}}}, year = {{2008}}, }