@inproceedings{13631, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424419609}}, publisher = {{IEEE}}, title = {{{A portable abstraction layer for hardware threads}}}, doi = {{10.1109/fpl.2008.4629901}}, year = {{2008}}, } @inproceedings{2364, author = {{Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{A Hardware Accelerator for k-th Nearest Neighbor Thinning}}}, year = {{2008}}, } @inproceedings{2372, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Many-core and Reconfigurable Supercomputing Conference (MRSC)}}, keywords = {{IMORC, IP core, interconnect}}, title = {{{IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}}}, year = {{2008}}, } @inproceedings{10698, author = {{Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Biologically Inspired Collaborative Computing (BICC)}}, pages = {{213--222}}, publisher = {{Springer}}, title = {{{On Robust Evolution of Digital Hardware}}}, doi = {{10.1007/978-0-387-09655-1_19}}, volume = {{268}}, year = {{2008}}, } @inproceedings{6508, abstract = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}}, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}}, isbn = {{076952866X}}, keywords = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}}, location = {{Edinburgh, UK}}, pages = {{447--454}}, publisher = {{IEEE}}, title = {{{MOVES: A Modular Framework for Hardware Evolution}}}, doi = {{10.1109/ahs.2007.73}}, year = {{2007}}, } @misc{10623, author = {{Beisel, Tobias}}, publisher = {{Paderborn University}}, title = {{{Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}}}, year = {{2007}}, } @article{10625, author = {{Bergmann, Neil and Platzner, Marco and Teich, Jürgen}}, journal = {{{EURASIP} Journal on Embedded Systems}}, pages = {{1--2}}, publisher = {{Springer Science+Business Media}}, title = {{{Dynamically Reconfigurable Architectures (editorial)}}}, doi = {{10.1155/2007/28405}}, volume = {{2007}}, year = {{2007}}, } @misc{10643, author = {{Ceylan, Toni and Yalcin, Coni}}, publisher = {{Paderborn University}}, title = {{{Distributed Simulation of mobile Robots using EyeSim}}}, year = {{2007}}, } @article{10646, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, keywords = {{reconfigurable architectures, resource allocation, device reconfiguration time, dynamic hardware reconfiguration, dynamically reconfigurable hardware, light-weight runtime system, merge server distribute load, periodic real-time tasks, runtime system overheads, schedulability analysis, scheduling technique, server-based execution, synthesis tool flow}}, number = {{4}}, pages = {{295--302}}, title = {{{Server-based execution of periodic tasks on dynamically reconfigurable hardware}}}, doi = {{10.1049/iet-cdt:20060186}}, volume = {{1}}, year = {{2007}}, } @misc{10647, author = {{Defo, Bertrand}}, publisher = {{Paderborn University}}, title = {{{A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}}}, year = {{2007}}, } @misc{10648, author = {{Döhre, Sven}}, publisher = {{Paderborn University}}, title = {{{Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}}}, year = {{2007}}, } @inproceedings{10689, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Architecture of Computing Systems (ARCS)}}, pages = {{199--208}}, publisher = {{Springer}}, title = {{{Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}}}, volume = {{4415}}, year = {{2007}}, } @misc{10709, author = {{Meiche, Robert}}, publisher = {{Paderborn University}}, title = {{{VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}}}, year = {{2007}}, } @misc{10728, author = {{Reisch, Waldemar}}, publisher = {{Paderborn University}}, title = {{{Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}}}, year = {{2007}}, } @misc{10729, author = {{Rethmeier, Eike}}, publisher = {{Paderborn University}}, title = {{{Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}}}, year = {{2007}}, } @inproceedings{10735, author = {{Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}}, pages = {{749--756}}, publisher = {{IOS Press}}, title = {{{Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}}}, volume = {{15}}, year = {{2007}}, } @inproceedings{13627, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{A Many-Core Implementation Based on the Reconfigurable Mesh Model}}}, doi = {{10.1109/fpl.2007.4380623}}, year = {{2007}}, } @inproceedings{13628, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{ReconOS: An RTOS Supporting Hard-and Software Threads}}}, doi = {{10.1109/fpl.2007.4380686}}, year = {{2007}}, } @inproceedings{2401, abstract = {{ This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. }}, author = {{Plessl, Christian and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{temporal partitioning, retiming, ILP}}, pages = {{345--348}}, publisher = {{IEEE Computer Society}}, title = {{{Optimal Temporal Partitioning based on Slowdown and Retiming}}}, doi = {{10.1109/FPT.2006.270344}}, year = {{2006}}, } @inproceedings{10688, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}}, title = {{{Multi-objective Intrinsic Hardware Evolution}}}, year = {{2006}}, }