@misc{45916, author = {{Yadalam Murali Kumar, Nihal}}, publisher = {{Paderborn University}}, title = {{{Data Analytics for Predictive Maintenance of Time Series Data}}}, year = {{2023}}, } @inproceedings{64114, author = {{Ahmed, Qazi Arbab and Awais, Muhammad and Platzner, Marco}}, booktitle = {{2023 24th International Symposium on Quality Electronic Design (ISQED)}}, publisher = {{IEEE}}, title = {{{MAAS: Hiding Trojans in Approximate Circuits}}}, doi = {{10.1109/isqed57927.2023.10129286}}, year = {{2023}}, } @misc{54244, author = {{AlAidroos, Salem}}, publisher = {{Paderborn University}}, title = {{{Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform}}}, year = {{2023}}, } @misc{54243, author = {{Oviasogie, Marvin Osaretin}}, publisher = {{Paderborn University}}, title = {{{Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on Platform FPGAs}}}, year = {{2023}}, } @misc{54241, author = {{Reuter, Lucas David}}, publisher = {{Paderborn University}}, title = {{{Development of a Power Analysis Framework for Embedded FPGA Accelerators}}}, year = {{2023}}, } @inproceedings{29945, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco}}, booktitle = {{2022 59th ACM/IEEE Design Automation Conference (DAC)}}, location = {{San Francisco, USA}}, title = {{{Search Space Characterization for Approximate Logic Synthesis }}}, year = {{2022}}, } @inproceedings{29865, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, location = {{Online}}, title = {{{MUSCAT: MUS-based Circuit Approximation Technique}}}, year = {{2022}}, } @inproceedings{30971, author = {{Hansmeier, Tim and Platzner, Marco}}, booktitle = {{Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}}, isbn = {{9783031024610}}, issn = {{0302-9743}}, location = {{Madrid}}, pages = {{386--401}}, publisher = {{Springer International Publishing}}, title = {{{Integrating Safety Guarantees into the Learning Classifier System XCS}}}, doi = {{10.1007/978-3-031-02462-7_25}}, volume = {{13224}}, year = {{2022}}, } @inproceedings{32855, author = {{Clausing, Lennart and Platzner, Marco}}, booktitle = {{2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, location = {{ Lyon, France}}, pages = {{120--127}}, publisher = {{IEEE}}, title = {{{ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support}}}, doi = {{10.1109/ipdpsw55747.2022.00029}}, year = {{2022}}, } @inproceedings{33253, author = {{Hansmeier, Tim and Brede, Mathis and Platzner, Marco}}, booktitle = {{GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, location = {{Boston, MA, USA}}, pages = {{2071--2079}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}}}, doi = {{10.1145/3520304.3533977}}, year = {{2022}}, } @phdthesis{29769, abstract = {{Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.}}, author = {{Ahmed, Qazi Arbab}}, keywords = {{FPGA Security, Hardware Trojans, Bitstream-level Trojans, Bitstream Verification}}, publisher = {{ Paderborn University, Paderborn, Germany}}, title = {{{Hardware Trojans in Reconfigurable Computing}}}, doi = {{10.17619/UNIPB/1-1271}}, year = {{2022}}, } @unpublished{29541, author = {{Lienen, Christian and Platzner, Marco}}, title = {{{ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}}}, year = {{2022}}, } @inproceedings{34007, author = {{Lienen, Christian and Platzner, Marco}}, location = {{Neaples, Italy}}, title = {{{Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}}}, year = {{2022}}, } @inproceedings{34005, author = {{Lienen, Christian and Platzner, Marco}}, booktitle = {{2022 25th Euromicro Conference on Digital System Design (DSD)}}, location = {{Maspalomas, Gran Canaria, Spain}}, title = {{{Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}}}, doi = {{10.1109/DSD57027.2022.00088}}, year = {{2022}}, } @phdthesis{34041, author = {{Witschen, Linus Matthias}}, title = {{{Frameworks and Methodologies for Search-based Approximate Logic Synthesis}}}, doi = {{10.17619/UNIPB/1-1649}}, year = {{2022}}, } @inproceedings{32342, author = {{Ahmed, Qazi Arbab and Platzner, Marco}}, location = {{Pafos, Cyprus}}, publisher = {{IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}}, title = {{{On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}}}, year = {{2022}}, } @article{33990, abstract = {{Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.}}, author = {{Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}}, journal = {{IEEE Micro}}, number = {{6}}, pages = {{125--133}}, publisher = {{IEEE}}, title = {{{RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}}}, doi = {{10.1109/MM.2022.3202091}}, volume = {{42}}, year = {{2022}}, } @misc{45715, author = {{Tcheussi Ngayap, Vanessa Ingrid}}, title = {{{FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators}}}, year = {{2022}}, } @misc{45914, author = {{Manjunatha, Suraj}}, publisher = {{Paderborn University }}, title = {{{Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance}}}, year = {{2022}}, } @misc{45915, author = {{Kaur , Parvinder}}, title = {{{Analysis of Time-Series Classification in Conditional Monitoring Systems}}}, year = {{2022}}, }