@misc{10716, author = {{Mühlenbernd, Roland}}, publisher = {{Paderborn University}}, title = {{{FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}}}, year = {{2006}}, } @inproceedings{13624, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, booktitle = {{Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}}, publisher = {{IEEE}}, title = {{{Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}}}, year = {{2006}}, } @inproceedings{13625, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}}, title = {{{An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}}}, year = {{2006}}, } @inproceedings{13626, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}}, publisher = {{IEEE CS Press}}, title = {{{Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}}}, year = {{2006}}, } @inproceedings{2411, abstract = {{ This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, keywords = {{Zippy}}, pages = {{213--218}}, publisher = {{IEEE Computer Society}}, title = {{{Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}}}, doi = {{10.1109/ASAP.2005.69}}, year = {{2005}}, } @article{2412, abstract = {{ Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, keywords = {{FPGA, reconfigurable computing, co-simulation, Zippy}}, number = {{2-3}}, pages = {{63--73}}, publisher = {{Elsevier}}, title = {{{System-level performance evaluation of reconfigurable processors}}}, doi = {{10.1016/j.micpro.2004.06.004}}, volume = {{29}}, year = {{2005}}, } @inproceedings{13621, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}}, isbn = {{3902463031}}, title = {{{Periodic real-time scheduling for FPGA computers}}}, doi = {{10.1109/wises.2005.1438720}}, year = {{2005}}, } @inproceedings{13622, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}}, title = {{{Memory-demanding Periodic Real-time Applications on FPGA Computers}}}, year = {{2005}}, } @inproceedings{13623, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{0780393627}}, publisher = {{IEEE CS Press}}, title = {{{A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}}}, doi = {{10.1109/fpl.2005.1515787}}, year = {{2005}}, } @inproceedings{2415, abstract = {{In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{hardware virtualization}}, pages = {{63--69}}, publisher = {{CSREA Press}}, title = {{{Virtualization of Hardware – Introduction and Survey}}}, year = {{2004}}, } @article{10742, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco}}, journal = {{{IEEE} Transactions on Computers}}, number = {{11}}, pages = {{1393--1407}}, title = {{{Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}}}, doi = {{10.1109/tc.2004.99}}, volume = {{53}}, year = {{2004}}, } @inproceedings{13618, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9783540229896}}, issn = {{0302-9743}}, pages = {{831--835}}, publisher = {{Springer}}, title = {{{A Runtime Environment for Reconfigurable Hardware Operating Systems}}}, doi = {{10.1007/978-3-540-30117-2_84}}, year = {{2004}}, } @inproceedings{13619, author = {{Walder, Hebert and Nobs, Samuel and Platzner, Marco}}, booktitle = {{Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}}}, year = {{2004}}, } @inproceedings{13620, author = {{Dyer, Matthias and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{0769522300}}, publisher = {{IEEE CS Press}}, title = {{{Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}}}, doi = {{10.1109/fccm.2004.31}}, year = {{2004}}, } @inproceedings{2418, abstract = {{ This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{coprocessor, DIMM, memory bus, FPGA, high performance computing}}, pages = {{252--259}}, publisher = {{IEEE Computer Society}}, title = {{{TKDM – A Reconfigurable Co-processor in a PC's Memory Slot}}}, doi = {{10.1109/FPT.2003.1275755}}, year = {{2003}}, } @article{2419, abstract = {{Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.}}, author = {{Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}}, journal = {{Personal and Ubiquitous Computing}}, number = {{5}}, pages = {{299--308}}, publisher = {{Springer}}, title = {{{The Case for Reconfigurable Hardware in Wearable Computing}}}, doi = {{10.1007/s00779-003-0243-x}}, volume = {{7}}, year = {{2003}}, } @article{2420, abstract = {{ This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, issn = {{0920-8542}}, journal = {{Journal of Supercomputing}}, keywords = {{reconfigurable computing, instance-specific acceleration, minimum covering}}, number = {{2}}, pages = {{109--129}}, publisher = {{Kluwer Academic Publishers}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, doi = {{10.1023/a:1024443416592}}, volume = {{26}}, year = {{2003}}, } @inproceedings{2421, abstract = {{In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Zippy, multi-context, FPGA}}, pages = {{151--160}}, publisher = {{Springer}}, title = {{{Virtualizing Hardware with Multi-Context Reconfigurable Arrays}}}, doi = {{10.1007/b12007}}, volume = {{2778}}, year = {{2003}}, } @inproceedings{2422, abstract = {{Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-932415-05-X}}, keywords = {{Zippy, co-simulation}}, pages = {{174--180}}, publisher = {{CSREA Press}}, title = {{{Co-simulation of a Hybrid Multi-Context Architecture}}}, year = {{2003}}, } @inproceedings{13612, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings Design, Automation and Test in Europe Conference (DATE)}}, isbn = {{0769518702}}, pages = {{290--295}}, publisher = {{IEEE CS Press}}, title = {{{Online scheduling for block-partitioned reconfigurable devices}}}, doi = {{10.1109/date.2003.1253622}}, year = {{2003}}, }