@inproceedings{13613, author = {{Walder, Herbert and Steiger, Christoph and Platzner, Marco}}, booktitle = {{Proceedings International Parallel and Distributed Processing Symposium}}, isbn = {{0769519261}}, publisher = {{IEEE CS Press}}, title = {{{Fast online task placement on FPGAs: free space partitioning and 2D-hashing}}}, doi = {{10.1109/ipdps.2003.1213329}}, year = {{2003}}, } @inproceedings{13614, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, pages = {{284--287}}, publisher = {{CSREA Press}}, title = {{{Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}}}, year = {{2003}}, } @inproceedings{13615, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9783540408222}}, issn = {{0302-9743}}, pages = {{575--584}}, publisher = {{Springer}}, title = {{{Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}}}, doi = {{10.1007/978-3-540-45234-8_56}}, year = {{2003}}, } @inproceedings{13617, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}}, isbn = {{0769520448}}, pages = {{224--225}}, publisher = {{IEEE CS Press}}, title = {{{Online scheduling and placement of real-time tasks to partially reconfigurable devices}}}, doi = {{10.1109/real.2003.1253269}}, year = {{2003}}, } @inproceedings{2423, abstract = {{Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.}}, author = {{Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proc. Int. Symp. on Wearable Computers (ISWC)}}, isbn = {{0-7695-1816-8}}, keywords = {{wearable computing}}, pages = {{215--222}}, publisher = {{IEEE Computer Society}}, title = {{{Reconfigurable Hardware in Wearable Computing Nodes}}}, doi = {{10.1109/ISWC.2002.1167250}}, year = {{2002}}, } @inproceedings{2424, abstract = {{ Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. }}, author = {{Dyer, Matthias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{partial reconfiguration}}, pages = {{292--301}}, publisher = {{Springer}}, title = {{{Partially Reconfigurable Cores for Xilinx Virtex}}}, doi = {{10.1007/3-540-46117-5}}, volume = {{2438}}, year = {{2002}}, } @inproceedings{2425, abstract = {{ We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, pages = {{163--172}}, publisher = {{IEEE Computer Society}}, title = {{{Custom Computing Machines for the Set Covering Problem}}}, doi = {{10.1109/FPGA.2002.1106671}}, year = {{2002}}, } @article{10651, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{The Journal of Supercomputing}}, number = {{2}}, pages = {{145--159}}, publisher = {{Kluwer Academic Publishers}}, title = {{{A Framework for Run-time Reconfigurable Systems}}}, doi = {{10.1023/a:1013627403946}}, volume = {{21}}, year = {{2002}}, } @inproceedings{13611, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, pages = {{24--30}}, publisher = {{CSREA Press}}, title = {{{Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}}}, year = {{2002}}, } @inproceedings{2428, abstract = {{ In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{minimum covering, accelerator, funding-sundance}}, pages = {{85--91}}, publisher = {{CSREA Press}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, year = {{2001}}, } @inproceedings{2432, abstract = {{In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.}}, author = {{Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}}, booktitle = {{Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}}, keywords = {{benchmark}}, pages = {{135--146}}, title = {{{Reconfigurable Processors for Handhelds and Wearables: Application Analysis}}}, doi = {{10.1117/12.434376}}, volume = {{4525}}, year = {{2001}}, } @article{10713, author = {{Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}}, journal = {{{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}}, number = {{1}}, pages = {{205--210}}, title = {{{Object-oriented domain specific compilers for programming FPGAs}}}, doi = {{10.1109/92.920835}}, volume = {{9}}, year = {{2001}}, } @misc{13463, author = {{Enzler, Rolf and Platzner, Marco}}, publisher = {{TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}}, title = {{{Dynamically Reconfigurable Processors}}}, year = {{2001}}, } @article{6507, author = {{Platzner, Marco}}, issn = {{0018-9162}}, journal = {{Computer}}, number = {{4}}, pages = {{58--60}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Reconfigurable accelerators for combinatorial problems}}}, doi = {{10.1109/2.839322}}, volume = {{33}}, year = {{2000}}, } @article{10606, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{IEE Proceedings -- Computers & Digital Techniques}}, pages = {{159--165}}, publisher = {{IET}}, title = {{{Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}}}, doi = {{10.1049/ip-cdt:20000496}}, volume = {{147}}, year = {{2000}}, } @article{10725, author = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}}, journal = {{IEEE Intelligent Systems}}, number = {{2}}, pages = {{62--68}}, publisher = {{Institute of Electrical {\&} Electronics Engineers ({IEEE})}}, title = {{{Toward embedded qualitative simulation: a specialized computer architecture for QSim}}}, doi = {{10.1109/5254.850829}}, volume = {{15}}, year = {{2000}}, } @inproceedings{13609, author = {{Eisenring, Michael H. and Platzner, Marco}}, booktitle = {{Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)}}, pages = {{151--157}}, publisher = {{CSREA Press}}, title = {{{An Implementation Framework for Run-time Reconfigurable Systems}}}, year = {{2000}}, } @inproceedings{13610, author = {{Eisenring, Michael and Platzner, Marco}}, booktitle = {{Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)}}, pages = {{565--574}}, publisher = {{Springer}}, title = {{{Optimization of Run-time Reconfigurable Embedded Systems}}}, year = {{2000}}, } @inproceedings{13607, author = {{Mencer, Oskar and Platzner, Marco}}, booktitle = {{Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)}}, isbn = {{0769500013}}, publisher = {{IEEE CS Press}}, title = {{{Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment}}}, doi = {{10.1109/hicss.1999.772883}}, year = {{1999}}, } @inproceedings{13608, author = {{Eisenring, Michael and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)}}, isbn = {{9783540664574}}, issn = {{0302-9743}}, pages = {{205--214}}, publisher = {{Springer}}, title = {{{Communication Synthesis for Reconfigurable Embedded Systems}}}, doi = {{10.1007/978-3-540-48302-1_21}}, volume = {{1673}}, year = {{1999}}, }