@inproceedings{2432,
  abstract     = {{In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.}},
  author       = {{Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}},
  booktitle    = {{Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}},
  keywords     = {{benchmark}},
  pages        = {{135--146}},
  title        = {{{Reconfigurable Processors for Handhelds and Wearables: Application Analysis}}},
  doi          = {{10.1117/12.434376}},
  volume       = {{4525}},
  year         = {{2001}},
}

@article{10713,
  author       = {{Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}},
  journal      = {{{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}},
  number       = {{1}},
  pages        = {{205--210}},
  title        = {{{Object-oriented domain specific compilers for programming FPGAs}}},
  doi          = {{10.1109/92.920835}},
  volume       = {{9}},
  year         = {{2001}},
}

@misc{13463,
  author       = {{Enzler, Rolf and Platzner, Marco}},
  publisher    = {{TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}},
  title        = {{{Dynamically Reconfigurable Processors}}},
  year         = {{2001}},
}

@article{6507,
  author       = {{Platzner, Marco}},
  issn         = {{0018-9162}},
  journal      = {{Computer}},
  number       = {{4}},
  pages        = {{58--60}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Reconfigurable accelerators for combinatorial problems}}},
  doi          = {{10.1109/2.839322}},
  volume       = {{33}},
  year         = {{2000}},
}

@article{10606,
  author       = {{Eisenring, Michael and Platzner, Marco}},
  journal      = {{IEE Proceedings -- Computers & Digital Techniques}},
  pages        = {{159--165}},
  publisher    = {{IET}},
  title        = {{{Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}}},
  doi          = {{10.1049/ip-cdt:20000496}},
  volume       = {{147}},
  year         = {{2000}},
}

@article{10725,
  author       = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}},
  journal      = {{IEEE Intelligent Systems}},
  number       = {{2}},
  pages        = {{62--68}},
  publisher    = {{Institute of Electrical {\&} Electronics Engineers ({IEEE})}},
  title        = {{{Toward embedded qualitative simulation: a specialized computer architecture for QSim}}},
  doi          = {{10.1109/5254.850829}},
  volume       = {{15}},
  year         = {{2000}},
}

@inproceedings{13609,
  author       = {{Eisenring, Michael H. and Platzner, Marco}},
  booktitle    = {{Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)}},
  pages        = {{151--157}},
  publisher    = {{CSREA Press}},
  title        = {{{An Implementation Framework for Run-time Reconfigurable Systems}}},
  year         = {{2000}},
}

@inproceedings{13610,
  author       = {{Eisenring, Michael and Platzner, Marco}},
  booktitle    = {{Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)}},
  pages        = {{565--574}},
  publisher    = {{Springer}},
  title        = {{{Optimization of Run-time Reconfigurable Embedded Systems}}},
  year         = {{2000}},
}

@inproceedings{13607,
  author       = {{Mencer, Oskar and Platzner, Marco}},
  booktitle    = {{Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)}},
  isbn         = {{0769500013}},
  publisher    = {{IEEE CS Press}},
  title        = {{{Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment}}},
  doi          = {{10.1109/hicss.1999.772883}},
  year         = {{1999}},
}

@inproceedings{13608,
  author       = {{Eisenring, Michael and Platzner, Marco and Thiele, Lothar}},
  booktitle    = {{Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)}},
  isbn         = {{9783540664574}},
  issn         = {{0302-9743}},
  pages        = {{205--214}},
  publisher    = {{Springer}},
  title        = {{{Communication Synthesis for Reconfigurable Embedded Systems}}},
  doi          = {{10.1007/978-3-540-48302-1_21}},
  volume       = {{1673}},
  year         = {{1999}},
}

@article{10607,
  author       = {{Platzner, Marco}},
  journal      = {{e&i Elektrotechnik und Informationstechnik}},
  pages        = {{143--148}},
  publisher    = {{Springer}},
  title        = {{{Reconfigurable Computer Architectures}}},
  volume       = {{115}},
  year         = {{1998}},
}

@article{10608,
  author       = {{Platzner, Marco and Rinner, Bernhard}},
  journal      = {{International Journal of Computers & Their Applications}},
  pages        = {{106--116}},
  publisher    = {{ISCA}},
  title        = {{{Design and Implementation of a Parallel Constraint Satisfaction Algorithm}}},
  volume       = {{5}},
  year         = {{1998}},
}

@misc{13464,
  author       = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}},
  pages        = {{106--107}},
  publisher    = {{Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe's leading Universities}},
  title        = {{{A Distributed Computer Architecture for Fast Qualitative Simulation }}},
  year         = {{1998}},
}

@inproceedings{13606,
  author       = {{Platzner, Marco and De Micheli, Giovanni}},
  booktitle    = {{Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) }},
  isbn         = {{9783540649489}},
  issn         = {{0302-9743}},
  pages        = {{69--78}},
  publisher    = {{Springer }},
  title        = {{{Acceleration of satisfiability algorithms by reconfigurable hardware}}},
  doi          = {{10.1007/bfb0055234}},
  year         = {{1998}},
}

@article{10609,
  author       = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}},
  journal      = {{e & i Elektrotechnik und Informationstechnik}},
  pages        = {{13--18}},
  publisher    = {{Springer}},
  title        = {{{A Computer Architecture to Support Qualitative Simulation in Industrial Applications}}},
  volume       = {{114}},
  year         = {{1997}},
}

@article{10724,
  author       = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}},
  journal      = {{Simulation Practice and Theory}},
  number       = {{7-8}},
  pages        = {{623--638}},
  publisher    = {{Elsevier}},
  title        = {{{Parallel qualitative simulation}}},
  doi          = {{10.1016/s0928-4869(97)00008-6}},
  volume       = {{5}},
  year         = {{1997}},
}

@inproceedings{13603,
  author       = {{Platzner, Marco and Peters, Liliane}},
  booktitle    = {{Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing}},
  title        = {{{Fast Signature Segmentation on a Multi-DSP Architecture}}},
  volume       = {{3166}},
  year         = {{1997}},
}

@inproceedings{13604,
  author       = {{Röwekamp, Thomas and Platzner, Marco and Peters, Liliane }},
  booktitle    = {{Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT)}},
  pages        = {{829--833}},
  title        = {{{Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP}}},
  year         = {{1997}},
}

@inproceedings{13602,
  author       = {{Lind, Erich and Platzner, Marco and Rinner, Bernhard }},
  booktitle    = {{Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT)}},
  title        = {{{A Multi-DSP System with Dynamically Reconfigurable Processors}}},
  year         = {{1996}},
}

@article{10610,
  author       = {{Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}},
  journal      = {{J.UCS Journal of Universal Computer Science}},
  pages        = {{811--820}},
  publisher    = {{Springer}},
  title        = {{{Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation}}},
  volume       = {{12}},
  year         = {{1995}},
}