@inproceedings{3583, author = {{ Guetttatfi, Zakarya and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}}, title = {{{Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices}}}, year = {{2020}}, } @misc{21324, author = {{Chandrakar, Khushboo}}, title = {{{Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}}}, year = {{2020}}, } @misc{21432, abstract = {{Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular middleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation.}}, author = {{Henke, Luca-Sebastian}}, title = {{{Evaluation of a ReconOS-ROS Combination based on a Video Processing Application}}}, year = {{2020}}, } @inproceedings{21584, author = {{Gatica, Carlos Paiz and Platzner, Marco}}, booktitle = {{Machine Learning for Cyber Physical Systems (ML4CPS 2017)}}, isbn = {{9783662590836}}, issn = {{2522-8579}}, title = {{{Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures}}}, doi = {{10.1007/978-3-662-59084-3_9}}, year = {{2020}}, } @article{17358, abstract = {{Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, issn = {{1557-9999}}, journal = {{IEEE Transactions On Very Large Scale Integration Systems}}, keywords = {{Approximate circuit synthesis, approximate computing, error metrics, formal verification, proof-carrying hardware}}, number = {{9}}, pages = {{2084 -- 2088}}, publisher = {{IEEE}}, title = {{{Proof-carrying Approximate Circuits}}}, doi = {{10.1109/TVLSI.2020.3008061}}, volume = {{28}}, year = {{2020}}, } @article{17369, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, journal = {{International Journal of Hybrid intelligent Systems}}, publisher = {{IOS Press}}, title = {{{Evolution of Application-Specific Cache Mappings}}}, year = {{2020}}, } @unpublished{20748, abstract = {{On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Fifth Workshop on Approximate Computing (AxC 2020)}}, pages = {{2}}, title = {{{Search Space Characterization for AxC Synthesis}}}, year = {{2020}}, } @inproceedings{20750, author = {{Lienen, Christian and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)}}, title = {{{ReconROS: Flexible Hardware Acceleration for ROS2 Applications}}}, year = {{2020}}, } @misc{20820, author = {{Thiele, Simon}}, title = {{{Implementing Machine Learning Functions as PYNQ FPGA Overlays}}}, year = {{2020}}, } @misc{20821, author = {{Jaganath, Vivek}}, title = {{{Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}}}, year = {{2020}}, } @inproceedings{17063, author = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, isbn = {{978-1-4503-7127-8}}, location = {{Cancún, Mexico}}, pages = {{1756--1764}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{An Adaption Mechanism for the Error Threshold of XCSF}}}, doi = {{10.1145/3377929.3398106}}, year = {{2020}}, } @article{17092, abstract = {{Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.}}, author = {{Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}}, issn = {{1687-7195}}, journal = {{International Journal of Reconfigurable Computing}}, pages = {{1--19}}, title = {{{Dynamic Reliability Management for FPGA-Based Systems}}}, doi = {{10.1155/2020/2808710}}, year = {{2020}}, } @article{15836, author = {{Bellman, K. and Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C. and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}}, journal = {{ACM Transactions on Cyber-Physical Systems}}, pages = {{1--24}}, title = {{{Self-aware Cyber-Physical Systems}}}, volume = {{Accepted for Publication}}, year = {{2020}}, } @inproceedings{16213, abstract = {{Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. }}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020}}, location = {{Beijing, China}}, pages = {{421--426}}, publisher = {{ACM}}, title = {{{A Hybrid Synthesis Methodology for Approximate Circuits}}}, doi = {{10.1145/3386263.3406952}}, year = {{2020}}, } @inproceedings{16363, author = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, isbn = {{978-1-4503-7127-8}}, location = {{Cancún, Mexico}}, pages = {{125--126}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}}}, doi = {{10.1145/3377929.3389968}}, year = {{2020}}, } @inproceedings{20838, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, isbn = {{9781728174457}}, title = {{{MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}}}, doi = {{10.1109/ipdpsw50202.2020.00012}}, year = {{2020}}, } @inproceedings{35152, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, pages = {{6--16}}, title = {{{MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}}}, doi = {{10.1109/IPDPSW50202.2020.00012}}, year = {{2020}}, } @misc{21433, abstract = {{Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware. This thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable computing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.}}, author = {{Jentzsch, Felix P.}}, title = {{{Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}}}, year = {{2020}}, } @article{3585, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, issn = {{0026-2714}}, journal = {{Microelectronics Reliability}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{277--290}}, publisher = {{Elsevier}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, doi = {{10.1016/j.microrel.2019.04.003}}, volume = {{99}}, year = {{2019}}, } @unpublished{16853, abstract = {{State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Fourth Workshop on Approximate Computing (AxC 2019)}}, keywords = {{Approximate computing, parameter selection, search space exploration, verification, circuit synthesis}}, pages = {{2}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, year = {{2019}}, }