[{"author":[{"first_name":"Farjana","last_name":"Jalil","full_name":"Jalil, Farjana"},{"last_name":"Awais","full_name":"Awais, Muhammad","first_name":"Muhammad"},{"first_name":"Qazi Arbab","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed"},{"full_name":"Mohammadi, Hassan Ghasemzadeh","last_name":"Mohammadi","first_name":"Hassan Ghasemzadeh"},{"full_name":"Jungeblut, Thorsten","last_name":"Jungeblut","first_name":"Thorsten"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2026-02-11T10:18:50Z","publisher":"IEEE","date_updated":"2026-02-11T10:20:30Z","doi":"10.1109/dsn-w65791.2025.00048","title":"Deep&amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators","publication_status":"published","citation":{"ieee":"F. Jalil, M. Awais, Q. A. Ahmed, H. G. Mohammadi, T. Jungeblut, and M. Platzner, “Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators,” 2025, doi: <a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">10.1109/dsn-w65791.2025.00048</a>.","chicago":"Jalil, Farjana, Muhammad Awais, Qazi Arbab Ahmed, Hassan Ghasemzadeh Mohammadi, Thorsten Jungeblut, and Marco Platzner. “Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators.” In <i>2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">https://doi.org/10.1109/dsn-w65791.2025.00048</a>.","ama":"Jalil F, Awais M, Ahmed QA, Mohammadi HG, Jungeblut T, Platzner M. Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators. In: <i>2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">10.1109/dsn-w65791.2025.00048</a>","mla":"Jalil, Farjana, et al. “Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators.” <i>2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">10.1109/dsn-w65791.2025.00048</a>.","bibtex":"@inproceedings{Jalil_Awais_Ahmed_Mohammadi_Jungeblut_Platzner_2025, title={Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators}, DOI={<a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">10.1109/dsn-w65791.2025.00048</a>}, booktitle={2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Jalil, Farjana and Awais, Muhammad and Ahmed, Qazi Arbab and Mohammadi, Hassan Ghasemzadeh and Jungeblut, Thorsten and Platzner, Marco}, year={2025} }","short":"F. Jalil, M. Awais, Q.A. Ahmed, H.G. Mohammadi, T. Jungeblut, M. Platzner, in: 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2025.","apa":"Jalil, F., Awais, M., Ahmed, Q. A., Mohammadi, H. G., Jungeblut, T., &#38; Platzner, M. (2025). Deep&#38;amp;Wide: Achieving Area Efficiency in Scalable Approximate Accelerators. <i>2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. <a href=\"https://doi.org/10.1109/dsn-w65791.2025.00048\">https://doi.org/10.1109/dsn-w65791.2025.00048</a>"},"year":"2025","department":[{"_id":"78"}],"user_id":"64665","_id":"64112","publication":"2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","type":"conference","status":"public"},{"publication_status":"published","citation":{"mla":"Hadipour, Amir Hossein, et al. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>.","bibtex":"@inproceedings{Hadipour_Jafari_Awais_Platzner_2025, title={A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation}, DOI={<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>}, booktitle={2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}, publisher={IEEE}, author={Hadipour, Amir Hossein and Jafari, Atousa and Awais, Muhammad and Platzner, Marco}, year={2025} }","short":"A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.","apa":"Hadipour, A. H., Jafari, A., Awais, M., &#38; Platzner, M. (2025). A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">https://doi.org/10.1109/ddecs63720.2025.11006769</a>","ama":"Hadipour AH, Jafari A, Awais M, Platzner M. A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. In: <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>","ieee":"A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>.","chicago":"Hadipour, Amir Hossein, Atousa Jafari, Muhammad Awais, and Marco Platzner. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” In <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">https://doi.org/10.1109/ddecs63720.2025.11006769</a>."},"year":"2025","author":[{"last_name":"Hadipour","full_name":"Hadipour, Amir Hossein","first_name":"Amir Hossein"},{"first_name":"Atousa","full_name":"Jafari, Atousa","last_name":"Jafari"},{"full_name":"Awais, Muhammad","last_name":"Awais","first_name":"Muhammad"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2026-02-11T10:19:16Z","publisher":"IEEE","date_updated":"2026-02-11T10:20:31Z","doi":"10.1109/ddecs63720.2025.11006769","title":"A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation","publication":"2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"64665","_id":"64113"},{"type":"preprint","abstract":[{"text":"While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms.","lang":"eng"}],"status":"public","_id":"61152","department":[{"_id":"78"}],"user_id":"55631","language":[{"iso":"eng"}],"publication_status":"submitted","year":"2025","citation":{"short":"Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, (n.d.).","mla":"Umuroglu, Yaman, et al. <i>SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators</i>.","bibtex":"@article{Umuroglu_Berganski_Jentzsch_Danilowicz_Kryjak_Bezaitis_Sjalander_Colbert_Preusser_Petri-Koenig_et al., title={SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators}, author={Umuroglu, Yaman and Berganski, Christoph and Jentzsch, Felix and Danilowicz, Michal and Kryjak, Tomasz and Bezaitis, Charalampos and Sjalander, Magnus and Colbert, Ian and Preusser, Thomas and Petri-Koenig, Jakoba and et al.} }","apa":"Umuroglu, Y., Berganski, C., Jentzsch, F., Danilowicz, M., Kryjak, T., Bezaitis, C., Sjalander, M., Colbert, I., Preusser, T., Petri-Koenig, J., &#38; Blott, M. (n.d.). <i>SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators</i>.","ama":"Umuroglu Y, Berganski C, Jentzsch F, et al. SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.","ieee":"Y. Umuroglu <i>et al.</i>, “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.” .","chicago":"Umuroglu, Yaman, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Sjalander, et al. “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators,” n.d."},"date_updated":"2025-09-08T14:13:47Z","author":[{"full_name":"Umuroglu, Yaman","last_name":"Umuroglu","first_name":"Yaman"},{"last_name":"Berganski","full_name":"Berganski, Christoph","id":"98854","first_name":"Christoph"},{"id":"55631","full_name":"Jentzsch, Felix","last_name":"Jentzsch","orcid":"0000-0003-4987-5708","first_name":"Felix"},{"full_name":"Danilowicz, Michal","last_name":"Danilowicz","first_name":"Michal"},{"full_name":"Kryjak, Tomasz","last_name":"Kryjak","first_name":"Tomasz"},{"full_name":"Bezaitis, Charalampos","last_name":"Bezaitis","first_name":"Charalampos"},{"first_name":"Magnus","full_name":"Sjalander, Magnus","last_name":"Sjalander"},{"first_name":"Ian","last_name":"Colbert","full_name":"Colbert, Ian"},{"first_name":"Thomas","last_name":"Preusser","full_name":"Preusser, Thomas"},{"first_name":"Jakoba","last_name":"Petri-Koenig","full_name":"Petri-Koenig, Jakoba"},{"full_name":"Blott, Michaela","last_name":"Blott","first_name":"Michaela"}],"date_created":"2025-09-08T14:10:39Z","title":"SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators"},{"user_id":"64665","department":[{"_id":"78"}],"_id":"62020","status":"public","type":"journal_article","publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","doi":"10.1109/tvlsi.2025.3559377","title":"Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators","date_created":"2025-10-30T10:07:49Z","author":[{"full_name":"Awais, Muhammad","last_name":"Awais","first_name":"Muhammad"},{"full_name":"Mohammadi, Hassan Ghasemzadeh","last_name":"Mohammadi","first_name":"Hassan Ghasemzadeh"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"volume":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2025-10-30T10:08:55Z","citation":{"mla":"Awais, Muhammad, et al. “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, vol. 33, no. 9, Institute of Electrical and Electronics Engineers (IEEE), 2025, pp. 2395–405, doi:<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>.","short":"M. Awais, H.G. Mohammadi, M. Platzner, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33 (2025) 2395–2405.","bibtex":"@article{Awais_Mohammadi_Platzner_2025, title={Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators}, volume={33}, DOI={<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>}, number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Awais, Muhammad and Mohammadi, Hassan Ghasemzadeh and Platzner, Marco}, year={2025}, pages={2395–2405} }","apa":"Awais, M., Mohammadi, H. G., &#38; Platzner, M. (2025). Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, <i>33</i>(9), 2395–2405. <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">https://doi.org/10.1109/tvlsi.2025.3559377</a>","ama":"Awais M, Mohammadi HG, Platzner M. Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. 2025;33(9):2395-2405. doi:<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i> 33, no. 9 (2025): 2395–2405. <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">https://doi.org/10.1109/tvlsi.2025.3559377</a>.","ieee":"M. Awais, H. G. Mohammadi, and M. Platzner, “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, vol. 33, no. 9, pp. 2395–2405, 2025, doi: <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>."},"page":"2395-2405","intvolume":"        33","year":"2025","issue":"9","publication_status":"published","publication_identifier":{"issn":["1063-8210","1557-9999"]}},{"status":"public","type":"conference","publication":"2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","_id":"62019","user_id":"64665","department":[{"_id":"78"}],"year":"2025","citation":{"apa":"Hadipour, A. H., Jafari, A., Awais, M., &#38; Platzner, M. (2025). A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">https://doi.org/10.1109/ddecs63720.2025.11006769</a>","mla":"Hadipour, Amir Hossein, et al. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>.","bibtex":"@inproceedings{Hadipour_Jafari_Awais_Platzner_2025, title={A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation}, DOI={<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>}, booktitle={2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}, publisher={IEEE}, author={Hadipour, Amir Hossein and Jafari, Atousa and Awais, Muhammad and Platzner, Marco}, year={2025} }","short":"A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.","ieee":"A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>.","chicago":"Hadipour, Amir Hossein, Atousa Jafari, Muhammad Awais, and Marco Platzner. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” In <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">https://doi.org/10.1109/ddecs63720.2025.11006769</a>.","ama":"Hadipour AH, Jafari A, Awais M, Platzner M. A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. In: <i>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/ddecs63720.2025.11006769\">10.1109/ddecs63720.2025.11006769</a>"},"publication_status":"published","title":"A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation","doi":"10.1109/ddecs63720.2025.11006769","publisher":"IEEE","date_updated":"2025-10-30T10:08:50Z","date_created":"2025-10-30T10:07:11Z","author":[{"last_name":"Hadipour","full_name":"Hadipour, Amir Hossein","first_name":"Amir Hossein"},{"full_name":"Jafari, Atousa","last_name":"Jafari","first_name":"Atousa"},{"first_name":"Muhammad","full_name":"Awais, Muhammad","last_name":"Awais"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}]},{"year":"2025","citation":{"chicago":"Bengaluru Amarnath, Prajwal. <i>Design and Integration of Intra-Process Communication for ROS 2 into ReconROS</i>. Paderborn University, 2025.","ieee":"P. Bengaluru Amarnath, <i>Design and Integration of Intra-Process Communication for ROS 2 into ReconROS</i>. Paderborn University, 2025.","ama":"Bengaluru Amarnath P. <i>Design and Integration of Intra-Process Communication for ROS 2 into ReconROS</i>. Paderborn University; 2025.","apa":"Bengaluru Amarnath, P. (2025). <i>Design and Integration of Intra-Process Communication for ROS 2 into ReconROS</i>. Paderborn University.","short":"P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication for ROS 2 into ReconROS, Paderborn University, 2025.","bibtex":"@book{Bengaluru Amarnath_2025, title={Design and Integration of Intra-Process Communication for ROS 2 into ReconROS}, publisher={Paderborn University}, author={Bengaluru Amarnath, Prajwal}, year={2025} }","mla":"Bengaluru Amarnath, Prajwal. <i>Design and Integration of Intra-Process Communication for ROS 2 into ReconROS</i>. Paderborn University, 2025."},"title":"Design and Integration of Intra-Process Communication for ROS 2 into ReconROS","publisher":"Paderborn University","date_updated":"2025-11-20T10:17:09Z","date_created":"2025-11-20T10:15:20Z","supervisor":[{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"first_name":"Alexander Philipp","last_name":"Nowosad","orcid":"0009-0009-3783-3843","full_name":"Nowosad, Alexander Philipp","id":"68801"}],"author":[{"full_name":"Bengaluru Amarnath, Prajwal","last_name":"Bengaluru Amarnath","first_name":"Prajwal"}],"status":"public","type":"mastersthesis","language":[{"iso":"eng"}],"_id":"62268","user_id":"68801","department":[{"_id":"78"}]},{"status":"public","type":"journal_article","publication":"Journal of Hardware and Systems Security","language":[{"iso":"eng"}],"keyword":["General Engineering","Energy Engineering and Power Technology"],"user_id":"72764","department":[{"_id":"78"}],"_id":"52686","citation":{"chicago":"Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Post-Configuration Activation of Hardware Trojans in FPGAs.” <i>Journal of Hardware and Systems Security</i>, 2024. <a href=\"https://doi.org/10.1007/s41635-024-00147-5\">https://doi.org/10.1007/s41635-024-00147-5</a>.","ieee":"Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,” <i>Journal of Hardware and Systems Security</i>, 2024, doi: <a href=\"https://doi.org/10.1007/s41635-024-00147-5\">10.1007/s41635-024-00147-5</a>.","ama":"Ahmed QA, Wiersema T, Platzner M. Post-configuration Activation of Hardware Trojans in FPGAs. <i>Journal of Hardware and Systems Security</i>. Published online 2024. doi:<a href=\"https://doi.org/10.1007/s41635-024-00147-5\">10.1007/s41635-024-00147-5</a>","bibtex":"@article{Ahmed_Wiersema_Platzner_2024, title={Post-configuration Activation of Hardware Trojans in FPGAs}, DOI={<a href=\"https://doi.org/10.1007/s41635-024-00147-5\">10.1007/s41635-024-00147-5</a>}, journal={Journal of Hardware and Systems Security}, publisher={Springer Science and Business Media LLC}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2024} }","short":"Q.A. Ahmed, T. Wiersema, M. Platzner, Journal of Hardware and Systems Security (2024).","mla":"Ahmed, Qazi Arbab, et al. “Post-Configuration Activation of Hardware Trojans in FPGAs.” <i>Journal of Hardware and Systems Security</i>, Springer Science and Business Media LLC, 2024, doi:<a href=\"https://doi.org/10.1007/s41635-024-00147-5\">10.1007/s41635-024-00147-5</a>.","apa":"Ahmed, Q. A., Wiersema, T., &#38; Platzner, M. (2024). Post-configuration Activation of Hardware Trojans in FPGAs. <i>Journal of Hardware and Systems Security</i>. <a href=\"https://doi.org/10.1007/s41635-024-00147-5\">https://doi.org/10.1007/s41635-024-00147-5</a>"},"year":"2024","publication_status":"published","publication_identifier":{"issn":["2509-3428","2509-3436"]},"doi":"10.1007/s41635-024-00147-5","title":"Post-configuration Activation of Hardware Trojans in FPGAs","date_created":"2024-03-20T12:24:50Z","author":[{"first_name":"Qazi Arbab","orcid":"0000-0002-1837-2254","last_name":"Ahmed","full_name":"Ahmed, Qazi Arbab","id":"72764"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2024-03-20T12:31:36Z","publisher":"Springer Science and Business Media LLC"},{"user_id":"55631","department":[{"_id":"78"}],"_id":"54245","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","author":[{"first_name":"Luca-Sebastian","full_name":"Henke, Luca-Sebastian","last_name":"Henke"}],"date_created":"2024-05-13T14:00:01Z","supervisor":[{"last_name":"Jentzsch","orcid":"0000-0003-4987-5708","full_name":"Jentzsch, Felix","id":"55631","first_name":"Felix"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_updated":"2024-05-13T14:01:23Z","title":"Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting","citation":{"ieee":"L.-S. Henke, <i>Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting</i>. 2024.","chicago":"Henke, Luca-Sebastian. <i>Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting</i>, 2024.","ama":"Henke L-S. <i>Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting</i>.; 2024.","short":"L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting, 2024.","mla":"Henke, Luca-Sebastian. <i>Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting</i>. 2024.","bibtex":"@book{Henke_2024, title={Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting}, author={Henke, Luca-Sebastian}, year={2024} }","apa":"Henke, L.-S. (2024). <i>Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting</i>."},"year":"2024"},{"type":"conference","publication":"To apear in IEEE ISVLSI 2024","status":"public","_id":"54468","user_id":"64665","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"year":"2024","citation":{"ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing. In: <i>To Apear in IEEE ISVLSI 2024</i>. ; 2024.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing,” presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA, 2024.","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “DeepApprox: Rapid Deep Learning Based Design Space Exploration of Approximate Circuits via Check-Pointing.” In <i>To Apear in IEEE ISVLSI 2024</i>, 2024.","apa":"Awais, M., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2024). DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing. <i>To Apear in IEEE ISVLSI 2024</i>. IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: To Apear in IEEE ISVLSI 2024, 2024.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2024, title={DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing}, booktitle={To apear in IEEE ISVLSI 2024}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2024} }","mla":"Awais, Muhammad, et al. “DeepApprox: Rapid Deep Learning Based Design Space Exploration of Approximate Circuits via Check-Pointing.” <i>To Apear in IEEE ISVLSI 2024</i>, 2024."},"date_updated":"2024-05-29T08:26:29Z","date_created":"2024-05-28T08:14:43Z","author":[{"id":"64665","full_name":"Awais, Muhammad","last_name":"Awais","orcid":"https://orcid.org/0000-0003-4148-2969","first_name":"Muhammad"},{"first_name":"Hassan","id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing","conference":{"location":"Knoxville, Tennessee, USA","end_date":"2024-07-03","start_date":"2024-07-01","name":"IEEE Computer Society Annual Symposium on VLSI"}},{"type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"98854","_id":"56481","language":[{"iso":"eng"}],"citation":{"ama":"Berganski C, Jentzsch F, Platzner M, Kuhmichel M, Giefers H. FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers. In: ; 2024.","chicago":"Berganski, Christoph, Felix Jentzsch, Marco Platzner, Max Kuhmichel, and Heiner Giefers. “FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers,” 2024.","ieee":"C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, and H. Giefers, “FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers,” presented at the International Conference on Field Programmable Technology, Sydney, 2024.","bibtex":"@inproceedings{Berganski_Jentzsch_Platzner_Kuhmichel_Giefers_2024, title={FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers}, author={Berganski, Christoph and Jentzsch, Felix and Platzner, Marco and Kuhmichel, Max and Giefers, Heiner}, year={2024} }","short":"C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers, in: 2024.","mla":"Berganski, Christoph, et al. <i>FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers</i>. 2024.","apa":"Berganski, C., Jentzsch, F., Platzner, M., Kuhmichel, M., &#38; Giefers, H. (2024). <i>FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers</i>. International Conference on Field Programmable Technology, Sydney."},"year":"2024","date_created":"2024-10-10T07:49:13Z","author":[{"last_name":"Berganski","id":"98854","full_name":"Berganski, Christoph","first_name":"Christoph"},{"first_name":"Felix","id":"55631","full_name":"Jentzsch, Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Max","full_name":"Kuhmichel, Max","last_name":"Kuhmichel"},{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"}],"date_updated":"2024-10-10T07:52:06Z","conference":{"name":"International Conference on Field Programmable Technology","start_date":"2024-12-10","end_date":"2024-12-12","location":"Sydney"},"title":"FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers"},{"date_updated":"2025-01-09T15:32:54Z","publisher":"Paderborn University","date_created":"2025-01-09T15:29:16Z","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"orcid":"0009-0009-3783-3843","last_name":"Nowosad","full_name":"Nowosad, Alexander Philipp","id":"68801","first_name":"Alexander Philipp"}],"author":[{"first_name":"Maximilian","last_name":"Hartinger","full_name":"Hartinger, Maximilian"}],"title":"Controlling I/O Devices from Hardware-Mapped ReconROS Nodes","year":"2024","citation":{"ieee":"M. Hartinger, <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>. Paderborn University, 2024.","chicago":"Hartinger, Maximilian. <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>. Paderborn University, 2024.","ama":"Hartinger M. <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>. Paderborn University; 2024.","apa":"Hartinger, M. (2024). <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>. Paderborn University.","short":"M. Hartinger, Controlling I/O Devices from Hardware-Mapped ReconROS Nodes, Paderborn University, 2024.","bibtex":"@book{Hartinger_2024, title={Controlling I/O Devices from Hardware-Mapped ReconROS Nodes}, publisher={Paderborn University}, author={Hartinger, Maximilian}, year={2024} }","mla":"Hartinger, Maximilian. <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>. Paderborn University, 2024."},"_id":"58132","department":[{"_id":"78"}],"user_id":"68801","language":[{"iso":"eng"}],"type":"bachelorsthesis","status":"public"},{"status":"public","type":"dissertation","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"15504","_id":"47837","project":[{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)","_id":"14","grant_number":"160364472"}],"citation":{"chicago":"Hansmeier, Tim. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>, 2023.","ieee":"T. Hansmeier, <i>XCS for Self-awareness in Autonomous Computing Systems</i>. 2023.","ama":"Hansmeier T. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>.; 2023.","apa":"Hansmeier, T. (2023). <i>XCS for Self-awareness in Autonomous Computing Systems</i>.","short":"T. Hansmeier, XCS for Self-Awareness in Autonomous Computing Systems, 2023.","mla":"Hansmeier, Tim. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>. 2023.","bibtex":"@book{Hansmeier_2023, title={XCS for Self-awareness in Autonomous Computing Systems}, author={Hansmeier, Tim}, year={2023} }"},"year":"2023","title":"XCS for Self-awareness in Autonomous Computing Systems","supervisor":[{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"author":[{"first_name":"Tim","last_name":"Hansmeier","full_name":"Hansmeier, Tim"}],"date_created":"2023-10-06T12:45:58Z","date_updated":"2023-10-06T12:46:08Z"},{"user_id":"398","department":[{"_id":"78"}],"_id":"53794","language":[{"iso":"eng"}],"type":"conference","publication":"2023 Seventh IEEE International Conference on Robotic Computing (IRC)","status":"public","date_created":"2024-04-30T09:04:55Z","author":[{"first_name":"Christian","full_name":"Lienen, Christian","id":"60323","last_name":"Lienen"},{"last_name":"Brede","full_name":"Brede, Mathis","first_name":"Mathis"},{"first_name":"Daniel","full_name":"Karger, Daniel","last_name":"Karger"},{"last_name":"Koch","full_name":"Koch, Kevin","first_name":"Kevin"},{"first_name":"Dalisha","full_name":"Logan, Dalisha","last_name":"Logan"},{"first_name":"Janet","last_name":"Mazur","full_name":"Mazur, Janet"},{"first_name":"Alexander Philipp","last_name":"Nowosad","full_name":"Nowosad, Alexander Philipp"},{"full_name":"Schnelle, Alexander","last_name":"Schnelle","first_name":"Alexander"},{"last_name":"Waizy","full_name":"Waizy, Mohness","first_name":"Mohness"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_updated":"2024-04-30T09:16:01Z","publisher":"IEEE","doi":"10.1109/irc59093.2023.00056","title":"AutonomROS: A ReconROS-based Autonomous Driving Unit","publication_status":"published","citation":{"mla":"Lienen, Christian, et al. “AutonomROS: A ReconROS-Based Autonomous Driving Unit.” <i>2023 Seventh IEEE International Conference on Robotic Computing (IRC)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/irc59093.2023.00056\">10.1109/irc59093.2023.00056</a>.","short":"C. Lienen, M. Brede, D. Karger, K. Koch, D. Logan, J. Mazur, A.P. Nowosad, A. Schnelle, M. Waizy, M. Platzner, in: 2023 Seventh IEEE International Conference on Robotic Computing (IRC), IEEE, 2023.","bibtex":"@inproceedings{Lienen_Brede_Karger_Koch_Logan_Mazur_Nowosad_Schnelle_Waizy_Platzner_2023, title={AutonomROS: A ReconROS-based Autonomous Driving Unit}, DOI={<a href=\"https://doi.org/10.1109/irc59093.2023.00056\">10.1109/irc59093.2023.00056</a>}, booktitle={2023 Seventh IEEE International Conference on Robotic Computing (IRC)}, publisher={IEEE}, author={Lienen, Christian and Brede, Mathis and Karger, Daniel and Koch, Kevin and Logan, Dalisha and Mazur, Janet and Nowosad, Alexander Philipp and Schnelle, Alexander and Waizy, Mohness and Platzner, Marco}, year={2023} }","apa":"Lienen, C., Brede, M., Karger, D., Koch, K., Logan, D., Mazur, J., Nowosad, A. P., Schnelle, A., Waizy, M., &#38; Platzner, M. (2023). AutonomROS: A ReconROS-based Autonomous Driving Unit. <i>2023 Seventh IEEE International Conference on Robotic Computing (IRC)</i>. <a href=\"https://doi.org/10.1109/irc59093.2023.00056\">https://doi.org/10.1109/irc59093.2023.00056</a>","ama":"Lienen C, Brede M, Karger D, et al. AutonomROS: A ReconROS-based Autonomous Driving Unit. In: <i>2023 Seventh IEEE International Conference on Robotic Computing (IRC)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/irc59093.2023.00056\">10.1109/irc59093.2023.00056</a>","ieee":"C. Lienen <i>et al.</i>, “AutonomROS: A ReconROS-based Autonomous Driving Unit,” 2023, doi: <a href=\"https://doi.org/10.1109/irc59093.2023.00056\">10.1109/irc59093.2023.00056</a>.","chicago":"Lienen, Christian, Mathis Brede, Daniel Karger, Kevin Koch, Dalisha Logan, Janet Mazur, Alexander Philipp Nowosad, Alexander Schnelle, Mohness Waizy, and Marco Platzner. “AutonomROS: A ReconROS-Based Autonomous Driving Unit.” In <i>2023 Seventh IEEE International Conference on Robotic Computing (IRC)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/irc59093.2023.00056\">https://doi.org/10.1109/irc59093.2023.00056</a>."},"year":"2023"},{"citation":{"ama":"Clausing L, Guetattfi Z, Kaufmann P, Lienen C, Platzner M. On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. In: <i>Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)</i>. ; 2023. doi:<a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>","ieee":"L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64,” 2023, doi: <a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>.","chicago":"Clausing, Lennart, Zakarya Guetattfi, Paul Kaufmann, Christian Lienen, and Marco Platzner. “On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks under ReconOS64.” In <i>Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)</i>, 2023. <a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>.","apa":"Clausing, L., Guetattfi, Z., Kaufmann, P., Lienen, C., &#38; Platzner, M. (2023). On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. <i>Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)</i>. <a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>","short":"L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, M. Platzner, in: Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023.","bibtex":"@inproceedings{Clausing_Guetattfi_Kaufmann_Lienen_Platzner_2023, title={On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64}, DOI={<a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>}, booktitle={Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)}, author={Clausing, Lennart and Guetattfi, Zakarya and Kaufmann, Paul and Lienen, Christian and Platzner, Marco}, year={2023} }","mla":"Clausing, Lennart, et al. “On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks under ReconOS64.” <i>Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)</i>, 2023, doi:<a href=\"https://doi.org/10.1007/978-3-031-42921-7_17\">https://doi.org/10.1007/978-3-031-42921-7_17</a>."},"year":"2023","doi":"https://doi.org/10.1007/978-3-031-42921-7_17","title":"On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64","author":[{"first_name":"Lennart","id":"74287","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing"},{"full_name":"Guetattfi, Zakarya","last_name":"Guetattfi","first_name":"Zakarya"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"id":"60323","full_name":"Lienen, Christian","last_name":"Lienen","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2023-07-09T12:50:32Z","date_updated":"2024-04-30T09:11:26Z","status":"public","publication":"Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"398","_id":"45913","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"}]},{"_id":"46229","department":[{"_id":"78"}],"user_id":"398","language":[{"iso":"eng"}],"publication":"Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)","type":"conference","status":"public","date_updated":"2024-04-30T09:13:08Z","author":[{"first_name":"Christian","full_name":"Lienen, Christian","id":"60323","last_name":"Lienen"},{"first_name":"Alexander Philipp","last_name":"Nowosad","full_name":"Nowosad, Alexander Philipp"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2023-07-31T11:56:47Z","title":"Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms","doi":"https://doi.org/10.1145/3637843.3637846","main_file_link":[{"url":"https://arxiv.org/pdf/2306.12761.pdf"}],"publication_status":"accepted","year":"2023","citation":{"mla":"Lienen, Christian, et al. “Mapping and Optimizing Communication in ROS 2-Based Applications on Configurable System-on-Chip Platforms.” <i>Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)</i>, doi:<a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>.","short":"C. Lienen, A.P. Nowosad, M. Platzner, in: Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI), n.d.","bibtex":"@inproceedings{Lienen_Nowosad_Platzner, title={Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms}, DOI={<a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>}, booktitle={Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)}, author={Lienen, Christian and Nowosad, Alexander Philipp and Platzner, Marco} }","apa":"Lienen, C., Nowosad, A. P., &#38; Platzner, M. (n.d.). Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms. <i>Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)</i>. <a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>","ama":"Lienen C, Nowosad AP, Platzner M. Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms. In: <i>Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)</i>. doi:<a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>","chicago":"Lienen, Christian, Alexander Philipp Nowosad, and Marco Platzner. “Mapping and Optimizing Communication in ROS 2-Based Applications on Configurable System-on-Chip Platforms.” In <i>Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)</i>, n.d. <a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>.","ieee":"C. Lienen, A. P. Nowosad, and M. Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms,” doi: <a href=\"https://doi.org/10.1145/3637843.3637846\">https://doi.org/10.1145/3637843.3637846</a>."}},{"year":"2023","citation":{"apa":"Lienen, C., Middeke, S. H., &#38; Platzner, M. (2023). fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications. <i> Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)</i>. <a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">https://doi.org/10.1109/IROS55552.2023.10341921</a>","bibtex":"@inproceedings{Lienen_Middeke_Platzner_2023, title={fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications}, DOI={<a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">10.1109/IROS55552.2023.10341921</a>}, booktitle={ Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)}, author={Lienen, Christian and Middeke, Sorel Horst and Platzner, Marco}, year={2023} }","short":"C. Lienen, S.H. Middeke, M. Platzner, in:  Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2023.","mla":"Lienen, Christian, et al. “FpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications.” <i> Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)</i>, 2023, doi:<a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">10.1109/IROS55552.2023.10341921</a>.","ieee":"C. Lienen, S. H. Middeke, and M. Platzner, “fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications,” 2023, doi: <a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">10.1109/IROS55552.2023.10341921</a>.","chicago":"Lienen, Christian, Sorel Horst Middeke, and Marco Platzner. “FpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications.” In <i> Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)</i>, 2023. <a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">https://doi.org/10.1109/IROS55552.2023.10341921</a>.","ama":"Lienen C, Middeke SH, Platzner M. fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications. In: <i> Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)</i>. ; 2023. doi:<a href=\"https://doi.org/10.1109/IROS55552.2023.10341921\">10.1109/IROS55552.2023.10341921</a>"},"title":"fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications","main_file_link":[{"url":"https://arxiv.org/pdf/2303.00532.pdf"}],"doi":"10.1109/IROS55552.2023.10341921","date_updated":"2024-04-30T09:13:03Z","author":[{"first_name":"Christian","last_name":"Lienen","id":"60323","full_name":"Lienen, Christian"},{"first_name":"Sorel Horst","full_name":"Middeke, Sorel Horst","last_name":"Middeke"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2023-03-20T07:41:47Z","status":"public","type":"conference","publication":" Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)","language":[{"iso":"eng"}],"_id":"43048","user_id":"398","department":[{"_id":"78"}]},{"file":[{"access_level":"open_access","file_name":"B4-Chapter-SFB-Buch-Final.pdf","file_id":"45889","file_size":840964,"creator":"florida","date_created":"2023-07-07T08:01:12Z","date_updated":"2023-07-07T11:18:59Z","relation":"main_file","content_type":"application/pdf"}],"publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","ddc":["004"],"language":[{"iso":"eng"}],"year":"2023","title":"Verifying Software and Reconfigurable Hardware Services","publisher":"Heinz Nixdorf Institut, Universität Paderborn","date_created":"2023-07-07T08:01:23Z","editor":[{"full_name":"Haake, Claus-Jochen","last_name":"Haake","first_name":"Claus-Jochen"},{"first_name":"Friedhelm","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm"},{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Henning","full_name":"Wachsmuth, Henning","last_name":"Wachsmuth"},{"first_name":"Heike","last_name":"Wehrheim","full_name":"Wehrheim, Heike"}],"status":"public","type":"book_chapter","file_date_updated":"2023-07-07T11:18:59Z","_id":"45888","project":[{"_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","grant_number":"160364472"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"}],"department":[{"_id":"7"},{"_id":"78"}],"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","user_id":"398","place":"Paderborn","page":"125-144","intvolume":"       412","citation":{"mla":"Wehrheim, Heike, et al. “Verifying Software and Reconfigurable Hardware Services.” <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 125–44, doi:<a href=\"https://doi.org/10.5281/zenodo.8068583\">10.5281/zenodo.8068583</a>.","short":"H. Wehrheim, M. Platzner, E. Bodden, P. Schubert, F. Pauck, M.-C. Jakobs, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 125–144.","bibtex":"@inbook{Wehrheim_Platzner_Bodden_Schubert_Pauck_Jakobs_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Verifying Software and Reconfigurable Hardware Services}, volume={412}, DOI={<a href=\"https://doi.org/10.5281/zenodo.8068583\">10.5281/zenodo.8068583</a>}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Wehrheim, Heike and Platzner, Marco and Bodden, Eric and Schubert, Philipp  and Pauck, Felix and Jakobs, Marie-Christine}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={125–144}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","apa":"Wehrheim, H., Platzner, M., Bodden, E., Schubert, P., Pauck, F., &#38; Jakobs, M.-C. (2023). Verifying Software and Reconfigurable Hardware Services. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, &#38; H. Wehrheim (Eds.), <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i> (Vol. 412, pp. 125–144). Heinz Nixdorf Institut, Universität Paderborn. <a href=\"https://doi.org/10.5281/zenodo.8068583\">https://doi.org/10.5281/zenodo.8068583</a>","chicago":"Wehrheim, Heike, Marco Platzner, Eric Bodden, Philipp  Schubert, Felix Pauck, and Marie-Christine Jakobs. “Verifying Software and Reconfigurable Hardware Services.” In <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:125–44. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. <a href=\"https://doi.org/10.5281/zenodo.8068583\">https://doi.org/10.5281/zenodo.8068583</a>.","ieee":"H. Wehrheim, M. Platzner, E. Bodden, P. Schubert, F. Pauck, and M.-C. Jakobs, “Verifying Software and Reconfigurable Hardware Services,” in <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i>, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 125–144.","ama":"Wehrheim H, Platzner M, Bodden E, Schubert P, Pauck F, Jakobs M-C. Verifying Software and Reconfigurable Hardware Services. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:125-144. doi:<a href=\"https://doi.org/10.5281/zenodo.8068583\">10.5281/zenodo.8068583</a>"},"has_accepted_license":"1","doi":"10.5281/zenodo.8068583","oa":"1","date_updated":"2024-05-02T10:29:31Z","volume":412,"author":[{"first_name":"Heike","full_name":"Wehrheim, Heike","id":"573","last_name":"Wehrheim"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"},{"full_name":"Bodden, Eric","id":"59256","orcid":"0000-0003-3470-3647","last_name":"Bodden","first_name":"Eric"},{"last_name":"Schubert","full_name":"Schubert, Philipp ","first_name":"Philipp "},{"id":"22398","full_name":"Pauck, Felix","last_name":"Pauck","first_name":"Felix"},{"first_name":"Marie-Christine","full_name":"Jakobs, Marie-Christine","last_name":"Jakobs"}]},{"language":[{"iso":"eng"}],"ddc":["004"],"publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","file":[{"date_updated":"2023-07-07T11:17:33Z","date_created":"2023-07-07T08:15:35Z","creator":"florida","file_size":2288788,"file_name":"C2-Chapter-SFB-Buch-Final.pdf","access_level":"open_access","file_id":"45894","content_type":"application/pdf","relation":"main_file"}],"date_created":"2023-07-07T08:15:45Z","publisher":"Heinz Nixdorf Institut, Universität Paderborn","title":"Compute Centers I: Heterogeneous Execution Environments","year":"2023","user_id":"398","series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","department":[{"_id":"7"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)","_id":"14","grant_number":"160364472"}],"_id":"45893","file_date_updated":"2023-07-07T11:17:33Z","type":"book_chapter","status":"public","editor":[{"first_name":"Claus-Jochen","last_name":"Haake","full_name":"Haake, Claus-Jochen"},{"full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","first_name":"Friedhelm"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"},{"full_name":"Wachsmuth, Henning","last_name":"Wachsmuth","first_name":"Henning"},{"last_name":"Wehrheim","full_name":"Wehrheim, Heike","first_name":"Heike"}],"author":[{"first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","id":"49992"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"id":"40778","full_name":"Meyer, Marius","last_name":"Meyer","first_name":"Marius"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"volume":412,"oa":"1","date_updated":"2024-05-02T10:33:00Z","doi":"10.5281/zenodo.8068642","has_accepted_license":"1","citation":{"ama":"Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:<a href=\"https://doi.org/10.5281/zenodo.8068642\">10.5281/zenodo.8068642</a>","ieee":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl, “Compute Centers I: Heterogeneous Execution Environments,” in <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i>, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.","chicago":"Hansmeier, Tim, Tobias Kenter, Marius Meyer, Heinrich Riebler, Marco Platzner, and Christian Plessl. “Compute Centers I: Heterogeneous Execution Environments.” In <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:165–82. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. <a href=\"https://doi.org/10.5281/zenodo.8068642\">https://doi.org/10.5281/zenodo.8068642</a>.","apa":"Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., &#38; Plessl, C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, &#38; H. Wehrheim (Eds.), <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i> (Vol. 412, pp. 165–182). Heinz Nixdorf Institut, Universität Paderborn. <a href=\"https://doi.org/10.5281/zenodo.8068642\">https://doi.org/10.5281/zenodo.8068642</a>","short":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.","bibtex":"@inbook{Hansmeier_Kenter_Meyer_Riebler_Platzner_Plessl_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Compute Centers I: Heterogeneous Execution Environments}, volume={412}, DOI={<a href=\"https://doi.org/10.5281/zenodo.8068642\">10.5281/zenodo.8068642</a>}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={165–182}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","mla":"Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.” <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–82, doi:<a href=\"https://doi.org/10.5281/zenodo.8068642\">10.5281/zenodo.8068642</a>."},"page":"165-182","intvolume":"       412","place":"Paderborn"},{"department":[{"_id":"7"},{"_id":"78"}],"user_id":"398","series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","_id":"45899","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"}],"file_date_updated":"2023-07-07T11:14:23Z","type":"book_chapter","status":"public","editor":[{"first_name":"Claus-Jochen","full_name":"Haake, Claus-Jochen","last_name":"Haake"},{"first_name":"Friedhelm","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"first_name":"Henning","full_name":"Wachsmuth, Henning","last_name":"Wachsmuth"},{"first_name":"Heike","full_name":"Wehrheim, Heike","last_name":"Wehrheim"}],"volume":412,"author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287"},{"orcid":"0000-0003-4987-5708","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631","first_name":"Felix"},{"full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2024-05-02T10:33:26Z","oa":"1","doi":"10.5281/zenodo.8068713","has_accepted_license":"1","page":"225-236","intvolume":"       412","citation":{"ama":"Boschmann A, Clausing L, Jentzsch F, Ghasemzadeh Mohammadi H, Platzner M. Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:225-236. doi:<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>","chicago":"Boschmann, Alexander, Lennart Clausing, Felix Jentzsch, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.” In <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:225–36. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. <a href=\"https://doi.org/10.5281/zenodo.8068713\">https://doi.org/10.5281/zenodo.8068713</a>.","ieee":"A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, and M. Platzner, “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip,” in <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i>, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 225–236.","apa":"Boschmann, A., Clausing, L., Jentzsch, F., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2023). Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, &#38; H. Wehrheim (Eds.), <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i> (Vol. 412, pp. 225–236). Heinz Nixdorf Institut, Universität Paderborn. <a href=\"https://doi.org/10.5281/zenodo.8068713\">https://doi.org/10.5281/zenodo.8068713</a>","mla":"Boschmann, Alexander, et al. “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.” <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 225–36, doi:<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>.","bibtex":"@inbook{Boschmann_Clausing_Jentzsch_Ghasemzadeh Mohammadi_Platzner_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}, volume={412}, DOI={<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Boschmann, Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={225–236}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","short":"A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, M. Platzner, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 225–236."},"place":"Paderborn","language":[{"iso":"eng"}],"ddc":["004"],"publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","file":[{"relation":"main_file","content_type":"application/pdf","file_name":"T1-Chapter-SFB-Buch-Final.pdf","access_level":"open_access","file_id":"45900","file_size":468973,"creator":"florida","date_created":"2023-07-07T08:36:40Z","date_updated":"2023-07-07T11:14:23Z"}],"date_created":"2023-07-07T08:36:58Z","publisher":"Heinz Nixdorf Institut, Universität Paderborn","title":"Flexible Industrial Analytics on Reconfigurable Systems-On-Chip","year":"2023"},{"publisher":"Paderborn University","date_updated":"2024-05-08T15:51:52Z","supervisor":[{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christoph","last_name":"Berganski","full_name":"Berganski, Christoph","id":"98854"},{"first_name":"Andre","full_name":"Diekwisch, Andre","id":"9451","last_name":"Diekwisch"}],"author":[{"first_name":"Deepak Bhardwaj","last_name":"Anantha Rao","full_name":"Anantha Rao, Deepak Bhardwaj"}],"date_created":"2024-05-08T15:40:17Z","title":"Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller","year":"2023","citation":{"chicago":"Anantha Rao, Deepak Bhardwaj. <i>Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University, 2023.","ieee":"D. B. Anantha Rao, <i>Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University, 2023.","ama":"Anantha Rao DB. <i>Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University; 2023.","apa":"Anantha Rao, D. B. (2023). <i>Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University.","short":"D.B. Anantha Rao, Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller, Paderborn University, 2023.","mla":"Anantha Rao, Deepak Bhardwaj. <i>Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University, 2023.","bibtex":"@book{Anantha Rao_2023, title={Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller}, publisher={Paderborn University}, author={Anantha Rao, Deepak Bhardwaj}, year={2023} }"},"_id":"54127","department":[{"_id":"78"}],"user_id":"98854","extern":"1","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"}]