[{"_id":"168","citation":{"mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917."},"type":"conference","year":"2016","page":"912-917","abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf","file_id":"1541","creator":"florida","file_size":261356,"access_level":"closed","file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z"}],"author":[{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1","publisher":"EDA Consortium / IEEE","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2018-03-21T12:41:55Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}]},{"date_updated":"2022-01-06T06:57:30Z","doi":"10.1007/978-3-319-16214-0_32","series_title":"LNCS","language":[{"iso":"eng"}],"title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"_id":"269","page":"365--372","year":"2015","type":"conference","citation":{"short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","apa":"Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32","ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32","chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32.","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.","bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }"},"abstract":[{"text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.","lang":"eng"}],"user_id":"477","ddc":["040"],"file":[{"access_level":"closed","date_created":"2018-03-21T09:32:42Z","file_name":"269-paper_53.pdf","date_updated":"2018-03-21T09:32:42Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":344309,"creator":"florida","file_id":"1477"}],"publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","file_date_updated":"2018-03-21T09:32:42Z","author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Wu","full_name":"Wu, Sen","first_name":"Sen"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2017-10-17T12:41:44Z","status":"public","has_accepted_license":"1"},{"status":"public","date_created":"2018-06-26T14:06:07Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"author":[{"full_name":"Knorr, Christoph","first_name":"Christoph","last_name":"Knorr"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","user_id":"477","type":"bachelorsthesis","citation":{"short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","ieee":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","apa":"Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn.","ama":"Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.","chicago":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","mla":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015."},"year":"2015","supervisor":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"ger"}],"_id":"3364","date_updated":"2022-01-06T06:59:13Z"},{"issue":"7","intvolume":" 48","_id":"1772","year":"2015","type":"journal_article","citation":{"apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015."},"page":"18-20","user_id":"16153","ddc":["000"],"has_accepted_license":"1","status":"public","date_created":"2018-03-23T14:06:12Z","volume":48,"file":[{"file_size":5605009,"creator":"ups","file_id":"5313","content_type":"application/pdf","date_updated":"2018-11-02T15:47:45Z","success":1,"relation":"main_file","file_name":"07163237.pdf","date_created":"2018-11-02T15:47:45Z","access_level":"closed"}],"publisher":"IEEE Computer Society","author":[{"first_name":"Jim","full_name":"Torresen, Jim","last_name":"Torresen"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Yao","first_name":"Xin","full_name":"Yao, Xin"}],"file_date_updated":"2018-11-02T15:47:45Z","publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"date_updated":"2022-01-06T06:50:47Z","_id":"10615","year":"2015","citation":{"ieee":"A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015.","short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }","mla":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","apa":"Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University.","ama":"Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.","chicago":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015."},"type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"title":"Self-Optimizing Organic Cache","user_id":"3118","publisher":"Paderborn University","author":[{"first_name":"Abdullah Fathi","full_name":"Ahmed, Abdullah Fathi","last_name":"Ahmed"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:25:13Z"},{"abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"place":"Berlin","user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"}],"date_created":"2019-07-10T09:36:58Z","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004"}],"status":"public","publication_identifier":{"isbn":["978-3-8325-4155-2"]},"_id":"10624","date_updated":"2022-01-06T06:50:48Z","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"page":"183","citation":{"mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015."},"type":"dissertation","year":"2015"},{"_id":"10668","date_updated":"2022-01-06T06:50:49Z","supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2015","citation":{"bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","mla":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","chicago":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","ama":"Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.","apa":"Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University.","ieee":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015."},"user_id":"3118","title":"Evolution of Heat Flow Prediction Models for FPGA Devices","department":[{"_id":"78"}],"author":[{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:15:13Z","status":"public"},{"_id":"10671","date_updated":"2022-01-06T06:50:49Z","supervisor":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"}],"language":[{"iso":"eng"}],"year":"2015","citation":{"mla":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }","chicago":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","ama":"Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.","apa":"Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University.","ieee":"C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015."},"type":"mastersthesis","user_id":"3118","title":"Computer Vision basierte Klassifikation von HD EMG Signalen","publisher":"Paderborn University","author":[{"full_name":"Haupt, Christian","first_name":"Christian","last_name":"Haupt"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:17:57Z"},{"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","department":[{"_id":"78"}],"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Ahmed, Abdullah Fathi","first_name":"Abdullah Fathi","last_name":"Ahmed"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:18:00Z","project":[{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"status":"public","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","user_id":"3118","page":"1-7","year":"2015","type":"conference","citation":{"short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }"},"language":[{"iso":"eng"}],"_id":"10673","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/AHS.2015.7231178"},{"user_id":"3118","title":"Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing","date_created":"2019-07-10T11:30:00Z","status":"public","department":[{"_id":"78"}],"publication":"Genetic and Evolutionary Computation (GECCO)","publisher":"ACM","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10693","page":"409-416","citation":{"ieee":"P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416.","short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.","mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.","bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.","apa":"Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM.","chicago":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic and Evolutionary Computation (GECCO), 409–16. ACM, 2015."},"year":"2015","type":"conference"}]