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Journal of Electronics 100 (2012) 1646–1651."},"page":"1646-1651","user_id":"24135","title":"Parallel algorithm for computation of second-order sequential best rotations","author":[{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"},{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"}],"publisher":"Taylor & Francis","department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Journal of Electronics","status":"public","date_created":"2018-04-03T09:05:36Z","volume":100},{"issue":"6","intvolume":" 7","_id":"2174","date_updated":"2022-01-06T06:55:12Z","page":"1312-1328","type":"journal_article","citation":{"chicago":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.","apa":"Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328.","ama":"Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.","mla":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.","bibtex":"@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }","short":"S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328.","ieee":"S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012."},"year":"2012","title":"Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer","user_id":"24135","volume":7,"date_created":"2018-04-03T09:08:00Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Journal of Computers","author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"last_name":"Benkrid","first_name":"Khaled","full_name":"Benkrid, Khaled"}],"publisher":"Academy Publishers"},{"abstract":[{"lang":"eng","text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety."},{"lang":"ger","text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit."}],"user_id":"477","ddc":["040"],"file":[{"file_name":"586-Drzevitzky-PhD_01.pdf","date_created":"2018-03-15T08:38:19Z","access_level":"closed","creator":"florida","file_id":"1261","file_size":1438436,"relation":"main_file","success":1,"date_updated":"2018-03-15T08:38:19Z","content_type":"application/pdf"}],"author":[{"first_name":"Stephanie","full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky"}],"publisher":"Universität Paderborn","file_date_updated":"2018-03-15T08:38:19Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:46Z","_id":"586","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423"}],"supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"citation":{"ieee":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012.","mla":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","chicago":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","apa":"Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn.","ama":"Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012."},"year":"2012","type":"dissertation","page":"114","title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","department":[{"_id":"78"}],"project":[{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"}],"publication_status":"published","date_updated":"2022-01-06T07:02:44Z","oa":"1","language":[{"iso":"eng"}]},{"ddc":["040"],"title":"Programming models for reconfigurable heterogeneous multi-cores","user_id":"398","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"}],"publisher":"Awareness Magazine","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-15T08:37:02Z","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T08:37:02Z","file_id":"1260","creator":"florida","file_size":353057,"access_level":"closed","date_created":"2018-03-15T08:37:02Z","file_name":"587-2012_plessl_awareness_magazine.pdf"}],"status":"public","has_accepted_license":"1","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_created":"2017-10-17T12:42:46Z","_id":"587","date_updated":"2022-01-06T07:02:44Z","year":"2012","citation":{"short":"C. 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(EMBC)","department":[{"_id":"78"}],"author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:03:21Z","status":"public","title":"Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array","user_id":"3118","year":"2012","citation":{"ieee":"A. Boschmann and M. Platzner, “Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012.","short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. 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