[{"conference":{"end_date":"2021-06-25","start_date":"2021-06-22","name":"31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","location":"Virtual"},"_id":"21610","date_updated":"2022-01-06T06:55:07Z","doi":"https://doi.org/10.1145/3453688.3461506","page":"27-32","citation":{"mla":"Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32, doi:https://doi.org/10.1145/3453688.3461506.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis}, DOI={https://doi.org/10.1145/3453688.3461506}, booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2021}, pages={27–32} }","apa":"Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2021). LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 (pp. 27–32). Virtual: ACM. https://doi.org/10.1145/3453688.3461506","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32. doi:https://doi.org/10.1145/3453688.3461506","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, 27–32. ACM, 2021. https://doi.org/10.1145/3453688.3461506.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32."},"year":"2021","type":"conference","language":[{"iso":"eng"}],"title":"LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis","user_id":"64665","department":[{"_id":"78"}],"publication":"Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","publisher":"ACM","author":[{"last_name":"Awais","id":"64665","first_name":"Muhammad","full_name":"Awais, Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication_status":"published","date_created":"2021-04-13T10:17:47Z","status":"public"},{"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"}],"year":"2021","type":"bachelorsthesis","citation":{"ieee":"J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.","short":"J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib, 2021.","bibtex":"@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner}, year={2021} }","mla":"Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.","ama":"Rehnen JW. Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib.; 2021.","apa":"Rehnen, J. W. (2021). Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib.","chicago":"Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib, 2021."},"_id":"22216","date_updated":"2022-01-06T06:55:29Z","date_created":"2021-05-19T16:56:11Z","status":"public","department":[{"_id":"78"},{"_id":"7"}],"author":[{"last_name":"Rehnen","first_name":"Jakob Werner","full_name":"Rehnen, Jakob Werner"}],"user_id":"49051","title":"Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib"},{"_id":"22309","date_updated":"2022-01-06T06:55:31Z","conference":{"end_date":"2021-07-09","location":"Tampa, Florida USA (Virtual)","name":"IEEE Computer Society Annual Symposium on VLSI","start_date":"2021-07-07"},"type":"conference","year":"2021","citation":{"short":"M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–389.","ieee":"M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.","chicago":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” In Proceedings of IEEE Computer Society Annual Symposium on VLSI, 384–89. IEEE, 2021.","ama":"Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE; 2021:384-389.","apa":"Awais, M., & Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient Approximate Accelerators. Proceedings of IEEE Computer Society Annual Symposium on VLSI, 384–389.","bibtex":"@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2021}, pages={384–389} }","mla":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–89."},"page":"384-389","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime."}],"title":"MCTS-Based Synthesis Towards Efficient Approximate Accelerators","user_id":"64665","author":[{"id":"64665","last_name":"Awais","full_name":"Awais, Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969","first_name":"Muhammad"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"publisher":"IEEE","keyword":["Approximate computing","Design space exploration","Accelerator synthesis"],"department":[{"_id":"78"}],"publication":"Proceedings of IEEE Computer Society Annual Symposium on VLSI","status":"public","date_created":"2021-06-14T14:05:17Z"},{"type":"bachelorsthesis","citation":{"short":"M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems, Paderborn University, Paderborn, 2021.","ieee":"M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.","chicago":"Brede, Mathis. Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.","apa":"Brede, M. (2021). Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University.","ama":"Brede M. Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University; 2021.","bibtex":"@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling of XCS in the Context of Embedded Systems}, publisher={Paderborn University}, author={Brede, Mathis}, year={2021} }","mla":"Brede, Mathis. Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn University, 2021."},"year":"2021","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Hansmeier","id":"49992","first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim"}],"_id":"22483","date_updated":"2022-01-06T06:55:33Z","date_created":"2021-06-21T09:35:03Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"}],"status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Brede, Mathis","first_name":"Mathis","last_name":"Brede"}],"title":"Implementation and Profiling of XCS in the Context of Embedded Systems","user_id":"477","extern":"1","abstract":[{"lang":"eng","text":"This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems."}],"place":"Paderborn"},{"conference":{"end_date":"2021-07-01","start_date":"2021-06-29","name":"International Symposium on Applied Reconfigurable Computing","location":"Virtual conference"},"_id":"21953","date_updated":"2022-02-14T11:03:09Z","doi":"10.1007/978-3-030-79025-7_4","series_title":"Reconfigurable Computing: Architectures, Tools, and Applications","language":[{"iso":"eng"}],"year":"2021","type":"conference","citation":{"apa":"Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., & Platzner, M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig, S. Derrien, P. Diniz, & D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Springer Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-030-79025-7_4","ama":"Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.” In Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science, n.d. https://doi.org/10.1007/978-3-030-79025-7_4.","mla":"Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.” Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), edited by Frank Hannig et al., Springer Lecture Notes in Computer Science, doi:10.1007/978-3-030-79025-7_4.","bibtex":"@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable Computing: Architectures, Tools, and Applications}, title={Timing Optimization for Virtual FPGA Configurations}, DOI={10.1007/978-3-030-79025-7_4}, booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen, Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools, and Applications} }","short":"L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner, in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes in Computer Science, n.d.","ieee":"L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi: 10.1007/978-3-030-79025-7_4."},"user_id":"3118","title":"Timing Optimization for Virtual FPGA Configurations","publication":"Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21)","department":[{"_id":"78"}],"publisher":"Springer Lecture Notes in Computer Science","author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Raeisi Nafchi","full_name":"Raeisi Nafchi, Masood","first_name":"Masood"},{"first_name":"Arne","full_name":"Bockhorn, Arne","last_name":"Bockhorn"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2021-05-04T14:18:46Z","status":"public","publication_status":"accepted","editor":[{"last_name":"Hannig","first_name":"Frank","full_name":"Hannig, Frank"},{"first_name":"Steven","full_name":"Derrien, Steven","last_name":"Derrien"},{"full_name":"Diniz, Pedro","first_name":"Pedro","last_name":"Diniz"},{"last_name":"Chillet","first_name":"Daniel","full_name":"Chillet, Daniel"}]},{"intvolume":" 18","_id":"30906","article_number":"25","issue":"1","type":"journal_article","year":"2021","citation":{"short":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen, Journal of NeuroEngineering and Rehabilitation 18 (2021).","ieee":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,” Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi: 10.1186/s12984-021-00822-6.","apa":"Boschmann, A., Neuhaus, D., Vogt, S., Kaltschmidt, C., Platzner, M., & Dosen, S. (2021). Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. Journal of NeuroEngineering and Rehabilitation, 18(1), Article 25. https://doi.org/10.1186/s12984-021-00822-6","ama":"Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. Journal of NeuroEngineering and Rehabilitation. 2021;18(1). doi:10.1186/s12984-021-00822-6","chicago":"Boschmann, Alexander, Dorothee Neuhaus, Sarah Vogt, Christian Kaltschmidt, Marco Platzner, and Strahinja Dosen. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” Journal of NeuroEngineering and Rehabilitation 18, no. 1 (2021). https://doi.org/10.1186/s12984-021-00822-6.","mla":"Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, 25, Springer Science and Business Media LLC, 2021, doi:10.1186/s12984-021-00822-6.","bibtex":"@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis}, volume={18}, DOI={10.1186/s12984-021-00822-6}, number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja}, year={2021} }"},"abstract":[{"lang":"eng","text":"Abstract\r\n Background\r\n Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training.\r\n \r\n Methods\r\n In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback.\r\n \r\n Results\r\n The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7).\r\n \r\n Conclusion\r\n The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development.\r\n "}],"user_id":"398","keyword":["Health Informatics","Rehabilitation"],"publication":"Journal of NeuroEngineering and Rehabilitation","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"first_name":"Dorothee","full_name":"Neuhaus, Dorothee","last_name":"Neuhaus"},{"full_name":"Vogt, Sarah","first_name":"Sarah","last_name":"Vogt"},{"full_name":"Kaltschmidt, Christian","first_name":"Christian","last_name":"Kaltschmidt"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Dosen, Strahinja","first_name":"Strahinja","last_name":"Dosen"}],"publisher":"Springer Science and Business Media LLC","volume":18,"date_created":"2022-04-18T10:02:20Z","status":"public","date_updated":"2022-04-18T10:04:16Z","doi":"10.1186/s12984-021-00822-6","language":[{"iso":"eng"}],"title":"Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"issn":["1743-0003"]}},{"language":[{"iso":"eng"}],"page":"1-1","citation":{"chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, 2021, 1–1. https://doi.org/10.1109/tc.2021.3107196.","apa":"Rodriguez, A., Otero, A., Platzner, M., & De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2021.3107196","ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:10.1109/tc.2021.3107196.","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={10.1109/tc.2021.3107196}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196."},"year":"2021","type":"journal_article","doi":"10.1109/tc.2021.3107196","_id":"30907","date_updated":"2022-04-18T10:04:21Z","date_created":"2022-04-18T10:03:16Z","status":"public","publication_status":"published","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"department":[{"_id":"78"}],"keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"publication":"IEEE Transactions on Computers","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"last_name":"Rodriguez","full_name":"Rodriguez, Alfonso","first_name":"Alfonso"},{"full_name":"Otero, Andres","first_name":"Andres","last_name":"Otero"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"De la Torre","first_name":"Eduardo","full_name":"De la Torre, Eduardo"}],"user_id":"398","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs"},{"type":"conference","year":"2021","citation":{"apa":"Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online. https://doi.org/10.1145/3468044.3468055","ama":"Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. In: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. Association for Computing Machinery (ACM); 2021. doi:10.1145/3468044.3468055","chicago":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” In HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. New York, NY, United States: Association for Computing Machinery (ACM), 2021. https://doi.org/10.1145/3468044.3468055.","mla":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), 2021, doi:10.1145/3468044.3468055.","bibtex":"@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}, DOI={10.1145/3468044.3468055}, booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }","short":"T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), New York, NY, United States, 2021.","ieee":"T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,” presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi: 10.1145/3468044.3468055."},"language":[{"iso":"eng"}],"doi":"10.1145/3468044.3468055","conference":{"end_date":"2021-06-23","start_date":"2021-06-21","name":"International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21)","location":"Online"},"date_updated":"2022-11-18T10:03:24Z","_id":"29137","publication_status":"published","date_created":"2021-12-27T12:01:02Z","project":[{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"status":"public","publication":"HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","department":[{"_id":"78"}],"publisher":"Association for Computing Machinery (ACM)","author":[{"full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","first_name":"Tim","id":"49992","last_name":"Hansmeier"}],"title":"Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS","user_id":"477","place":"New York, NY, United States"},{"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Sheikh, Muhammad Aamir","first_name":"Muhammad Aamir","last_name":"Sheikh"}],"date_created":"2022-01-26T08:50:52Z","status":"public","abstract":[{"text":"Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption.","lang":"eng"}],"title":"Design and Implementation of a ReconROS-based Obstacle Avoidance System","user_id":"60323","citation":{"short":"M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance System, Paderborn University, 2021.","ieee":"M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.","chicago":"Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based Obstacle Avoidance System. Paderborn University, 2021.","ama":"Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance System. Paderborn University; 2021.","apa":"Sheikh, M. A. (2021). Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University.","mla":"Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based Obstacle Avoidance System. Paderborn University, 2021.","bibtex":"@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh, Muhammad Aamir}, year={2021} }"},"type":"mastersthesis","year":"2021","language":[{"iso":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Lienen, Christian","first_name":"Christian","id":"60323","last_name":"Lienen"}],"date_updated":"2022-01-28T08:30:46Z","_id":"29540"},{"oa":"1","_id":"22764","date_updated":"2022-01-28T08:30:24Z","language":[{"iso":"eng"}],"citation":{"ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.","short":"C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).","mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.","bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, journal={arXiv:2107.07208}, author={Lienen, Christian and Platzner, Marco}, year={2021} }","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. arXiv:210707208. Published online 2021.","apa":"Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. In arXiv:2107.07208."},"type":"preprint","year":"2021","page":"19","main_file_link":[{"open_access":"1","url":"https://arxiv.org/abs/2107.07208"}],"user_id":"60323","title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","abstract":[{"text":"Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.","lang":"eng"}],"status":"public","date_created":"2021-07-16T05:38:56Z","author":[{"id":"60323","last_name":"Lienen","full_name":"Lienen, Christian","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"arXiv:2107.07208"}]