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Advances in Parallel Computing. IOS Press, 2007.","ama":"Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756.","apa":"Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.","ieee":"T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.","short":"T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756."},"year":"2007","language":[{"iso":"eng"}],"series_title":"Advances in Parallel Computing","date_updated":"2022-01-06T06:50:50Z","_id":"10735","intvolume":" 15"},{"date_created":"2019-10-04T21:57:25Z","status":"public","publication_identifier":{"isbn":["9781424410590","9781424410606"]},"publication_status":"published","department":[{"_id":"78"}],"publication":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","user_id":"398","title":"A Many-Core Implementation Based on the Reconfigurable Mesh Model","language":[{"iso":"eng"}],"type":"conference","citation":{"short":"H. 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Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.","bibtex":"@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }","apa":"Lübbers, E., & Platzner, M. (2007). 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Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344.","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.","apa":"Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344"},"type":"conference","year":"2006","page":"345-348","doi":"10.1109/FPT.2006.270344","date_updated":"2022-01-06T06:56:05Z","_id":"2401","status":"public","date_created":"2018-04-17T13:43:21Z","publisher":"IEEE Computer Society","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","keyword":["temporal partitioning","retiming","ILP"],"title":"Optimal Temporal Partitioning based on Slowdown and Retiming","user_id":"24135","abstract":[{"text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ","lang":"eng"}]},{"user_id":"3118","title":"Multi-objective Intrinsic Hardware Evolution","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)","status":"public","date_created":"2019-07-10T11:28:14Z","_id":"10688","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"chicago":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","ama":"Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.","apa":"Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD).","mla":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","bibtex":"@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }","short":"P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","ieee":"P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. 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Paderborn University, 2006.","bibtex":"@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }","mla":"Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006.","short":"R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006.","ieee":"R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006."},"type":"bachelorsthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10716"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13624","type":"conference","citation":{"apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE.","ama":"Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006.","mla":"Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","bibtex":"@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }","short":"K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006."},"year":"2006","language":[{"iso":"eng"}],"title":"Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions","user_id":"398","status":"public","date_created":"2019-10-04T21:48:42Z","author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"last_name":"Mühlenbernd","first_name":"Roland","full_name":"Mühlenbernd, Roland"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)"},{"_id":"13625","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"type":"conference","year":"2006","citation":{"ieee":"K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","short":"K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","apa":"Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).","ama":"Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006."},"user_id":"398","title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices","publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","department":[{"_id":"78"}],"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-10-04T21:51:29Z","status":"public"},{"title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","user_id":"398","date_created":"2019-10-04T21:53:12Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","publisher":"IEEE CS Press","author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"_id":"13626","date_updated":"2022-01-06T06:51:40Z","year":"2006","citation":{"chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006."},"type":"conference","language":[{"iso":"eng"}]},{"abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","user_id":"24135","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy"],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","status":"public","date_created":"2018-04-17T14:34:03Z","_id":"2411","date_updated":"2022-01-06T06:56:07Z","doi":"10.1109/ASAP.2005.69","type":"conference","citation":{"ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","apa":"Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69."},"year":"2005","page":"213-218"}]