[{"status":"public","funded_apc":"1","title":"Software/Hardware Co-Verification for Custom Instruction Set Processors","_id":"27841","keyword":["Software Analysis","Abstract Interpretation","Custom Instruction","Hardware Verification"],"author":[{"first_name":"Marie-Christine","last_name":"Jakobs","full_name":"Jakobs, Marie-Christine"},{"id":"22398","full_name":"Pauck, Felix","last_name":"Pauck","first_name":"Felix"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"first_name":"Heike","last_name":"Wehrheim","id":"573","full_name":"Wehrheim, Heike"},{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"}],"date_updated":"2023-01-18T08:34:50Z","doi":"10.1109/ACCESS.2021.3131213","publisher":"IEEE","quality_controlled":"1","year":"2021","publication_status":"published","publication":"IEEE Access","type":"journal_article","department":[{"_id":"78"}],"abstract":[{"lang":"eng","text":"Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques."}],"language":[{"iso":"eng"}],"user_id":"22398","date_created":"2021-11-25T14:12:22Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"}],"citation":{"ama":"Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213","ieee":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.","chicago":"Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.","mla":"Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.","apa":"Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. https://doi.org/10.1109/ACCESS.2021.3131213","short":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).","bibtex":"@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }"}},{"type":"conference","publication":"2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)","publication_status":"published","project":[{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"SFB 901: SFB 901","_id":"1"}],"citation":{"mla":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021, doi:10.1109/vlsi-soc53125.2021.9606974.","ama":"Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). ; 2021. doi:10.1109/vlsi-soc53125.2021.9606974","ieee":"Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.","chicago":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021. https://doi.org/10.1109/vlsi-soc53125.2021.9606974.","short":"Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.","apa":"Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). https://doi.org/10.1109/vlsi-soc53125.2021.9606974","bibtex":"@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing}, DOI={10.1109/vlsi-soc53125.2021.9606974}, booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }"},"user_id":"72764","date_created":"2021-12-30T00:02:24Z","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"doi":"10.1109/vlsi-soc53125.2021.9606974","date_updated":"2023-04-19T15:03:45Z","year":"2021","_id":"29138","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","orcid":"0000-0002-1837-2254","last_name":"Ahmed","first_name":"Qazi Arbab"}],"status":"public","title":"Hardware Trojans in Reconfigurable Computing"},{"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"citation":{"bibtex":"@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble, France}, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={10.23919/DATE51398.2021.9474026}, booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021} }","mla":"Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:10.23919/DATE51398.2021.9474026.","ama":"Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:10.23919/DATE51398.2021.9474026","ieee":"Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.","chicago":"Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble, France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.","short":"Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.","apa":"Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026"},"has_accepted_license":"1","user_id":"72764","abstract":[{"text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.","lang":"eng"}],"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"publication":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2023-05-11T09:16:15Z","doi":"10.23919/DATE51398.2021.9474026","date_updated":"2023-05-11T09:16:34Z","author":[{"orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab","last_name":"Ahmed","id":"72764","full_name":"Ahmed, Qazi Arbab"},{"last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"ddc":["006"],"_id":"20681","title":"Malicious Routing: Circumventing Bitstream-level Verification for FPGAs","publication_identifier":{"eisbn":["978-3-9819263-5-4"]},"date_created":"2020-12-07T14:03:00Z","oa":"1","type":"conference","publication_status":"published","place":"Alpexpo | Grenoble, France","year":"2021","publisher":"2021 Design, Automation and Test in Europe Conference (DATE)","conference":{"end_date":"2021-02-05","start_date":"2021-02-01","name":"Design, Automation and Test in Europe Conference (DATE'21)","location":"Alpexpo | Grenoble, France"},"main_file_link":[{"open_access":"1"}],"file":[{"file_name":"1812.pdf","creator":"qazi","file_id":"44752","file_size":394011,"date_updated":"2023-05-11T09:16:15Z","relation":"main_file","content_type":"application/pdf","access_level":"closed","success":1,"date_created":"2023-05-11T09:16:15Z"}],"status":"public"},{"_id":"30909","author":[{"full_name":"Clausing, Lennart","id":"74287","first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034"}],"status":"public","title":"ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip","publication_status":"published","publication":"Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"398","date_created":"2022-04-18T10:17:47Z","citation":{"apa":"Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3468044.3468056","bibtex":"@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={10.1145/3468044.3468056}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }","chicago":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” In Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM, 2021. https://doi.org/10.1145/3468044.3468056.","ieee":"L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.","ama":"Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2021. doi:10.1145/3468044.3468056","mla":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021, doi:10.1145/3468044.3468056.","short":"L. Clausing, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021."},"project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","grant_number":"160364472","_id":"1"}],"date_updated":"2023-07-09T13:09:11Z","doi":"10.1145/3468044.3468056","publisher":"ACM","year":"2021"},{"author":[{"first_name":"Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"id":"55631","full_name":"Jentzsch, Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch","first_name":"Felix"},{"full_name":"Kuschel, Maurice","first_name":"Maurice","last_name":"Kuschel"},{"first_name":"Rahil ","last_name":"Arshad","full_name":"Arshad, Rahil "},{"full_name":"Rautmare, Sneha","first_name":"Sneha","last_name":"Rautmare"},{"full_name":"Manjunatha, Suraj","first_name":"Suraj","last_name":"Manjunatha"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"full_name":"Schollbach, Dirk ","last_name":"Schollbach","first_name":"Dirk "}],"_id":"30908","title":"FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics","status":"public","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"citation":{"mla":"Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.","ieee":"H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.","chicago":"Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil Arshad, Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk Schollbach. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” In Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Springer, 2021. https://doi.org/10.1007/978-3-030-93736-2_27.","ama":"Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Springer; 2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27","short":"H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021, title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}, DOI={https://doi.org/10.1007/978-3-030-93736-2_27}, booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }, year={2021} }","apa":"Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare, S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021). FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. Machine Learning and Principles and Practice of Knowledge Discovery in Databases. https://doi.org/10.1007/978-3-030-93736-2_27"},"project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"_id":"1","grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"}],"date_created":"2022-04-18T10:16:55Z","user_id":"477","type":"conference","publication":" Machine Learning and Principles and Practice of Knowledge Discovery in Databases","year":"2021","date_updated":"2023-09-15T15:09:07Z","doi":"https://doi.org/10.1007/978-3-030-93736-2_27","publisher":"Springer"},{"department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"language":[{"iso":"eng"}],"citation":{"apa":"Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC).","mla":"Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","ieee":"Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","ama":"Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). ; 2020.","chicago":"Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","short":"Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","bibtex":"@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul and Platzner, Marco}, year={2020} }"},"user_id":"398","date_created":"2018-07-20T14:07:15Z","type":"conference","publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","year":"2020","date_updated":"2022-01-06T06:59:25Z","author":[{"last_name":" Guetttatfi","first_name":"Zakarya","full_name":" Guetttatfi, Zakarya"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"_id":"3583","title":"Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices","status":"public"},{"author":[{"last_name":"Chandrakar","first_name":"Khushboo","full_name":"Chandrakar, Khushboo"}],"_id":"21324","title":"Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis","status":"public","department":[{"_id":"78"},{"_id":"7"}],"language":[{"iso":"eng"}],"user_id":"49051","date_created":"2021-03-01T09:19:29Z","citation":{"bibtex":"@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020} }","short":"K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis, 2020.","ieee":"K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis. 2020.","ama":"Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis.; 2020.","chicago":"Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis, 2020.","mla":"Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis. 2020.","apa":"Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis."},"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"type":"mastersthesis","year":"2020","supervisor":[{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"full_name":"Witschen, Linus Matthias","id":"49051","last_name":"Witschen","first_name":"Linus Matthias"}],"date_updated":"2022-01-06T06:54:54Z"},{"date_updated":"2022-01-06T06:54:59Z","year":"2020","supervisor":[{"full_name":"Lienen, Christian","id":"60323","first_name":"Christian","last_name":"Lienen"},{"last_name":"Platzner","first_name":"Marco","id":"398","full_name":"Platzner, Marco"}],"type":"bachelorsthesis","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"abstract":[{"text":"Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation.","lang":"eng"}],"citation":{"short":"L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application, 2020.","chicago":"Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application, 2020.","ieee":"L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing Application. 2020.","ama":"Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application.; 2020.","mla":"Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application. 2020.","bibtex":"@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020} }","apa":"Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a Video Processing Application."},"date_created":"2021-03-10T07:07:01Z","user_id":"60323","status":"public","title":"Evaluation of a ReconOS-ROS Combination based on a Video Processing Application","_id":"21432","author":[{"full_name":"Henke, Luca-Sebastian","first_name":"Luca-Sebastian","last_name":"Henke"}]},{"date_created":"2021-03-31T08:58:59Z","user_id":"398","citation":{"mla":"Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020, doi:10.1007/978-3-662-59084-3_9.","ieee":"C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020.","chicago":"Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” In Machine Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg, 2020. https://doi.org/10.1007/978-3-662-59084-3_9.","ama":"Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In: Machine Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg; 2020. doi:10.1007/978-3-662-59084-3_9","short":"C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems (ML4CPS 2017), Berlin, Heidelberg, 2020.","bibtex":"@inproceedings{Gatica_Platzner_2020, place={Berlin, Heidelberg}, title={Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures}, DOI={10.1007/978-3-662-59084-3_9}, booktitle={Machine Learning for Cyber Physical Systems (ML4CPS 2017)}, author={Gatica, Carlos Paiz and Platzner, Marco}, year={2020} }","apa":"Gatica, C. P., & Platzner, M. (2020). Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In Machine Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-59084-3_9"},"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"publication":"Machine Learning for Cyber Physical Systems (ML4CPS 2017)","type":"conference","publication_status":"published","place":"Berlin, Heidelberg","year":"2020","doi":"10.1007/978-3-662-59084-3_9","date_updated":"2022-01-06T06:55:06Z","author":[{"first_name":"Carlos Paiz","last_name":"Gatica","full_name":"Gatica, Carlos Paiz"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"_id":"21584","title":"Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures","status":"public","publication_identifier":{"isbn":["9783662590836","9783662590843"],"issn":["2522-8579","2522-8587"]}},{"type":"journal_article","publication_status":"published","date_created":"2020-07-06T11:21:30Z","publisher":"IEEE","page":"2084 - 2088","intvolume":" 28","year":"2020","issue":"9","keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"funded_apc":"1","status":"public","publication":"IEEE Transactions On Very Large Scale Integration Systems","citation":{"apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020.","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems 28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.","mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.","short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088."},"project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"1","name":"SFB 901"}],"user_id":"49051","language":[{"iso":"eng"}],"abstract":[{"text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.","lang":"eng"}],"department":[{"_id":"78"}],"date_updated":"2022-01-06T06:53:09Z","doi":"10.1109/TVLSI.2020.3008061","quality_controlled":"1","_id":"17358","author":[{"last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","id":"49051"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"article_type":"original","publication_identifier":{"eissn":["1557-9999"],"issn":["1063-8210"]},"title":"Proof-carrying Approximate Circuits","volume":28}]