[{"abstract":[{"text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.","lang":"eng"}],"article_type":"original","user_id":"49051","keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"publication":"IEEE Transactions On Very Large Scale Integration Systems","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Witschen","id":"49051","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"volume":28,"date_created":"2020-07-06T11:21:30Z","status":"public","intvolume":" 28","_id":"17358","issue":"9","funded_apc":"1","page":"2084 - 2088","year":"2020","citation":{"chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems 28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061","mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }","short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020."},"type":"journal_article","title":"Proof-carrying Approximate Circuits","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"issn":["1063-8210"],"eissn":["1557-9999"]},"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"date_updated":"2022-01-06T06:53:09Z","doi":"10.1109/TVLSI.2020.3008061","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:53:09Z","_id":"17369","language":[{"iso":"eng"}],"citation":{"bibtex":"@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific Cache Mappings}, journal={International Journal of Hybrid intelligent Systems}, publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2020} }","mla":"Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” International Journal of Hybrid Intelligent Systems, IOS Press, 2020.","ama":"Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings. International Journal of Hybrid intelligent Systems. 2020.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2020). Evolution of Application-Specific Cache Mappings. International Journal of Hybrid Intelligent Systems.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific Cache Mappings.” International Journal of Hybrid Intelligent Systems, 2020.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.","short":"N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent Systems (2020)."},"year":"2020","type":"journal_article","user_id":"398","title":"Evolution of Application-Specific Cache Mappings","department":[{"_id":"78"}],"publication":"International Journal of Hybrid intelligent Systems","publisher":"IOS Press","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2020-07-10T18:55:30Z","status":"public"},{"date_updated":"2022-01-06T06:54:35Z","language":[{"iso":"eng"}],"title":"Search Space Characterization for AxC Synthesis","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"publication_status":"accepted","department":[{"_id":"78"}],"_id":"20748","page":"2","type":"preprint","citation":{"mla":"Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020).","bibtex":"@article{Witschen_Wiersema_Platzner, title={Search Space Characterization for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020), n.d.","ama":"Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .","short":"L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.)."},"year":"2020","user_id":"3118","ddc":["000"],"abstract":[{"lang":"eng","text":"On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies.\r\nIn the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. \r\nIn this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification.\r\nIn our experimental results, we present the runtimes of our approach."}],"date_created":"2020-12-15T15:13:49Z","status":"public","has_accepted_license":"1","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2020-12-15T15:11:06Z","creator":"witschen","file_id":"20749","file_size":250870,"access_level":"closed","file_name":"witschen20_axc.pdf","date_created":"2020-12-15T15:11:06Z"}],"file_date_updated":"2020-12-15T15:11:06Z","publication":"Fifth Workshop on Approximate Computing (AxC 2020)","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"conference":{"name":"International Conference on Field Programmable Technology (ICFPT)","start_date":"2020-12-09","end_date":"2020-12-11"},"_id":"20750","date_updated":"2022-01-06T06:54:35Z","year":"2020","type":"conference","citation":{"mla":"Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","bibtex":"@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian and Platzner, Marco and Rinner, Bernhard}, year={2020} }","ama":"Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT). ; 2020.","apa":"Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT).","chicago":"Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” In Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","ieee":"C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for ROS2 Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","short":"C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020."},"language":[{"iso":"eng"}],"title":"ReconROS: Flexible Hardware Acceleration for ROS2 Applications","user_id":"398","date_created":"2020-12-16T05:20:01Z","status":"public","publication":"Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"78"}],"author":[{"full_name":"Lienen, Christian","first_name":"Christian","id":"60323","last_name":"Lienen"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"}]},{"user_id":"74287","title":"Implementing Machine Learning Functions as PYNQ FPGA Overlays","status":"public","date_created":"2020-12-21T13:59:55Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"author":[{"first_name":"Simon","full_name":"Thiele, Simon","last_name":"Thiele"}],"department":[{"_id":"78"}],"_id":"20820","date_updated":"2022-01-06T06:54:40Z","supervisor":[{"first_name":"Lennart","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","last_name":"Clausing","id":"74287"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}],"citation":{"ieee":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","short":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","mla":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","bibtex":"@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ FPGA Overlays}, author={Thiele, Simon}, year={2020} }","chicago":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","ama":"Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.; 2020.","apa":"Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA Overlays."},"type":"bachelorsthesis","year":"2020"},{"department":[{"_id":"78"}],"author":[{"full_name":"Jaganath, Vivek","first_name":"Vivek","last_name":"Jaganath"}],"date_created":"2020-12-21T14:02:42Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area T","_id":"82"},{"_id":"83","name":"SFB 901 -Subproject T1"}],"status":"public","title":"Extension and Evaluation of Python-based High-Level Synthesis Tool Flows","user_id":"74287","year":"2020","type":"mastersthesis","citation":{"ama":"Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows.; 2020.","apa":"Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level Synthesis Tool Flows.","chicago":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.","bibtex":"@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }","mla":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows. 2020.","short":"V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.","ieee":"V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020."},"supervisor":[{"last_name":"Clausing","id":"74287","first_name":"Lennart","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"language":[{"iso":"eng"}],"_id":"20821","date_updated":"2022-01-06T06:54:40Z"},{"page":"1756-1764","year":"2020","citation":{"apa":"Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106","ama":"Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764. doi:10.1145/3377929.3398106","chicago":"Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “An Adaption Mechanism for the Error Threshold of XCSF.” In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1756–64. New York, NY, United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3398106.","bibtex":"@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }","mla":"Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.” GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.","short":"T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764.","ieee":"T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi: 10.1145/3377929.3398106."},"type":"conference","conference":{"location":"Cancún, Mexico","name":"International Workshop on Learning Classifier Systems (IWLCS 2020)","start_date":"2020-07-08","end_date":"2020-07-12"},"_id":"17063","date_created":"2020-05-27T14:14:58Z","status":"public","publication":"GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion","publisher":"Association for Computing Machinery (ACM)","author":[{"last_name":"Hansmeier","id":"49992","first_name":"Tim","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"477","language":[{"iso":"eng"}],"doi":"10.1145/3377929.3398106","date_updated":"2022-01-06T06:53:03Z","project":[{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"publication_status":"published","publication_identifier":{"isbn":["978-1-4503-7127-8"]},"department":[{"_id":"78"}],"title":"An Adaption Mechanism for the Error Threshold of XCSF","place":"New York, NY, United States"},{"citation":{"short":"J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable Computing (2020) 1–19.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, pp. 1–19, 2020.","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management for FPGA-Based Systems.” International Journal of Reconfigurable Computing, 2020, 1–19. https://doi.org/10.1155/2020/2808710.","ama":"Anwer J, Meisner S, Platzner M. Dynamic Reliability Management for FPGA-Based Systems. International Journal of Reconfigurable Computing. 2020:1-19. doi:10.1155/2020/2808710","apa":"Anwer, J., Meisner, S., & Platzner, M. (2020). Dynamic Reliability Management for FPGA-Based Systems. International Journal of Reconfigurable Computing, 1–19. https://doi.org/10.1155/2020/2808710","bibtex":"@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management for FPGA-Based Systems}, DOI={10.1155/2020/2808710}, journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.” International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710."},"year":"2020","type":"journal_article","page":"1-19","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:53:04Z","_id":"17092","doi":"10.1155/2020/2808710","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"International Journal of Reconfigurable Computing","department":[{"_id":"78"}],"publication_identifier":{"issn":["1687-7195","1687-7209"]},"publication_status":"published","status":"public","date_created":"2020-06-15T11:25:07Z","abstract":[{"text":"Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.","lang":"eng"}],"title":"Dynamic Reliability Management for FPGA-Based Systems","user_id":"398"},{"language":[{"iso":"eng"}],"year":"2020","type":"journal_article","citation":{"short":"K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer, P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical Systems Accepted for Publication (2020) 1–24.","ieee":"K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.","chicago":"Bellman, K., N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer, P. R. Lewis, Marco Platzner, N. TaheriNejad, and K. Tammemäe. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems Accepted for Publication (2020): 1–24.","apa":"Bellman, K., Dutt, N., Esterle, L., Herkersdorf, A., Jantsch, A., Landauer, C., … Tammemäe, K. (2020). Self-aware Cyber-Physical Systems. ACM Transactions on Cyber-Physical Systems, Accepted for Publication, 1–24.","ama":"Bellman K, Dutt N, Esterle L, et al. Self-aware Cyber-Physical Systems. ACM Transactions on Cyber-Physical Systems. 2020;Accepted for Publication:1-24.","mla":"Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.","bibtex":"@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020, title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication}, journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C. and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020}, pages={1–24} }"},"page":"1-24","_id":"15836","date_updated":"2022-01-06T06:52:37Z","author":[{"last_name":"Bellman","full_name":"Bellman, K.","first_name":"K."},{"full_name":"Dutt, N.","first_name":"N.","last_name":"Dutt"},{"last_name":"Esterle","first_name":"L.","full_name":"Esterle, L."},{"first_name":"A.","full_name":"Herkersdorf, A.","last_name":"Herkersdorf"},{"last_name":"Jantsch","first_name":"A.","full_name":"Jantsch, A."},{"last_name":"Landauer","first_name":"C.","full_name":"Landauer, C."},{"last_name":"R. Lewis","first_name":"P.","full_name":"R. Lewis, P."},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"TaheriNejad","full_name":"TaheriNejad, N.","first_name":"N."},{"last_name":"Tammemäe","first_name":"K.","full_name":"Tammemäe, K."}],"department":[{"_id":"78"}],"publication":"ACM Transactions on Cyber-Physical Systems","status":"public","date_created":"2020-02-06T15:05:45Z","volume":"Accepted for Publication","user_id":"398","title":"Self-aware Cyber-Physical Systems"},{"department":[{"_id":"78"}],"publication":"Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020","publisher":"ACM","author":[{"orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","first_name":"Muhammad","id":"64665","last_name":"Awais"},{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication_status":"published","date_created":"2020-03-02T15:49:38Z","status":"public","abstract":[{"lang":"eng","text":"Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \\textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. "}],"title":"A Hybrid Synthesis Methodology for Approximate Circuits","user_id":"64665","page":"421-426","citation":{"short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952","apa":"Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China: ACM. https://doi.org/10.1145/3386263.3406952","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952}, booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2020}, pages={421–426} }","mla":"Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.” Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952."},"type":"conference","year":"2020","language":[{"iso":"eng"}],"conference":{"name":"ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020","location":"Beijing, China"},"_id":"16213","date_updated":"2022-01-06T06:52:45Z","doi":"10.1145/3386263.3406952"}]