[{"language":[{"iso":"eng"}],"type":"conference","citation":{"mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.","bibtex":"@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}, DOI={10.1007/978-3-319-27992-3_1}, booktitle={Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015}, pages={1–11} }","apa":"Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing. https://doi.org/10.1007/978-3-319-27992-3_1","ama":"Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 1–11. Springer International Publishing, 2015. https://doi.org/10.1007/978-3-319-27992-3_1.","ieee":"T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 2015, pp. 1–11.","short":"T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11."},"year":"2015","page":"1-11","doi":"10.1007/978-3-319-27992-3_1","date_updated":"2022-01-06T06:51:29Z","_id":"13153","status":"public","date_created":"2019-09-09T09:07:46Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publisher":"Springer International Publishing","author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers","user_id":"40778","title":"Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning"},{"article_number":"859425","_id":"296","intvolume":" 2015","type":"journal_article","year":"2015","citation":{"ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425"},"ddc":["040"],"user_id":"15278","abstract":[{"text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.","lang":"eng"}],"volume":2015,"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:49Z","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"Hindawi","publication":"International Journal of Reconfigurable Computing (IJRC)","file_date_updated":"2018-03-20T07:47:56Z","file":[{"access_level":"closed","file_name":"296-859425.pdf","date_created":"2018-03-20T07:47:56Z","date_updated":"2018-03-20T07:47:56Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":2993898,"file_id":"1444","creator":"florida"}],"doi":"10.1155/2015/859425","date_updated":"2023-09-26T13:29:08Z","language":[{"iso":"eng"}],"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]},"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.","lang":"eng"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:51Z","file":[{"file_id":"1442","creator":"florida","file_size":1176620,"relation":"main_file","date_updated":"2019-08-01T09:10:44Z","content_type":"application/pdf","date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","access_level":"open_access"}],"quality_controlled":"1","author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file_date_updated":"2019-08-01T09:10:44Z","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","_id":"303","type":"conference","citation":{"ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"year":"2015"},{"language":[{"iso":"eng"}],"citation":{"short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }"},"year":"2015","type":"conference","doi":"10.1145/2675743.2771824","_id":"1773","date_updated":"2023-09-26T13:31:01Z","status":"public","date_created":"2018-03-23T14:09:33Z","publisher":"ACM","quality_controlled":"1","author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"first_name":"J.","full_name":"T. Anderson, J.","last_name":"T. Anderson"},{"last_name":"Borga","first_name":"A.","full_name":"Borga, A."},{"first_name":"H.","full_name":"Boterenbrood, H.","last_name":"Boterenbrood"},{"last_name":"Chen","full_name":"Chen, H.","first_name":"H."},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"full_name":"Drake, G.","first_name":"G.","last_name":"Drake"},{"last_name":"Francis","full_name":"Francis, D.","first_name":"D."},{"full_name":"Gorini, B.","first_name":"B.","last_name":"Gorini"},{"full_name":"Lanni, F.","first_name":"F.","last_name":"Lanni"},{"first_name":"Giovanna","full_name":"Lehmann-Miotto, Giovanna","last_name":"Lehmann-Miotto"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"last_name":"Narevicius","full_name":"Narevicius, J.","first_name":"J."},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Roich","full_name":"Roich, A.","first_name":"A."},{"full_name":"Ryu, S.","first_name":"S.","last_name":"Ryu"},{"last_name":"P. Schreuder","first_name":"F.","full_name":"P. Schreuder, F."},{"first_name":"Wainer","full_name":"Vandelli, Wainer","last_name":"Vandelli"},{"full_name":"Vermeulen, J.","first_name":"J.","last_name":"Vermeulen"},{"full_name":"Zhang, J.","first_name":"J.","last_name":"Zhang"}],"publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm"},{"title":"Aktuelles Schlagwort: Approximate Computing","user_id":"15278","status":"public","date_created":"2018-03-23T13:58:34Z","publisher":"Springer","quality_controlled":"1","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Schreier, Peter J.","first_name":"Peter J.","last_name":"Schreier"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"publication":"Informatik Spektrum","keyword":["approximate computing","survey"],"doi":"10.1007/s00287-015-0911-z","issue":"5","_id":"1768","date_updated":"2023-09-26T13:30:22Z","citation":{"ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z."},"year":"2015","type":"journal_article","page":"396-399","language":[{"iso":"eng"}]},{"date_updated":"2023-09-26T13:31:44Z","doi":"10.7873/DATE.2015.1124","language":[{"iso":"eng"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"_id":"238","page":"1078-1083","type":"conference","year":"2015","citation":{"short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124."},"abstract":[{"lang":"eng","text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator."}],"ddc":["040"],"user_id":"15278","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","file_date_updated":"2018-03-21T10:29:49Z","publisher":"EDA Consortium / IEEE","author":[{"full_name":"Damschen, Marvin","first_name":"Marvin","last_name":"Damschen"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","file":[{"access_level":"closed","date_created":"2018-03-21T10:29:49Z","file_name":"238-plessl15_date.pdf","date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":380552,"creator":"florida","file_id":"1500"}],"date_created":"2017-10-17T12:41:38Z","has_accepted_license":"1","status":"public"},{"date_updated":"2022-01-06T06:59:18Z","doi":"10.1007/978-3-319-05960-0_30","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"title":"Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"editor":[{"first_name":"Diana","full_name":"Goehringer, Diana","last_name":"Goehringer"},{"full_name":"Santambrogio, MarcoDomenico","first_name":"MarcoDomenico","last_name":"Santambrogio"},{"last_name":"Cardoso","full_name":"Cardoso, JoãoM.P.","first_name":"JoãoM.P."},{"last_name":"Bertels","full_name":"Bertels, Koen","first_name":"Koen"}],"_id":"347","type":"conference","citation":{"ieee":"S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.","short":"S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.","bibtex":"@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}, DOI={10.1007/978-3-319-05960-0_30}, booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner, Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture Notes in Computer Science} }","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels, 283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.","apa":"Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio, J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer. https://doi.org/10.1007/978-3-319-05960-0_30","ama":"Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30"},"year":"2014","page":"283-290","abstract":[{"text":"Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead.","lang":"eng"}],"user_id":"398","ddc":["040"],"file":[{"file_name":"347-meisner13_xx_SFB1__1_.pdf","date_created":"2018-03-20T07:26:16Z","access_level":"closed","file_id":"1417","creator":"florida","file_size":1168877,"relation":"main_file","success":1,"date_updated":"2018-03-20T07:26:16Z","content_type":"application/pdf"}],"publisher":"Springer","author":[{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"file_date_updated":"2018-03-20T07:26:16Z","publication":"Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:59Z"},{"type":"conference","year":"2014","citation":{"ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2."},"page":"14-25","series_title":"Lecture Notes in Computer Science","issue":"8427","doi":"10.1007/978-3-319-09165-5_2","date_updated":"2022-01-06T06:53:20Z","_id":"1782","status":"public","date_created":"2018-03-26T13:50:37Z","publisher":"Springer","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proc. 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Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.","chicago":"Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771.","ama":"Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771","apa":"Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174). https://doi.org/10.1109/FPT.2014.7082771","bibtex":"@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}, year={2014}, pages={167–174} }","mla":"Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771."},"page":"167-174","ddc":["040"],"user_id":"477","abstract":[{"lang":"eng","text":"Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:09Z","author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"full_name":"Drzevitzky, Stephanie","first_name":"Stephanie","last_name":"Drzevitzky"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"file_date_updated":"2018-03-20T06:57:44Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file":[{"creator":"florida","file_id":"1380","file_size":404328,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T06:57:44Z","file_name":"399-wiersema14_fpt_IEEE_approved.pdf","date_created":"2018-03-20T06:57:44Z","access_level":"closed"}]},{"series_title":"LNCS","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:00:14Z","doi":"10.1007/978-3-319-10181-1_19","department":[{"_id":"77"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"editor":[{"last_name":"Albert","full_name":"Albert, Elvira","first_name":"Elvira"},{"last_name":"Sekerinski","full_name":"Sekerinski, Emil","first_name":"Emil"}],"title":"Integrating Software and Hardware Verification","type":"conference","citation":{"mla":"Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.” Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.","bibtex":"@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19}, booktitle={Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors}, year={2014}, pages={307–322}, collection={LNCS} }","chicago":"Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim. “Integrating Software and Hardware Verification.” In Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19.","ama":"Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19","apa":"Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322). https://doi.org/10.1007/978-3-319-10181-1_19","ieee":"M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in Proceedings of the 11th International Conference on Integrated Formal Methods (iFM), 2014, pp. 307–322.","short":"M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322."},"year":"2014","page":"307-322","_id":"408","file":[{"content_type":"application/pdf","date_updated":"2018-03-16T11:35:28Z","success":1,"relation":"main_file","file_size":561325,"file_id":"1364","creator":"florida","access_level":"closed","date_created":"2018-03-16T11:35:28Z","file_name":"408-jakobs14_ifm.pdf"}],"author":[{"last_name":"Jakobs","full_name":"Jakobs, Marie-Christine","first_name":"Marie-Christine"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Wehrheim","id":"573","first_name":"Heike","full_name":"Wehrheim, Heike"}],"file_date_updated":"2018-03-16T11:35:28Z","publication":"Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:11Z","abstract":[{"lang":"eng","text":"Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques."}],"user_id":"477","ddc":["040"]},{"page":"1-6 ","type":"conference","year":"2014","citation":{"short":"T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","apa":"Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514","ama":"Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–6, 2014. https://doi.org/10.1109/ReConFig.2014.7032514.","bibtex":"@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={10.1109/ReConFig.2014.7032514}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2014}, pages={1–6} }","mla":"Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514."},"_id":"433","date_created":"2017-10-17T12:42:16Z","status":"public","has_accepted_license":"1","file":[{"file_name":"433-wiersema14_reconfig_IEEE_approved.pdf","date_created":"2018-03-16T11:30:58Z","access_level":"closed","file_size":369333,"file_id":"1355","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-16T11:30:58Z","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:30:58Z","author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Bockhorn","full_name":"Bockhorn, Arne","first_name":"Arne"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"477","ddc":["040"],"abstract":[{"lang":"eng","text":"Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA."}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032514","date_updated":"2022-01-06T07:00:56Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"department":[{"_id":"78"}],"title":"Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA"},{"language":[{"iso":"eng"}],"citation":{"ieee":"L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, pp. 361–374, 2014.","short":"L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374.","mla":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.","bibtex":"@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={10.1109/TCIAIG.2014.2346997}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }","chicago":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” IEEE Transactions on Computational Intelligence and AI in Games 6, no. 3 (2014): 361–74. https://doi.org/10.1109/TCIAIG.2014.2346997.","ama":"Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374. doi:10.1109/TCIAIG.2014.2346997","apa":"Schaefers, L., & Platzner, M. (2014). A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games, 6(3), 361–374. https://doi.org/10.1109/TCIAIG.2014.2346997"},"year":"2014","type":"journal_article","page":"361-374","issue":"3","doi":"10.1109/TCIAIG.2014.2346997","intvolume":" 6","_id":"10602","date_updated":"2022-01-06T06:50:47Z","status":"public","date_created":"2019-07-10T09:22:43Z","volume":6,"author":[{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"IEEE Transactions on Computational Intelligence and AI in Games","department":[{"_id":"78"}],"user_id":"3118","title":"A Novel Technique and its Application to Computer Go"},{"_id":"10603","date_updated":"2022-01-06T06:50:47Z","intvolume":" 63","issue":"12","doi":"10.1109/TC.2013.174","language":[{"iso":"eng"}],"page":"2919 - 2932","citation":{"mla":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.","bibtex":"@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={10.1109/TC.2013.174}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }","ama":"Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174","apa":"Giefers, H., & Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers, 63(12), 2919–2932. https://doi.org/10.1109/TC.2013.174","chicago":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” IEEE Transactions on Computers 63, no. 12 (2014): 2919–32. https://doi.org/10.1109/TC.2013.174.","ieee":"H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.","short":"H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932."},"year":"2014","type":"journal_article","user_id":"398","title":"An FPGA-based Reconfigurable Mesh Many-Core","publication":"IEEE Transactions on Computers","department":[{"_id":"78"}],"author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-07-10T09:22:44Z","status":"public","volume":63},{"title":"FPGA Redundancy Configurations: An Automated Design Space Exploration","user_id":"3118","date_created":"2019-07-10T09:32:58Z","status":"public","department":[{"_id":"78"}],"publication":"Reconfigurable Architectures Workshop (RAW)","author":[{"last_name":"Anwer","full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"}],"doi":"10.1109/IPDPSW.2014.37","date_updated":"2022-01-06T06:50:48Z","_id":"10621","citation":{"ieee":"J. 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Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4."},"year":"2014","type":"conference","language":[{"iso":"eng"}]},{"author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"publication":"2014 {IEEE} Intl. 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EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","bibtex":"@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }","chicago":"König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","apa":"König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University.","ama":"König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.","ieee":"F. König, EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University, 2014.","short":"F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese, Paderborn University, 2014."},"_id":"10679","date_updated":"2022-01-06T06:50:49Z"},{"title":"Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA","user_id":"3118","status":"public","date_created":"2019-07-10T11:38:27Z","publisher":"Paderborn University","author":[{"first_name":"Benjamin","full_name":"Koch, Benjamin","last_name":"Koch"}],"department":[{"_id":"78"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10701","citation":{"short":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","ieee":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","chicago":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","apa":"Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.","ama":"Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.","mla":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. 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Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University.","chicago":"Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014.","ieee":"R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University, 2014.","short":"R. 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Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","short":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.","mla":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","bibtex":"@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }","ama":"Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.","apa":"Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University.","chicago":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014."}},{"date_updated":"2022-01-06T06:50:50Z","_id":"10733","page":"133","year":"2014","citation":{"mla":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Logos Verlag Berlin GmbH, 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","ama":"Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.","apa":"Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.","chicago":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","ieee":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014."},"type":"dissertation","language":[{"iso":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","user_id":"3118","abstract":[{"lang":"eng","text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches."}],"place":"Berlin","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"date_created":"2019-07-10T11:58:06Z","status":"public","department":[{"_id":"78"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Schäfers","full_name":"Schäfers, Lars","first_name":"Lars"}]},{"_id":"10738","date_updated":"2022-01-06T06:50:50Z","year":"2014","citation":{"ieee":"C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence After a Power System Blackout,” in IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","short":"C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","mla":"Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","apa":"Shen, C., Kaufmann, P., & Braun, M. (2014). Optimizing the Generator Start-up Sequence After a Power System Blackout. In IEEE Power and Energy Society General Meeting (IEEE GM).","ama":"Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: IEEE Power and Energy Society General Meeting (IEEE GM). ; 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” In IEEE Power and Energy Society General Meeting (IEEE GM), 2014."},"type":"conference","user_id":"3118","title":"Optimizing the Generator Start-up Sequence After a Power System Blackout","status":"public","date_created":"2019-07-10T11:59:36Z","author":[{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"department":[{"_id":"78"}],"publication":"IEEE Power and Energy Society General Meeting (IEEE GM)"},{"publisher":"IEEE","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"publication":"Power Systems Computation Conference (PSCC)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:59:37Z","title":"A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm","user_id":"3118","type":"conference","citation":{"ama":"Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: Power Systems Computation Conference (PSCC). IEEE; 2014.","apa":"Shen, C., Kaufmann, P., & Braun, M. (2014). A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In Power Systems Computation Conference (PSCC). IEEE.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” In Power Systems Computation Conference (PSCC). IEEE, 2014.","mla":"Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” Power Systems Computation Conference (PSCC), IEEE, 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","short":"C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm,” in Power Systems Computation Conference (PSCC), 2014."},"year":"2014","_id":"10739","date_updated":"2022-01-06T06:50:50Z"},{"supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"eng"}],"citation":{"chicago":"Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","ama":"Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.","apa":"Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.","mla":"Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","bibtex":"@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }","short":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","ieee":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014."},"type":"mastersthesis","year":"2014","_id":"10744","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"author":[{"first_name":"Sebastian","full_name":"Surmund, Sebastian","last_name":"Surmund"}],"publisher":"Paderborn University","date_created":"2019-07-10T12:00:45Z","status":"public","user_id":"3118","title":"Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA"},{"user_id":"3118","title":"Applications of Evolutionary Computation - 17th European Conference, EvoApplications","place":"Granada, Spain","status":"public","date_created":"2019-07-10T12:06:33Z","volume":8602,"author":[{"first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"last_name":"Eiben","full_name":"Eiben, A.E.","first_name":"A.E."},{"first_name":"Alexandros","full_name":"Agapitos, Alexandros","last_name":"Agapitos"},{"last_name":"Sim{\\~o}es","full_name":"Sim{\\~o}es, Anabela","first_name":"Anabela"},{"last_name":"G.B. Tettamanzi","full_name":"G.B. Tettamanzi, Andrea","first_name":"Andrea"},{"full_name":"Della Cioppa, Antonio","first_name":"Antonio","last_name":"Della Cioppa"},{"full_name":"M. Mora, Antonio","first_name":"Antonio","last_name":"M. Mora"},{"last_name":"Cotta","full_name":"Cotta, Carlos","first_name":"Carlos"},{"full_name":"Tarantino, Ernesto","first_name":"Ernesto","last_name":"Tarantino"},{"last_name":"Haasdijk","first_name":"Evert","full_name":"Haasdijk, Evert"},{"last_name":"Divina","full_name":"Divina, Federico","first_name":"Federico"},{"last_name":"Fern{\\'a}ndez de Vega","full_name":"Fern{\\'a}ndez de Vega, Francisco","first_name":"Francisco"},{"first_name":"Giovanni","full_name":"Squillero, Giovanni","last_name":"Squillero"},{"first_name":"Ivanoe","full_name":"De Falco, Ivanoe","last_name":"De Falco"},{"full_name":"Ignacio Hidalgo, J.","first_name":"J.","last_name":"Ignacio Hidalgo"},{"last_name":"Sim","full_name":"Sim, Kevin","first_name":"Kevin"},{"first_name":"Kyrre","full_name":"Glette, Kyrre","last_name":"Glette"},{"full_name":"Zhang, Mengjie","first_name":"Mengjie","last_name":"Zhang"},{"full_name":"Urquhart, Neil","first_name":"Neil","last_name":"Urquhart"},{"last_name":"Burelli","full_name":"Burelli, Paolo","first_name":"Paolo"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Po{\\v s}{\\'\\i}k, Petr","first_name":"Petr","last_name":"Po{\\v s}{\\'\\i}k"},{"last_name":"Schaefer","first_name":"Robert","full_name":"Schaefer, Robert"},{"last_name":"Drechsler","full_name":"Drechsler, Rolf","first_name":"Rolf"},{"full_name":"Antipolis, Sophia","first_name":"Sophia","last_name":"Antipolis"},{"last_name":"Cagnoni","first_name":"Stefano","full_name":"Cagnoni, Stefano"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"first_name":"William","full_name":"S. Bush (editors), William","last_name":"S. Bush (editors)"}],"publisher":"Springer","department":[{"_id":"78"}],"intvolume":" 8602","_id":"10756","date_updated":"2022-01-06T06:50:50Z","year":"2014","citation":{"ieee":"A. I. Esparcia-Alc{\\’a}zar et al., Applications of Evolutionary Computation - 17th European Conference, EvoApplications, vol. 8602. Granada, Spain: Springer, 2014.","short":"A. I. Esparcia-Alc{\\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\\~o}es, A. G.B. Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk, F. Divina, F. Fern{\\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo, K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\\v s}{\\’\\i}k, R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush (editors), Applications of Evolutionary Computation - 17th European Conference, EvoApplications, Springer, Granada, Spain, 2014.","bibtex":"@book{I. Esparcia-Alc{\\’a}zar_Eiben_Agapitos_Sim{\\~o}es_G.B. Tettamanzi_Della Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 17th European Conference, EvoApplications}, volume={8602}, publisher={Springer}, author={I. Esparcia-Alc{\\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros and Sim{\\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }","mla":"I. Esparcia-Alc{\\’a}zar, Anna, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol. 8602, Springer, 2014.","apa":"I. Esparcia-Alc{\\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\\~o}es, A., G.B. Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). Applications of Evolutionary Computation - 17th European Conference, EvoApplications (Vol. 8602). Granada, Spain: Springer.","ama":"I. Esparcia-Alc{\\’a}zar A, Eiben AE, Agapitos A, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol 8602. Granada, Spain: Springer; 2014.","chicago":"I. Esparcia-Alc{\\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela Sim{\\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014."},"type":"book","series_title":"Lecture Notes in Computer Science"},{"_id":"10764","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/DFT.2014.6962108","language":[{"iso":"eng"}],"year":"2014","citation":{"short":"J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.","ieee":"J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 177–184.","ama":"Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108","apa":"Anwer, J., & Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 177–184). IEEE. https://doi.org/10.1109/DFT.2014.6962108","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 177–84. IEEE, 2014. https://doi.org/10.1109/DFT.2014.6962108.","bibtex":"@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}, DOI={10.1109/DFT.2014.6962108}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2014}, pages={177–184} }","mla":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84, doi:10.1109/DFT.2014.6962108."},"type":"conference","page":"177-184","user_id":"398","title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:07:05Z"},{"publisher":"IEEE","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel","last_name":"Gaillardon"},{"full_name":"Yazdani, Majid","first_name":"Majid","last_name":"Yazdani"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"department":[{"_id":"78"}],"publication":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","status":"public","date_created":"2019-07-10T12:10:16Z","extern":"1","user_id":"3118","title":"Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection","language":[{"iso":"eng"}],"type":"conference","year":"2014","citation":{"mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014, title={Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}, DOI={10.1109/NANOARCH.2014.6880479}, booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli, G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani, and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 163–68. IEEE, 2014. https://doi.org/10.1109/NANOARCH.2014.6880479.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2014, pp. 163–168.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168."},"page":"163-168","date_updated":"2022-01-06T06:50:50Z","_id":"10773","doi":"10.1109/NANOARCH.2014.6880479"},{"title":"Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go","user_id":"40778","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"2014 IEEE Conference on Computational Intelligence and Games","status":"public","date_created":"2019-09-09T09:09:31Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"13154","date_updated":"2022-01-06T06:51:29Z","doi":"10.1109/CIG.2014.6932863","type":"conference","year":"2014","citation":{"short":"T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.","ieee":"T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go,” in 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.","chicago":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” In 2014 IEEE Conference on Computational Intelligence and Games, 1–8, 2014. https://doi.org/10.1109/CIG.2014.6932863.","ama":"Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863","apa":"Graf, T., & Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In 2014 IEEE Conference on Computational Intelligence and Games (pp. 1–8). https://doi.org/10.1109/CIG.2014.6932863","bibtex":"@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}, DOI={10.1109/CIG.2014.6932863}, booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2014}, pages={1–8} }","mla":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863."},"page":"1-8","language":[{"iso":"eng"}]},{"file_date_updated":"2018-03-20T07:29:58Z","publication":"Logiken strukturbildender Prozesse: Automatismen","quality_controlled":"1","publisher":"Wilhelm Fink","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file":[{"creator":"florida","file_id":"1424","file_size":2848154,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:29:58Z","date_created":"2018-03-20T07:29:58Z","file_name":"335-2014_plessl_automatismen.pdf","access_level":"closed"}],"date_created":"2017-10-17T12:41:57Z","status":"public","has_accepted_license":"1","abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"ddc":["040"],"user_id":"15278","page":"123-144","year":"2014","type":"book_chapter","citation":{"ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","apa":"Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014."},"_id":"335","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"publication_identifier":{"isbn":["978-3-7705-5730-1"]},"publication_status":"published","editor":[{"full_name":"Künsemöller, Jörn","first_name":"Jörn","last_name":"Künsemöller"},{"full_name":"Eke, Norber Otto","first_name":"Norber Otto","last_name":"Eke"},{"first_name":"Lioba","full_name":"Foit, Lioba","last_name":"Foit"},{"full_name":"Kaerlein, Timo","first_name":"Timo","last_name":"Kaerlein"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"place":"Paderborn","title":"Verschiebungen an der Grenze zwischen Hardware und Software","series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}],"date_updated":"2023-09-26T13:32:49Z"},{"file":[{"content_type":"application/pdf","date_updated":"2018-03-20T07:02:02Z","relation":"main_file","success":1,"file_size":330193,"creator":"florida","file_id":"1387","access_level":"closed","date_created":"2018-03-20T07:02:02Z","file_name":"388-plessl14_arc.pdf"}],"quality_controlled":"1","publisher":"Springer International Publishing","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","file_date_updated":"2018-03-20T07:02:02Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:07Z","volume":8405,"abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"user_id":"15278","ddc":["040"],"citation":{"short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13."},"year":"2014","type":"conference","page":"144-155","_id":"388","intvolume":" 8405","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13"},{"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2013.12.001","date_updated":"2023-09-26T13:33:06Z","volume":38,"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:02Z","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"Elsevier","quality_controlled":"1","file_date_updated":"2018-03-20T07:20:31Z","publication":"Microprocessors and Microsystems","file":[{"date_created":"2018-03-20T07:20:31Z","file_name":"363-plessl13_micpro.pdf","access_level":"closed","file_size":1499996,"creator":"florida","file_id":"1408","date_updated":"2018-03-20T07:20:31Z","content_type":"application/pdf","relation":"main_file","success":1}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"year":"2014","type":"journal_article","citation":{"short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }"},"page":"911-919","issue":"8, Part B","_id":"363","intvolume":" 38"},{"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"date_created":"2017-10-17T12:42:05Z","has_accepted_license":"1","status":"public","file":[{"file_id":"1397","creator":"florida","file_size":1003907,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","date_created":"2018-03-20T07:14:20Z","file_name":"377-FCCM14.pdf","access_level":"closed"}],"keyword":["coldboot"],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","file_date_updated":"2018-03-20T07:14:20Z","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"}],"publisher":"IEEE","quality_controlled":"1","_id":"377","page":"222-229","year":"2014","citation":{"apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67."},"type":"conference"},{"ddc":["040"],"user_id":"15278","abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"volume":7,"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:03Z","publisher":"ACM","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file_date_updated":"2018-03-20T07:19:19Z","file":[{"date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","access_level":"closed","file_size":916052,"creator":"florida","file_id":"1406","content_type":"application/pdf","date_updated":"2018-03-20T07:19:19Z","relation":"main_file","success":1}],"article_number":"13","issue":"2","intvolume":" 7","_id":"365","type":"journal_article","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596"},"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"doi":"10.1145/2617596","date_updated":"2023-09-26T13:33:31Z","language":[{"iso":"eng"}]},{"doi":"10.1109/MM.2013.110","date_updated":"2023-09-26T13:32:31Z","language":[{"iso":"eng"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"issue":"1","_id":"328","intvolume":" 34","page":"60-71","year":"2014","citation":{"apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110."},"type":"journal_article","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"date_created":"2017-10-17T12:41:55Z","has_accepted_license":"1","status":"public","volume":34,"file":[{"file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z","access_level":"closed","file_id":"1426","creator":"florida","file_size":1877185,"relation":"main_file","success":1,"date_updated":"2018-03-20T07:31:40Z","content_type":"application/pdf"}],"file_date_updated":"2018-03-20T07:31:40Z","publication":"IEEE Micro","quality_controlled":"1","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Keller","first_name":"Ariane","full_name":"Keller, Ariane"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Bernhard","full_name":"Plattner, Bernhard","last_name":"Plattner"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"IEEE"},{"user_id":"15278","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Pogliani","full_name":"Pogliani, Marcello","first_name":"Marcello"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco","first_name":"Marco"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","status":"public","project":[{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2018-03-26T13:40:14Z","_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","language":[{"iso":"eng"}],"type":"conference","citation":{"mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."},"year":"2014","page":"142-149"},{"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509","language":[{"iso":"eng"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"_id":"439","citation":{"short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509."},"type":"conference","year":"2014","page":"1-8","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"user_id":"15278","ddc":["040"],"file":[{"content_type":"application/pdf","date_updated":"2018-03-16T11:29:52Z","success":1,"relation":"main_file","file_size":557362,"file_id":"1353","creator":"florida","access_level":"closed","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf"}],"author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-16T11:29:52Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:17Z"},{"year":"2014","type":"conference","citation":{"short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }"},"page":"1-8","_id":"406","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:11Z","file":[{"access_level":"closed","file_name":"406-ReConFig14.pdf","date_created":"2018-03-16T11:37:42Z","relation":"main_file","success":1,"date_updated":"2018-03-16T11:37:42Z","content_type":"application/pdf","file_id":"1366","creator":"florida","file_size":932852}],"publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032535","date_updated":"2023-09-26T13:36:40Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching"},{"doi":"10.1007/978-3-319-05960-0_38","_id":"1780","date_updated":"2023-09-26T13:36:20Z","language":[{"iso":"eng"}],"type":"conference","year":"2014","citation":{"short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38."},"user_id":"15278","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","status":"public","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2018-03-26T13:45:35Z","publisher":"Springer","quality_controlled":"1","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Copolla","first_name":"Marcello","full_name":"Copolla, Marcello"},{"first_name":"Karim","full_name":"Djafarian, Karim","last_name":"Djafarian"},{"last_name":"Koranaros","full_name":"Koranaros, George","first_name":"George"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"last_name":"Paolino","full_name":"Paolino, Michele","first_name":"Michele"},{"last_name":"Pell","first_name":"Oliver","full_name":"Pell, Oliver"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"publication_identifier":{"issn":["0163-5964"]},"title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:35:58Z","doi":"10.1145/2641361.2641372","keyword":["funding-maxup","tet_topic_hpc"],"publication":"ACM SIGARCH Computer Architecture News","publisher":"ACM","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Förstner","id":"158","first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862"}],"quality_controlled":"1","date_created":"2018-03-26T13:42:34Z","status":"public","volume":41,"user_id":"15278","page":"65-70","type":"journal_article","year":"2014","citation":{"short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372","apa":"Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372."},"intvolume":" 41","_id":"1779","issue":"5"},{"status":"public","date_created":"2019-07-11T11:51:51Z","publication_identifier":{"isbn":["978-3-8325-3530-8"]},"publication_status":"published","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"}],"user_id":"3118","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","place":"Berlin","abstract":[{"text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.","lang":"eng"}],"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"year":"2013","citation":{"mla":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }","ama":"Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH.","chicago":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","ieee":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013."},"type":"dissertation","page":"249","date_updated":"2022-01-06T06:51:04Z","_id":"11619"},{"publisher":"IEEE","author":[{"last_name":"Kasap","first_name":"Server","full_name":"Kasap, Server"},{"last_name":"Redif","full_name":"Redif, Soydan","first_name":"Soydan"}],"publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","department":[{"_id":"27"},{"_id":"78"}],"status":"public","date_created":"2018-03-26T14:48:53Z","user_id":"24135","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","year":"2013","citation":{"mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). 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Springer.","bibtex":"@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers, Lars and Platzner, Marco}, year={2013} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings of the International Conference on Computers and Games (CG), Springer, 2013."},"language":[{"iso":"eng"}]},{"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2013.6718394","date_updated":"2023-09-26T13:37:35Z","date_created":"2017-10-17T12:42:35Z","status":"public","has_accepted_license":"1","file":[{"access_level":"closed","file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z","date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":822680,"file_id":"1294","creator":"florida"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","keyword":["coldboot"],"file_date_updated":"2018-03-15T10:36:08Z","quality_controlled":"1","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"page":"386-389","type":"conference","citation":{"ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394."},"year":"2013","_id":"528"},{"_id":"505","year":"2013","citation":{"ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232"},"type":"conference","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","success":1,"relation":"main_file","file_size":1040834,"creator":"florida","file_id":"1308","access_level":"closed","file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Meyer auf der Heide","id":"15523","first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm"}],"date_created":"2017-10-17T12:42:30Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:38:20Z","doi":"10.1109/ISORC.2013.6913232","language":[{"iso":"eng"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}]},{"language":[{"iso":"eng"}],"page":"64-73","year":"2013","citation":{"bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73."},"type":"conference","date_updated":"2023-09-26T13:38:05Z","_id":"1787","doi":"10.1109/IPDPSW.2013.136","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Suess, Tim","first_name":"Tim","last_name":"Suess"},{"full_name":"Schoenrock, Andrew","first_name":"Andrew","last_name":"Schoenrock"},{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2018-03-26T14:51:05Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"status":"public","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"place":"Washington, DC, USA","user_id":"15278","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer"},{"date_created":"2018-03-29T14:34:48Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"full_name":"Redif, Soydan","first_name":"Soydan","last_name":"Redif"}],"publisher":"IEEE Computer Society","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","page":"135-140","year":"2012","type":"conference","citation":{"ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140.","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125."},"doi":"10.1109/FPT.2012.6412125","date_updated":"2022-01-06T06:54:42Z","_id":"2097"},{"title":"FPGA implementation of a second-order convolutive blind signal separation algorithm","user_id":"24135","status":"public","date_created":"2018-03-29T14:43:18Z","author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"last_name":"Redif","full_name":"Redif, Soydan","first_name":"Soydan"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","department":[{"_id":"27"},{"_id":"78"}],"date_updated":"2022-01-06T06:54:42Z","_id":"2100","citation":{"short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012."},"year":"2012","type":"conference"},{"doi":"10.1109/CIG.2012.6374143","date_updated":"2022-01-06T06:54:42Z","_id":"2103","page":"91-99","type":"conference","year":"2012","citation":{"short":"M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.","ieee":"M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.","chicago":"Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.","ama":"Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143","apa":"Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143","bibtex":"@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }","mla":"Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143."},"title":"Comparison of Bayesian Move Prediction Systems for Computer Go","user_id":"24135","date_created":"2018-03-29T14:59:35Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Conf. on Computational Intelligence and Games (CIG)","publisher":"IEEE","author":[{"last_name":"Wistuba","first_name":"Martin","full_name":"Wistuba, Martin"},{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}]},{"title":"STIR: Software for Tomographic Image Reconstruction Release 2","user_id":"24135","volume":57,"date_created":"2018-04-03T09:02:27Z","status":"public","publication":"Physics in Medicine and Biology","department":[{"_id":"27"},{"_id":"78"}],"publisher":"IOP Publishing","author":[{"full_name":"Thielemans, Kris","first_name":"Kris","last_name":"Thielemans"},{"first_name":"Charalampos","full_name":"Tsoumpas, Charalampos","last_name":"Tsoumpas"},{"full_name":"Mustafovic, Sanida","first_name":"Sanida","last_name":"Mustafovic"},{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"last_name":"Aguiar","full_name":"Aguiar, Pablo","first_name":"Pablo"},{"last_name":"Dikaios","full_name":"Dikaios, Nikolaos","first_name":"Nikolaos"},{"last_name":"W Jacobson","first_name":"Matthew","full_name":"W Jacobson, Matthew"}],"doi":"10.1088/0031-9155/57/4/867","issue":"4","_id":"2172","intvolume":" 57","date_updated":"2022-01-06T06:55:12Z","page":"867-883","year":"2012","type":"journal_article","citation":{"bibtex":"@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }","mla":"Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.","chicago":"Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel, Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no. 4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.","ama":"Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867","apa":"Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867","ieee":"K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.","short":"K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883."}},{"_id":"2173","date_updated":"2022-01-06T06:55:12Z","intvolume":" 100","doi":"10.1080/00207217.2012.751343","issue":"12","citation":{"ieee":"S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012.","short":"S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651.","mla":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343.","bibtex":"@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }","chicago":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.","apa":"Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343","ama":"Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343"},"type":"journal_article","year":"2012","page":"1646-1651","title":"Parallel algorithm for computation of second-order sequential best rotations","user_id":"24135","author":[{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"},{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"}],"publisher":"Taylor & Francis","department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Journal of Electronics","volume":100,"status":"public","date_created":"2018-04-03T09:05:36Z"},{"publication":"Journal of Computers","department":[{"_id":"27"},{"_id":"78"}],"publisher":"Academy Publishers","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"first_name":"Khaled","full_name":"Benkrid, Khaled","last_name":"Benkrid"}],"date_created":"2018-04-03T09:08:00Z","status":"public","volume":7,"user_id":"24135","title":"Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer","page":"1312-1328","citation":{"short":"S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328.","ieee":"S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012.","apa":"Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328.","ama":"Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.","chicago":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.","mla":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.","bibtex":"@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }"},"type":"journal_article","year":"2012","date_updated":"2022-01-06T06:55:12Z","_id":"2174","intvolume":" 7","issue":"6"},{"title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","publication_status":"published","project":[{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"oa":"1","date_updated":"2022-01-06T07:02:44Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"477","abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"lang":"ger","text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit."}],"date_created":"2017-10-17T12:42:46Z","status":"public","has_accepted_license":"1","file_date_updated":"2018-03-15T08:38:19Z","publisher":"Universität Paderborn","author":[{"last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie","first_name":"Stephanie"}],"file":[{"access_level":"closed","file_name":"586-Drzevitzky-PhD_01.pdf","date_created":"2018-03-15T08:38:19Z","content_type":"application/pdf","date_updated":"2018-03-15T08:38:19Z","relation":"main_file","success":1,"file_size":1438436,"file_id":"1261","creator":"florida"}],"_id":"586","page":"114","type":"dissertation","year":"2012","citation":{"mla":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. 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In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores."}],"year":"2012","citation":{"ama":"Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.","apa":"Giefers, H. (2012). Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH.","chicago":"Giefers, Heiner. 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Awareness Magazine, 2012.","bibtex":"@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }"},"date_updated":"2022-01-06T06:51:36Z","_id":"13462","status":"public","date_created":"2019-09-30T09:24:09Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"publisher":"Awareness Magazine","author":[{"last_name":"Lewis","first_name":"Peter","full_name":"Lewis, Peter"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Yao","first_name":"Xin","full_name":"Yao, Xin"}],"department":[{"_id":"78"}],"user_id":"398","title":"An outlook for self-awareness in computing systems"},{"page":"189-196","citation":{"chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370."},"type":"conference","year":"2012","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"_id":"2106","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"file_date_updated":"2019-02-13T09:04:46Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Meyer, Björn","first_name":"Björn","last_name":"Meyer"},{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"}],"file":[{"content_type":"application/pdf","date_updated":"2019-02-13T09:04:46Z","success":1,"relation":"main_file","file_size":2148787,"file_id":"7638","creator":"fossie","access_level":"closed","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_created":"2019-02-13T09:04:46Z"}],"date_created":"2018-03-29T15:04:25Z","status":"public","has_accepted_license":"1","abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"ddc":["000"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:13Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","citation":{"bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126."},"type":"journal_article","year":"2012","page":"110-126","issue":"2","_id":"2108","intvolume":" 36","status":"public","date_created":"2018-03-29T15:12:38Z","volume":36,"quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","user_id":"15278"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","file":[{"file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z","access_level":"closed","file_size":730144,"file_id":"1246","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","relation":"main_file","success":1}],"author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","quality_controlled":"1","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"user_id":"15278","ddc":["040"],"type":"conference","year":"2012","citation":{"ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745"},"page":"1-8","_id":"615"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:47Z","file":[{"file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z","access_level":"closed","file_id":"1257","creator":"florida","file_size":371235,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z"}],"quality_controlled":"1","publisher":"IEEE","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"}],"file_date_updated":"2018-03-15T08:33:18Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","user_id":"15278","ddc":["040"],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"type":"conference","year":"2012","citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773."},"page":"1-8","_id":"591","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z"},{"author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file":[{"date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_id":"1249","creator":"florida","file_size":146789,"relation":"main_file","success":1,"date_updated":"2018-03-15T08:14:17Z","content_type":"application/pdf"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:50Z","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"ddc":["040"],"user_id":"15278","citation":{"ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012."},"type":"conference","year":"2012","page":"8-9","_id":"609","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","page":"559-565","type":"conference","citation":{"bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565."},"year":"2012","_id":"567","file":[{"date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","access_level":"closed","file_size":288508,"file_id":"1275","creator":"florida","date_updated":"2018-03-15T10:20:24Z","content_type":"application/pdf","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"full_name":"Carreras, Carlos","first_name":"Carlos","last_name":"Carreras"},{"first_name":"Roberto","full_name":"Sierra, Roberto","last_name":"Sierra"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"IEEE","quality_controlled":"1","date_created":"2017-10-17T12:42:42Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. 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As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"date_created":"2017-10-17T12:42:51Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-03-15T06:49:03Z","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Rüthing","first_name":"Christoph","full_name":"Rüthing, Christoph"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"file":[{"file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","access_level":"closed","creator":"florida","file_id":"1247","file_size":202923,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z"}]},{"user_id":"15278","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","status":"public","date_created":"2018-04-03T09:18:33Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"quality_controlled":"1","keyword":["funding-enhance"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. 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