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Paderborn University, 2014.","apa":"Hagedorn, C. (2014). Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University.","ama":"Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University; 2014.","chicago":"Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University, 2014.","ieee":"C. Hagedorn, Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University, 2014.","short":"C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014."}},{"date_updated":"2022-01-06T06:50:49Z","_id":"10674","doi":"10.1109/FPL.2014.6927437","citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437"},"year":"2014","type":"conference","page":"1-4","language":[{"iso":"eng"}],"title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","user_id":"3118","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"status":"public","project":[{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_created":"2019-07-10T11:18:01Z"},{"_id":"10677","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/ICES.2014.7008719","citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37."},"year":"2014","type":"conference","page":"31-37","language":[{"iso":"eng"}],"title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","user_id":"3118","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"department":[{"_id":"78"}],"publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","status":"public","date_created":"2019-07-10T11:23:00Z"},{"title":"EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese","user_id":"3118","date_created":"2019-07-10T11:23:20Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"König","full_name":"König, Fabian","first_name":"Fabian"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10679","type":"bachelorsthesis","year":"2014","citation":{"apa":"König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University.","ama":"König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.","chicago":"König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","bibtex":"@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }","mla":"König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","short":"F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese, Paderborn University, 2014.","ieee":"F. König, EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University, 2014."},"supervisor":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"}],"language":[{"iso":"eng"}]},{"type":"mastersthesis","year":"2014","citation":{"ieee":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","short":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","mla":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","bibtex":"@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin}, year={2014} }","chicago":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","ama":"Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.","apa":"Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University."},"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"_id":"10701","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T11:38:27Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Koch","full_name":"Koch, Benjamin","first_name":"Benjamin"}],"title":"Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA","user_id":"3118"},{"_id":"10715","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.","ieee":"R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University, 2014.","chicago":"Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014.","ama":"Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University; 2014.","apa":"Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University.","mla":"Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014.","bibtex":"@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }"},"type":"mastersthesis","year":"2014","language":[{"iso":"eng"}],"title":"Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs","user_id":"3118","status":"public","date_created":"2019-07-10T11:48:26Z","author":[{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"}],"publisher":"Paderborn University","department":[{"_id":"78"}]},{"status":"public","date_created":"2019-07-10T11:58:05Z","author":[{"last_name":"Rüthing","first_name":"Christoph","full_name":"Rüthing, Christoph"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"user_id":"3118","title":"The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores","language":[{"iso":"eng"}],"type":"bachelorsthesis","year":"2014","citation":{"short":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.","ieee":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","ama":"Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.","apa":"Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University.","chicago":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","mla":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","bibtex":"@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }"},"_id":"10732","date_updated":"2022-01-06T06:50:50Z"},{"year":"2014","citation":{"ama":"Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.","apa":"Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.","chicago":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","mla":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Logos Verlag Berlin GmbH, 2014.","short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.","ieee":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014."},"type":"dissertation","page":"133","supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"language":[{"iso":"eng"}],"_id":"10733","date_updated":"2022-01-06T06:50:50Z","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"publication_status":"published","status":"public","date_created":"2019-07-10T11:58:06Z","publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Schäfers","full_name":"Schäfers, Lars","first_name":"Lars"}],"department":[{"_id":"78"}],"title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","user_id":"3118","place":"Berlin","abstract":[{"lang":"eng","text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches."}]},{"date_updated":"2022-01-06T06:50:50Z","_id":"10738","type":"conference","citation":{"apa":"Shen, C., Kaufmann, P., & Braun, M. (2014). Optimizing the Generator Start-up Sequence After a Power System Blackout. In IEEE Power and Energy Society General Meeting (IEEE GM).","ama":"Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: IEEE Power and Energy Society General Meeting (IEEE GM). ; 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” In IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","mla":"Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","short":"C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence After a Power System Blackout,” in IEEE Power and Energy Society General Meeting (IEEE GM), 2014."},"year":"2014","user_id":"3118","title":"Optimizing the Generator Start-up Sequence After a Power System Blackout","author":[{"last_name":"Shen","full_name":"Shen, Cong","first_name":"Cong"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"department":[{"_id":"78"}],"publication":"IEEE Power and Energy Society General Meeting (IEEE GM)","status":"public","date_created":"2019-07-10T11:59:36Z"},{"user_id":"3118","title":"A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"publisher":"IEEE","publication":"Power Systems Computation Conference (PSCC)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:59:37Z","_id":"10739","date_updated":"2022-01-06T06:50:50Z","type":"conference","citation":{"ieee":"C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm,” in Power Systems Computation Conference (PSCC), 2014.","short":"C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","mla":"Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” Power Systems Computation Conference (PSCC), IEEE, 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” In Power Systems Computation Conference (PSCC). IEEE, 2014.","ama":"Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: Power Systems Computation Conference (PSCC). IEEE; 2014.","apa":"Shen, C., Kaufmann, P., & Braun, M. (2014). A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In Power Systems Computation Conference (PSCC). IEEE."},"year":"2014"},{"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Surmund","first_name":"Sebastian","full_name":"Surmund, Sebastian"}],"date_created":"2019-07-10T12:00:45Z","status":"public","user_id":"3118","title":"Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA","supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2014","citation":{"ieee":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","short":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","mla":"Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","bibtex":"@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }","ama":"Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.","apa":"Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.","chicago":"Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014."},"_id":"10744","date_updated":"2022-01-06T06:50:50Z"},{"citation":{"apa":"I. Esparcia-Alc{\\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\\~o}es, A., G.B. Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). Applications of Evolutionary Computation - 17th European Conference, EvoApplications (Vol. 8602). Granada, Spain: Springer.","ama":"I. Esparcia-Alc{\\’a}zar A, Eiben AE, Agapitos A, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol 8602. Granada, Spain: Springer; 2014.","chicago":"I. Esparcia-Alc{\\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela Sim{\\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014.","bibtex":"@book{I. Esparcia-Alc{\\’a}zar_Eiben_Agapitos_Sim{\\~o}es_G.B. Tettamanzi_Della Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 17th European Conference, EvoApplications}, volume={8602}, publisher={Springer}, author={I. Esparcia-Alc{\\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros and Sim{\\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }","mla":"I. Esparcia-Alc{\\’a}zar, Anna, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol. 8602, Springer, 2014.","short":"A. I. Esparcia-Alc{\\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\\~o}es, A. G.B. Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk, F. Divina, F. Fern{\\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo, K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\\v s}{\\’\\i}k, R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush (editors), Applications of Evolutionary Computation - 17th European Conference, EvoApplications, Springer, Granada, Spain, 2014.","ieee":"A. I. Esparcia-Alc{\\’a}zar et al., Applications of Evolutionary Computation - 17th European Conference, EvoApplications, vol. 8602. Granada, Spain: Springer, 2014."},"year":"2014","type":"book","series_title":"Lecture Notes in Computer Science","intvolume":" 8602","_id":"10756","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:06:33Z","status":"public","volume":8602,"department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"I. Esparcia-Alc{\\'a}zar, Anna","first_name":"Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"first_name":"A.E.","full_name":"Eiben, A.E.","last_name":"Eiben"},{"full_name":"Agapitos, Alexandros","first_name":"Alexandros","last_name":"Agapitos"},{"last_name":"Sim{\\~o}es","full_name":"Sim{\\~o}es, Anabela","first_name":"Anabela"},{"last_name":"G.B. Tettamanzi","full_name":"G.B. Tettamanzi, Andrea","first_name":"Andrea"},{"last_name":"Della Cioppa","full_name":"Della Cioppa, Antonio","first_name":"Antonio"},{"first_name":"Antonio","full_name":"M. Mora, Antonio","last_name":"M. Mora"},{"full_name":"Cotta, Carlos","first_name":"Carlos","last_name":"Cotta"},{"last_name":"Tarantino","first_name":"Ernesto","full_name":"Tarantino, Ernesto"},{"full_name":"Haasdijk, Evert","first_name":"Evert","last_name":"Haasdijk"},{"first_name":"Federico","full_name":"Divina, Federico","last_name":"Divina"},{"last_name":"Fern{\\'a}ndez de Vega","first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"last_name":"Squillero","full_name":"Squillero, Giovanni","first_name":"Giovanni"},{"full_name":"De Falco, Ivanoe","first_name":"Ivanoe","last_name":"De Falco"},{"first_name":"J.","full_name":"Ignacio Hidalgo, J.","last_name":"Ignacio Hidalgo"},{"last_name":"Sim","full_name":"Sim, Kevin","first_name":"Kevin"},{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"full_name":"Zhang, Mengjie","first_name":"Mengjie","last_name":"Zhang"},{"first_name":"Neil","full_name":"Urquhart, Neil","last_name":"Urquhart"},{"last_name":"Burelli","first_name":"Paolo","full_name":"Burelli, Paolo"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Po{\\v s}{\\'\\i}k","full_name":"Po{\\v s}{\\'\\i}k, Petr","first_name":"Petr"},{"full_name":"Schaefer, Robert","first_name":"Robert","last_name":"Schaefer"},{"full_name":"Drechsler, Rolf","first_name":"Rolf","last_name":"Drechsler"},{"full_name":"Antipolis, Sophia","first_name":"Sophia","last_name":"Antipolis"},{"first_name":"Stefano","full_name":"Cagnoni, Stefano","last_name":"Cagnoni"},{"last_name":"Thanh Nguyen","full_name":"Thanh Nguyen, Trung","first_name":"Trung"},{"last_name":"S. Bush (editors)","first_name":"William","full_name":"S. Bush (editors), William"}],"user_id":"3118","title":"Applications of Evolutionary Computation - 17th European Conference, EvoApplications","place":"Granada, Spain"},{"title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","user_id":"398","publisher":"IEEE","author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","status":"public","date_created":"2019-07-10T12:07:05Z","date_updated":"2022-01-06T06:50:50Z","_id":"10764","doi":"10.1109/DFT.2014.6962108","year":"2014","type":"conference","citation":{"chicago":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 177–84. IEEE, 2014. https://doi.org/10.1109/DFT.2014.6962108.","ama":"Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108","apa":"Anwer, J., & Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 177–184). IEEE. https://doi.org/10.1109/DFT.2014.6962108","bibtex":"@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}, DOI={10.1109/DFT.2014.6962108}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2014}, pages={177–184} }","mla":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84, doi:10.1109/DFT.2014.6962108.","short":"J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.","ieee":"J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 177–184."},"page":"177-184","language":[{"iso":"eng"}]},{"user_id":"3118","title":"Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection","extern":"1","status":"public","date_created":"2019-07-10T12:10:16Z","author":[{"last_name":"Ghasemzadeh Mohammadi","id":"61186","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"full_name":"Yazdani, Majid","first_name":"Majid","last_name":"Yazdani"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","doi":"10.1109/NANOARCH.2014.6880479","date_updated":"2022-01-06T06:50:50Z","_id":"10773","language":[{"iso":"eng"}],"year":"2014","type":"conference","citation":{"bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014, title={Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}, DOI={10.1109/NANOARCH.2014.6880479}, booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli, G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani, and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 163–68. IEEE, 2014. https://doi.org/10.1109/NANOARCH.2014.6880479.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2014, pp. 163–168.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168."},"page":"163-168"},{"doi":"10.1109/CIG.2014.6932863","date_updated":"2022-01-06T06:51:29Z","_id":"13154","language":[{"iso":"eng"}],"year":"2014","type":"conference","citation":{"ieee":"T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go,” in 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.","short":"T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.","mla":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863.","bibtex":"@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}, DOI={10.1109/CIG.2014.6932863}, booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2014}, pages={1–8} }","ama":"Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863","apa":"Graf, T., & Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In 2014 IEEE Conference on Computational Intelligence and Games (pp. 1–8). https://doi.org/10.1109/CIG.2014.6932863","chicago":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” In 2014 IEEE Conference on Computational Intelligence and Games, 1–8, 2014. https://doi.org/10.1109/CIG.2014.6932863."},"page":"1-8","user_id":"40778","title":"Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go","status":"public","date_created":"2019-09-09T09:09:31Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"author":[{"first_name":"Tobias","full_name":"Graf, Tobias","last_name":"Graf"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"2014 IEEE Conference on Computational Intelligence and Games"},{"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}],"date_updated":"2023-09-26T13:32:49Z","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"editor":[{"last_name":"Künsemöller","first_name":"Jörn","full_name":"Künsemöller, Jörn"},{"first_name":"Norber Otto","full_name":"Eke, Norber Otto","last_name":"Eke"},{"last_name":"Foit","first_name":"Lioba","full_name":"Foit, Lioba"},{"first_name":"Timo","full_name":"Kaerlein, Timo","last_name":"Kaerlein"}],"place":"Paderborn","title":"Verschiebungen an der Grenze zwischen Hardware und Software","page":"123-144","citation":{"ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","apa":"Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144."},"year":"2014","type":"book_chapter","_id":"335","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-20T07:29:58Z","content_type":"application/pdf","file_id":"1424","creator":"florida","file_size":2848154,"access_level":"closed","date_created":"2018-03-20T07:29:58Z","file_name":"335-2014_plessl_automatismen.pdf"}],"file_date_updated":"2018-03-20T07:29:58Z","publication":"Logiken strukturbildender Prozesse: Automatismen","publisher":"Wilhelm Fink","quality_controlled":"1","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"date_created":"2017-10-17T12:41:57Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf."}],"user_id":"15278","ddc":["040"]},{"series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","citation":{"chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13."},"type":"conference","year":"2014","page":"144-155","_id":"388","intvolume":" 8405","file":[{"access_level":"closed","date_created":"2018-03-20T07:02:02Z","file_name":"388-plessl14_arc.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:02:02Z","creator":"florida","file_id":"1387","file_size":330193}],"quality_controlled":"1","publisher":"Springer International Publishing","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"file_date_updated":"2018-03-20T07:02:02Z","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:07Z","volume":8405,"abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"user_id":"15278","ddc":["040"]},{"type":"journal_article","year":"2014","citation":{"short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }"},"page":"911-919","intvolume":" 38","_id":"363","issue":"8, Part B","publisher":"Elsevier","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Microprocessors and Microsystems","file_date_updated":"2018-03-20T07:20:31Z","file":[{"creator":"florida","file_id":"1408","file_size":1499996,"relation":"main_file","success":1,"date_updated":"2018-03-20T07:20:31Z","content_type":"application/pdf","date_created":"2018-03-20T07:20:31Z","file_name":"363-plessl13_micpro.pdf","access_level":"closed"}],"volume":38,"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:02Z","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:33:06Z","doi":"10.1016/j.micpro.2013.12.001","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators"},{"date_updated":"2023-09-26T13:33:50Z","doi":"10.1109/FCCM.2014.67","language":[{"iso":"eng"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"_id":"377","page":"222-229","type":"conference","citation":{"short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67."},"year":"2014","abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"ddc":["040"],"user_id":"15278","publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","keyword":["coldboot"],"file_date_updated":"2018-03-20T07:14:20Z","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"}],"publisher":"IEEE","quality_controlled":"1","file":[{"content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","success":1,"relation":"main_file","file_size":1003907,"creator":"florida","file_id":"1397","access_level":"closed","file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z"}],"date_created":"2017-10-17T12:42:05Z","status":"public","has_accepted_license":"1"},{"date_updated":"2023-09-26T13:33:31Z","doi":"10.1145/2617596","language":[{"iso":"eng"}],"title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"intvolume":" 7","_id":"365","article_number":"13","issue":"2","year":"2014","type":"journal_article","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596."},"abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-20T07:19:19Z","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","quality_controlled":"1","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"ACM","file":[{"access_level":"closed","date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","date_updated":"2018-03-20T07:19:19Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":916052,"file_id":"1406","creator":"florida"}],"volume":7,"date_created":"2017-10-17T12:42:03Z","has_accepted_license":"1","status":"public"},{"doi":"10.1109/MM.2013.110","date_updated":"2023-09-26T13:32:31Z","language":[{"iso":"eng"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"issue":"1","_id":"328","intvolume":" 34","year":"2014","type":"journal_article","citation":{"ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110"},"page":"60-71","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:55Z","volume":34,"file":[{"file_size":1877185,"creator":"florida","file_id":"1426","date_updated":"2018-03-20T07:31:40Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z","access_level":"closed"}],"quality_controlled":"1","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"IEEE","file_date_updated":"2018-03-20T07:31:40Z","publication":"IEEE Micro"},{"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","user_id":"15278","status":"public","date_created":"2018-03-26T13:40:14Z","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","author":[{"first_name":"Gianluca","full_name":"C. Durelli, Gianluca","last_name":"C. Durelli"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"D. Santambrogio","first_name":"Marco","full_name":"D. Santambrogio, Marco"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"publisher":"IEEE","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ISPA.2014.27","date_updated":"2023-09-26T13:35:40Z","_id":"1778","year":"2014","citation":{"ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27."},"type":"conference","page":"142-149","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","page":"1-8","type":"conference","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509"},"year":"2014","_id":"439","file":[{"content_type":"application/pdf","date_updated":"2018-03-16T11:29:52Z","success":1,"relation":"main_file","file_size":557362,"file_id":"1353","creator":"florida","access_level":"closed","file_name":"439-plessl14a_reconfig.pdf","date_created":"2018-03-16T11:29:52Z"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:29:52Z","publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2017-10-17T12:42:17Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"user_id":"15278","ddc":["040"]},{"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032535","date_updated":"2023-09-26T13:36:40Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","year":"2014","citation":{"mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"type":"conference","page":"1-8","_id":"406","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:11Z","file":[{"access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","success":1,"relation":"main_file","date_updated":"2018-03-16T11:37:42Z","content_type":"application/pdf","creator":"florida","file_id":"1366","file_size":932852}],"quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"IEEE","file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","user_id":"15278","ddc":["040"],"abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}]},{"project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_created":"2018-03-26T13:45:35Z","status":"public","publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Copolla","first_name":"Marcello","full_name":"Copolla, Marcello"},{"full_name":"Djafarian, Karim","first_name":"Karim","last_name":"Djafarian"},{"last_name":"Koranaros","first_name":"George","full_name":"Koranaros, George"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"last_name":"Paolino","first_name":"Michele","full_name":"Paolino, Michele"},{"last_name":"Pell","full_name":"Pell, Oliver","first_name":"Oliver"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","publisher":"Springer","user_id":"15278","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","language":[{"iso":"eng"}],"year":"2014","type":"conference","citation":{"short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38."},"doi":"10.1007/978-3-319-05960-0_38","_id":"1780","date_updated":"2023-09-26T13:36:20Z"},{"user_id":"15278","volume":41,"status":"public","date_created":"2018-03-26T13:42:34Z","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"}],"quality_controlled":"1","publisher":"ACM","keyword":["funding-maxup","tet_topic_hpc"],"publication":"ACM SIGARCH Computer Architecture News","issue":"5","_id":"1779","intvolume":" 41","citation":{"chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.","apa":"Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372."},"type":"journal_article","year":"2014","page":"65-70","title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","publication_identifier":{"issn":["0163-5964"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"doi":"10.1145/2641361.2641372","date_updated":"2023-09-26T13:35:58Z","language":[{"iso":"eng"}]},{"author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-11T11:51:51Z","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3530-8"]},"place":"Berlin","abstract":[{"text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.","lang":"eng"}],"user_id":"3118","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","language":[{"iso":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"year":"2013","citation":{"bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }","mla":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag Berlin GmbH, 2013.","chicago":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","ama":"Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH.","ieee":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013."},"type":"dissertation","page":"249","date_updated":"2022-01-06T06:51:04Z","_id":"11619"},{"doi":"10.1109/SIU.2013.6531530","_id":"1786","date_updated":"2022-01-06T06:53:20Z","citation":{"short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530."},"year":"2013","type":"conference","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","user_id":"24135","date_created":"2018-03-26T14:48:53Z","status":"public","publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","department":[{"_id":"27"},{"_id":"78"}],"author":[{"last_name":"Kasap","first_name":"Server","full_name":"Kasap, Server"},{"last_name":"Redif","full_name":"Redif, Soydan","first_name":"Soydan"}],"publisher":"IEEE"},{"doi":"10.1109/TVLSI.2013.2248069","issue":"3","_id":"1792","date_updated":"2022-01-06T06:53:23Z","intvolume":" 22","citation":{"short":"S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","ieee":"S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013.","ama":"Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069","apa":"Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3), 522–536. https://doi.org/10.1109/TVLSI.2013.2248069","chicago":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22, no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.","bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }"},"type":"journal_article","year":"2013","page":"522-536","title":"Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices","user_id":"24135","volume":22,"status":"public","date_created":"2018-03-26T15:15:03Z","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"publisher":"IEEE","department":[{"_id":"27"},{"_id":"78"}],"publication":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"status":"public","date_created":"2017-10-17T12:42:30Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"}],"publisher":"Logos Verlag Berlin GmbH","user_id":"477","abstract":[{"text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. ","lang":"eng"}],"citation":{"chicago":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.","ama":"Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Happe, M. (2013). Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","mla":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Logos Verlag Berlin GmbH, 2013.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","ieee":"M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH, 2013."},"type":"dissertation","year":"2013","page":"220","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"_id":"501","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3425-7"]},"project":[{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"78"}],"title":"Performance and thermal management on self-adaptive hybrid multi-cores","related_material":{"link":[{"relation":"confirmation","url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id="}]},"place":"Berlin","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:01:34Z"},{"language":[{"iso":"eng"}],"year":"2013","type":"journal_article","citation":{"ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” International Journal of Real-time Image Processing, vol. 8, no. 1, pp. 95–110, 2013.","short":"M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image Processing 8 (2013) 95–110.","mla":"Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” International Journal of Real-Time Image Processing, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:doi:10.1007/s11554-011-0212-y.","bibtex":"@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8}, DOI={doi:10.1007/s11554-011-0212-y}, number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110} }","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” International Journal of Real-Time Image Processing 8, no. 1 (2013): 95–110. https://doi.org/doi:10.1007/s11554-011-0212-y.","ama":"Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. International Journal of Real-time Image Processing. 2013;8(1):95-110. doi:doi:10.1007/s11554-011-0212-y","apa":"Happe, M., Lübbers, E., & Platzner, M. (2013). A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. 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Paderborn University; 2013."},"_id":"10743","date_updated":"2022-01-06T06:50:50Z"},{"date_created":"2019-07-10T12:01:51Z","status":"public","department":[{"_id":"78"}],"publication":"Real-Time Conference","author":[{"first_name":"Christian","full_name":"Toebermann, Christian","last_name":"Toebermann"},{"last_name":"Geibel","first_name":"Daniel","full_name":"Geibel, Daniel"},{"full_name":"Hau, Manuel","first_name":"Manuel","last_name":"Hau"},{"first_name":"Ron","full_name":"Brandl, Ron","last_name":"Brandl"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Chenjie","full_name":"Ma, Chenjie","last_name":"Ma"},{"last_name":"Braun","full_name":"Braun, Martin","first_name":"Martin"},{"last_name":"Degner","first_name":"Tobias","full_name":"Degner, Tobias"}],"publisher":"OPAL RT Paris","user_id":"3118","title":"Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation","citation":{"mla":"Toebermann, Christian, et al. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” Real-Time Conference, OPAL RT Paris, 2013.","bibtex":"@inproceedings{Toebermann_Geibel_Hau_Brandl_Kaufmann_Ma_Braun_Degner_2013, title={Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation}, booktitle={Real-Time Conference}, publisher={OPAL RT Paris}, author={Toebermann, Christian and Geibel, Daniel and Hau, Manuel and Brandl, Ron and Kaufmann, Paul and Ma, Chenjie and Braun, Martin and Degner, Tobias}, year={2013} }","chicago":"Toebermann, Christian, Daniel Geibel, Manuel Hau, Ron Brandl, Paul Kaufmann, Chenjie Ma, Martin Braun, and Tobias Degner. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” In Real-Time Conference. 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IEEE, 2013. https://doi.org/10.1109/DFT.2013.6653587."},"year":"2013","type":"conference","page":"83-88","user_id":"3118","title":"A fast TCAD-based methodology for Variation analysis of emerging nano-devices","extern":"1","status":"public","date_created":"2019-07-10T12:10:17Z","author":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"last_name":"Yazdani","full_name":"Yazdani, Majid","first_name":"Majid"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"publisher":"IEEE","publication":"2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","department":[{"_id":"78"}]},{"page":"1-6","type":"conference","year":"2013","citation":{"mla":"Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.","bibtex":"@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}, DOI={10.1109/LATW.2013.6562673}, booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013}, pages={1–6} }","apa":"Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013). Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6). IEEE. https://doi.org/10.1109/LATW.2013.6562673","ama":"Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673","chicago":"Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW, 1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.","ieee":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.","short":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6."},"language":[{"iso":"eng"}],"doi":"10.1109/LATW.2013.6562673","_id":"10775","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:10:18Z","status":"public","publication":"2013 14th Latin American Test Workshop-LATW","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel","last_name":"Gaillardon"},{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"title":"Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study","user_id":"3118","extern":"1"},{"_id":"13645","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"type":"conference","year":"2013","citation":{"ama":"Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proceedings of the International Conference on Computers and Games (CG). Springer; 2013.","apa":"Graf, T., Schäfers, L., & Platzner, M. (2013). On Semeai Detection in Monte-Carlo Go. In Proceedings of the International Conference on Computers and Games (CG). Springer.","chicago":"Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proceedings of the International Conference on Computers and Games (CG). Springer, 2013.","bibtex":"@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers, Lars and Platzner, Marco}, year={2013} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.","short":"T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.","ieee":"T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go.,” in Proceedings of the International Conference on Computers and Games (CG), 2013."},"user_id":"398","title":"On Semeai Detection in Monte-Carlo Go.","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"first_name":"Lars","full_name":"Schäfers, Lars","last_name":"Schäfers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","publication":"Proceedings of the International Conference on Computers and Games (CG)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T22:50:51Z"},{"type":"conference","year":"2013","citation":{"chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394."},"page":"386-389","_id":"528","file":[{"date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","access_level":"closed","file_size":822680,"creator":"florida","file_id":"1294","date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"publisher":"IEEE","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","keyword":["coldboot"],"file_date_updated":"2018-03-15T10:36:08Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:35Z","abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:38:20Z","doi":"10.1109/ISORC.2013.6913232","department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","year":"2013","type":"conference","citation":{"mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"_id":"505","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Kling","full_name":"Kling, Peter","first_name":"Peter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2018-03-15T13:38:56Z","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file":[{"file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z","access_level":"closed","creator":"florida","file_id":"1308","file_size":1040834,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:30Z","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"ddc":["040"],"user_id":"15278"},{"page":"64-73","year":"2013","citation":{"ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:38:05Z","_id":"1787","doi":"10.1109/IPDPSW.2013.136","publication":"Proc. Int. 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Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","chicago":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","apa":"Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn.","ama":"Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.","ieee":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012."},"type":"dissertation","year":"2012","main_file_link":[{"url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423","open_access":"1"}],"user_id":"477","ddc":["040"],"abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit.","lang":"ger"}],"date_created":"2017-10-17T12:42:46Z","has_accepted_license":"1","status":"public","file":[{"file_size":1438436,"file_id":"1261","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T08:38:19Z","relation":"main_file","success":1,"date_created":"2018-03-15T08:38:19Z","file_name":"586-Drzevitzky-PhD_01.pdf","access_level":"closed"}],"file_date_updated":"2018-03-15T08:38:19Z","author":[{"last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie","first_name":"Stephanie"}],"publisher":"Universität Paderborn"},{"language":[{"iso":"eng"}],"citation":{"chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","mla":"Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming models for reconfigurable heterogeneous multi-cores. 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Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University.","chicago":"Dridger, Denis. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012.","bibtex":"@book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }","mla":"Dridger, Denis. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012."},"type":"mastersthesis","language":[{"iso":"eng"}],"_id":"10650","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:10:59Z","publisher":"Paderborn University","author":[{"last_name":"Dridger","full_name":"Dridger, Denis","first_name":"Denis"}],"department":[{"_id":"78"}],"title":"Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer","user_id":"3118"},{"date_updated":"2022-01-06T06:50:49Z","_id":"10652","year":"2012","type":"dissertation","citation":{"ieee":"H. Giefers, Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.","short":"H. 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Berlin: Logos Verlag Berlin GmbH, 2012."},"page":"159","supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}],"place":"Berlin","abstract":[{"lang":"eng","text":"The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores."}],"title":"Design and Programming of Reconfigurable Mesh based Many-Cores","user_id":"3118","publisher":"Logos Verlag Berlin GmbH","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"}],"department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3165-2"]},"status":"public","date_created":"2019-07-10T11:13:12Z"},{"status":"public","date_created":"2019-07-10T11:13:34Z","author":[{"first_name":"Tobias","full_name":"Graf, Tobias","last_name":"Graf"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"title":"Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go","user_id":"3118","type":"mastersthesis","year":"2012","citation":{"bibtex":"@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }","mla":"Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012.","chicago":"Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012.","ama":"Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012.","apa":"Graf, T. (2012). Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go. Paderborn University.","ieee":"T. Graf, Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go. Paderborn University, 2012.","short":"T. Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go, Paderborn University, 2012."},"supervisor":[{"last_name":"Schäfers","first_name":"Lars","full_name":"Schäfers, Lars"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10658"},{"user_id":"3118","title":"Generating Adjustable Temperature Gradients on modern FPGAs","publisher":"Paderborn University","author":[{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:15:12Z","_id":"10667","date_updated":"2022-01-06T06:50:49Z","supervisor":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","citation":{"short":"H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Paderborn University, 2012.","ieee":"H. Hangmann, Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University, 2012.","chicago":"Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012.","ama":"Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012.","apa":"Hangmann, H. (2012). Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University.","bibtex":"@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }","mla":"Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012."},"year":"2012"},{"title":"Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture","user_id":"3118","publication":"International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)","department":[{"_id":"78"}],"publisher":"IGI Global","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"}],"volume":3,"date_created":"2019-07-10T11:28:10Z","status":"public","_id":"10685","date_updated":"2022-01-06T06:50:49Z","intvolume":" 3","doi":"10.4018/jaras.2012100102","issue":"4","page":"17-31","citation":{"ieee":"P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012.","short":"P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31.","bibtex":"@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}, volume={3}, DOI={10.4018/jaras.2012100102}, number={4}, journal={International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }","mla":"Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:10.4018/jaras.2012100102.","chicago":"Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3, no. 4 (2012): 17–31. https://doi.org/10.4018/jaras.2012100102.","ama":"Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102","apa":"Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2012). Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), 3(4), 17–31. https://doi.org/10.4018/jaras.2012100102"},"type":"journal_article","year":"2012","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"type":"misc","citation":{"short":"M. Platzner, A. Boschmann, P. Kaufmann, Wieder Natürlich Gehen Und Greifen, 2012.","ieee":"M. Platzner, A. Boschmann, and P. Kaufmann, Wieder natürlich gehen und greifen. 2012, pp. 6–11.","chicago":"Platzner, Marco, Alexander Boschmann, and Paul Kaufmann. Wieder Natürlich Gehen Und Greifen, 2012.","apa":"Platzner, M., Boschmann, A., & Kaufmann, P. (2012). Wieder natürlich gehen und greifen (pp. 6–11).","ama":"Platzner M, Boschmann A, Kaufmann P. Wieder Natürlich Gehen Und Greifen.; 2012:6-11.","bibtex":"@book{Platzner_Boschmann_Kaufmann_2012, title={Wieder natürlich gehen und greifen}, author={Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}, year={2012}, pages={6–11} }","mla":"Platzner, Marco, et al. Wieder Natürlich Gehen Und Greifen. 2012, pp. 6–11."},"year":"2012","page":"6-11","_id":"10723","date_updated":"2022-01-06T06:50:50Z","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:54:15Z","user_id":"398","title":"Wieder natürlich gehen und greifen"},{"language":[{"iso":"eng"}],"citation":{"chicago":"Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.","ama":"Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012.","apa":"Schmitz, H. (2012). Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University.","bibtex":"@book{Schmitz_2012, title={Stereo Matching on a HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Schmitz, Henning}, year={2012} }","mla":"Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.","short":"H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer, Paderborn University, 2012.","ieee":"H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012."},"type":"bachelorsthesis","year":"2012","_id":"10734","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:58:08Z","user_id":"3118","title":"Stereo Matching on a HC-1 Hybrid Core Computer"},{"date_updated":"2022-01-06T06:50:50Z","_id":"10747","type":"bachelorsthesis","year":"2012","citation":{"chicago":"Topmöller, Christoph. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University, 2012.","apa":"Topmöller, C. (2012). Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System. Paderborn University.","ama":"Topmöller C. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University; 2012.","mla":"Topmöller, Christoph. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University, 2012.","bibtex":"@book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }","short":"C. Topmöller, Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System, Paderborn University, 2012.","ieee":"C. Topmöller, Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System. Paderborn University, 2012."},"language":[{"iso":"eng"}],"title":"Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System","user_id":"3118","status":"public","date_created":"2019-07-10T12:01:53Z","publisher":"Paderborn University","author":[{"last_name":"Topmöller","full_name":"Topmöller, Christoph","first_name":"Christoph"}],"department":[{"_id":"78"}]},{"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2012","citation":{"chicago":"Wistuba, Martin. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012.","apa":"Wistuba, M. (2012). Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University.","ama":"Wistuba M. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University; 2012.","bibtex":"@book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }","mla":"Wistuba, Martin. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012.","short":"M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go, Paderborn University, 2012.","ieee":"M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012."},"_id":"10754","date_updated":"2022-01-06T06:50:50Z","status":"public","date_created":"2019-07-10T12:05:19Z","author":[{"last_name":"Wistuba","full_name":"Wistuba, Martin","first_name":"Martin"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"user_id":"3118","title":"Analysis of Pattern Based Model Design and Learning in Computer-Go"},{"date_updated":"2022-01-06T06:51:36Z","_id":"13462","year":"2012","type":"misc","citation":{"ieee":"P. Lewis, M. Platzner, and X. Yao, An outlook for self-awareness in computing systems. Awareness Magazine, 2012.","short":"P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012.","mla":"Lewis, Peter, et al. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine, 2012.","bibtex":"@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }","apa":"Lewis, P., Platzner, M., & Yao, X. (2012). An outlook for self-awareness in computing systems. Awareness Magazine.","ama":"Lewis P, Platzner M, Yao X. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine; 2012.","chicago":"Lewis, Peter, Marco Platzner, and Xin Yao. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine, 2012."},"language":[{"iso":"eng"}],"title":"An outlook for self-awareness in computing systems","user_id":"398","author":[{"full_name":"Lewis, Peter","first_name":"Peter","last_name":"Lewis"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"publisher":"Awareness Magazine","department":[{"_id":"78"}],"status":"public","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"date_created":"2019-09-30T09:24:09Z"},{"type":"conference","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370."},"year":"2012","page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"has_accepted_license":"1","status":"public","date_created":"2018-03-29T15:04:25Z","file":[{"file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_created":"2019-02-13T09:04:46Z","access_level":"closed","file_id":"7638","creator":"fossie","file_size":2148787,"success":1,"relation":"main_file","date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf"}],"publisher":"IEEE","author":[{"full_name":"Meyer, Björn","first_name":"Björn","last_name":"Meyer"},{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"}],"quality_controlled":"1","file_date_updated":"2019-02-13T09:04:46Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"user_id":"15278","ddc":["000"],"abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","page":"110-126","citation":{"ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002."},"type":"journal_article","year":"2012","issue":"2","intvolume":" 36","_id":"2108","date_created":"2018-03-29T15:12:38Z","status":"public","volume":36,"keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"quality_controlled":"1","user_id":"15278"},{"page":"1-8","citation":{"mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"year":"2012","type":"conference","_id":"615","date_created":"2017-10-17T12:42:51Z","has_accepted_license":"1","status":"public","file":[{"access_level":"closed","file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z","content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","relation":"main_file","success":1,"file_size":730144,"creator":"florida","file_id":"1246"}],"file_date_updated":"2018-03-15T06:48:32Z","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators"},{"citation":{"mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"year":"2012","type":"conference","page":"1-8","_id":"591","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:47Z","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","file_size":371235,"creator":"florida","file_id":"1257","access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort."}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?"},{"citation":{"short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }"},"year":"2012","type":"conference","page":"8-9","_id":"609","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:50Z","quality_controlled":"1","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file_date_updated":"2018-03-15T08:14:17Z","file":[{"date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_size":146789,"creator":"florida","file_id":"1249","content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z","success":1,"relation":"main_file"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes"},{"year":"2012","citation":{"bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565."},"type":"conference","page":"559-565","_id":"567","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:42Z","file":[{"date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","access_level":"closed","file_size":288508,"file_id":"1275","creator":"florida","date_updated":"2018-03-15T10:20:24Z","content_type":"application/pdf","relation":"main_file","success":1}],"author":[{"full_name":"Barrio, Pablo","first_name":"Pablo","last_name":"Barrio"},{"first_name":"Carlos","full_name":"Carreras, Carlos","last_name":"Carreras"},{"last_name":"Sierra","first_name":"Roberto","full_name":"Sierra, Roberto"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2018-03-15T10:20:24Z","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","user_id":"15278","ddc":["040"],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures"},{"_id":"612","type":"conference","citation":{"ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370."},"year":"2012","page":"559-562","user_id":"15278","ddc":["040"],"abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:51Z","file":[{"file_size":202923,"creator":"florida","file_id":"1247","date_updated":"2018-03-15T06:49:03Z","content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-15T06:49:03Z","file_name":"612-ruething_fpl12.pdf","access_level":"closed"}],"quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:42:03Z","language":[{"iso":"eng"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012."},"year":"2012","_id":"2180","date_updated":"2023-09-26T13:40:17Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","keyword":["funding-enhance"],"quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"date_created":"2018-04-03T09:18:33Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","user_id":"15278","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Int. Journal of Reconfigurable Computing (IJRC)","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"Hindawi Publishing Corp.","quality_controlled":"1","date_created":"2018-04-03T09:13:22Z","status":"public","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","user_id":"15278","type":"journal_article","citation":{"bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315.","apa":"Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)."},"year":"2012","language":[{"iso":"eng"}],"_id":"2177","date_updated":"2023-09-26T13:39:48Z","doi":"10.1155/2012/418315"},{"author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"keyword":["funding-intel"],"publication":"Intel European Research and Innovation Conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-03T14:34:57Z","user_id":"24135","title":"Estimation and Partitioning for CPU-Accelerator Architectures","type":"conference","year":"2011","citation":{"short":"T. Kenter, C. Plessl, M. Platzner, M. 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When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. 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A. Walker, J. F. Miller, P. Kaufmann, and M. Platzner, “Problem Decomposition in Cartesian Genetic Programming,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","short":"J.A. Walker, J.F. Miller, P. Kaufmann, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","mla":"Walker, James Alfred, et al. “Problem Decomposition in Cartesian Genetic Programming.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","bibtex":"@inbook{Walker_Miller_Kaufmann_Platzner_2011, series={Natural Computing Series}, title={Problem Decomposition in Cartesian Genetic Programming}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}, year={2011}, pages={35–99}, collection={Natural Computing Series} }","ama":"Walker JA, Miller JF, Kaufmann P, Platzner M. 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Welp, User Space Scheduling for Heterogeneous Systems, Paderborn University, 2011.","bibtex":"@book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems}, publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }","mla":"Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.","chicago":"Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.","ama":"Welp D. User Space Scheduling for Heterogeneous Systems. Paderborn University; 2011.","apa":"Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University."},"year":"2011","language":[{"iso":"eng"}],"title":"User Space Scheduling for Heterogeneous Systems","user_id":"3118","department":[{"_id":"78"}],"author":[{"last_name":"Welp","full_name":"Welp, Daniel","first_name":"Daniel"}],"publisher":"Paderborn University","date_created":"2019-07-10T12:03:00Z","status":"public"},{"doi":"10.1109/fpl.2011.42","_id":"13643","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"page":"185-188","citation":{"short":"A. Agne, M. Platzner, E. Lübbers, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–188.","ieee":"A. Agne, M. Platzner, and E. Lübbers, “Memory Virtualization for Multithreaded Reconfigurable Hardware,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2011, pp. 185–188.","apa":"Agne, A., Platzner, M., & Lübbers, E. (2011). Memory Virtualization for Multithreaded Reconfigurable Hardware. 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Henkel, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, L. Bauer, J. Teich, N. Wehn, H.-J. Wunderlich, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, in: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011.","ieee":"J. Henkel et al., “Design and architectures for dependable embedded systems,” in Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11, 2011."},"type":"conference","language":[{"iso":"eng"}],"_id":"13644","date_updated":"2022-01-06T06:51:40Z","doi":"10.1145/2039370.2039384","author":[{"full_name":"Henkel, Jörg","first_name":"Jörg","last_name":"Henkel"},{"last_name":"Hedrich","first_name":"Lars","full_name":"Hedrich, Lars"},{"first_name":"Andreas","full_name":"Herkersdorf, Andreas","last_name":"Herkersdorf"},{"first_name":"Rüdiger","full_name":"Kapitza, Rüdiger","last_name":"Kapitza"},{"last_name":"Lohmann","full_name":"Lohmann, Daniel","first_name":"Daniel"},{"last_name":"Marwedel","full_name":"Marwedel, Peter","first_name":"Peter"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Rosenstiel","full_name":"Rosenstiel, Wolfgang","first_name":"Wolfgang"},{"first_name":"Ulf","full_name":"Schlichtmann, Ulf","last_name":"Schlichtmann"},{"last_name":"Spinczyk","full_name":"Spinczyk, Olaf","first_name":"Olaf"},{"last_name":"Tahoori","full_name":"Tahoori, Mehdi","first_name":"Mehdi"},{"full_name":"Bauer, Lars","first_name":"Lars","last_name":"Bauer"},{"last_name":"Teich","first_name":"Jürgen","full_name":"Teich, Jürgen"},{"last_name":"Wehn","full_name":"Wehn, Norbert","first_name":"Norbert"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"},{"last_name":"Becker","first_name":"Joachim","full_name":"Becker, Joachim"},{"last_name":"Bringmann","first_name":"Oliver","full_name":"Bringmann, Oliver"},{"full_name":"Brinkschulte, Uwe","first_name":"Uwe","last_name":"Brinkschulte"},{"last_name":"Chakraborty","first_name":"Samarjit","full_name":"Chakraborty, Samarjit"},{"last_name":"Engel","full_name":"Engel, Michael","first_name":"Michael"},{"first_name":"Rolf","full_name":"Ernst, Rolf","last_name":"Ernst"},{"full_name":"Härtig, Hermann","first_name":"Hermann","last_name":"Härtig"}],"publication":"Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["9781450307154"]},"status":"public","date_created":"2019-10-04T22:44:36Z","title":"Design and architectures for dependable embedded systems","user_id":"398"},{"title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","user_id":"15278","status":"public","date_created":"2018-04-03T14:55:57Z","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","first_name":"Jens","id":"158","last_name":"Förstner"}],"keyword":["tet_topic_hpc"],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"doi":"10.1109/SAAHPC.2011.12","date_updated":"2023-09-26T13:44:11Z","_id":"2194","type":"conference","citation":{"ieee":"B. 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Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12","apa":"Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12"},"year":"2011","page":"60-63","language":[{"iso":"eng"}]},{"date_created":"2018-04-03T14:37:14Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"status":"public","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"publisher":"IEEE Computer Society","user_id":"15278","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","language":[{"iso":"eng"}],"page":"223-226","year":"2011","citation":{"ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273"},"type":"conference","doi":"10.1109/ASAP.2011.6043273","date_updated":"2023-09-26T13:43:48Z","_id":"2193"},{"_id":"656","year":"2011","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59"},"type":"conference","page":"55-60","user_id":"15278","ddc":["040"],"abstract":[{"text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:59Z","file":[{"access_level":"closed","date_created":"2018-03-14T13:49:39Z","file_name":"656-2011_happe_reconfig.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-14T13:49:39Z","creator":"florida","file_id":"1220","file_size":502244}],"author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"IEEE","quality_controlled":"1","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-14T13:49:39Z","doi":"10.1109/ReConFig.2011.59","date_updated":"2023-09-26T13:46:08Z","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"quality_controlled":"1","publisher":"ACM","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"date_created":"2018-04-03T15:08:13Z","status":"public","place":"New York, NY, USA","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","user_id":"15278","page":"177-180","year":"2011","type":"conference","citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. 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