[{"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/MM.2013.110","date_updated":"2023-09-26T13:32:31Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications","lang":"eng"}],"volume":34,"date_created":"2017-10-17T12:41:55Z","status":"public","has_accepted_license":"1","publication":"IEEE Micro","file_date_updated":"2018-03-20T07:31:40Z","publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file":[{"access_level":"closed","file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z","content_type":"application/pdf","date_updated":"2018-03-20T07:31:40Z","success":1,"relation":"main_file","file_size":1877185,"creator":"florida","file_id":"1426"}],"issue":"1","_id":"328","intvolume":" 34","page":"60-71","year":"2014","citation":{"mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71."},"type":"journal_article"},{"_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","language":[{"iso":"eng"}],"page":"142-149","citation":{"ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27."},"year":"2014","type":"conference","user_id":"15278","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"first_name":"Marcello","full_name":"Pogliani, Marcello","last_name":"Pogliani"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"publisher":"IEEE","date_created":"2018-03-26T13:40:14Z","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"status":"public"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","page":"1-8","year":"2014","type":"conference","citation":{"short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509."},"_id":"439","file":[{"date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed","file_size":557362,"file_id":"1353","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-16T11:29:52Z","success":1,"relation":"main_file"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:29:52Z","publisher":"IEEE","author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:17Z","status":"public","has_accepted_license":"1","abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"user_id":"15278","ddc":["040"]},{"user_id":"15278","ddc":["040"],"abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"date_created":"2017-10-17T12:42:11Z","status":"public","has_accepted_license":"1","file":[{"access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","relation":"main_file","success":1,"date_updated":"2018-03-16T11:37:42Z","content_type":"application/pdf","file_id":"1366","creator":"florida","file_size":932852}],"file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","_id":"406","page":"1-8","year":"2014","type":"conference","citation":{"ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535"},"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2014.7032535","date_updated":"2023-09-26T13:36:40Z","language":[{"iso":"eng"}]},{"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"Springer","quality_controlled":"1","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"first_name":"Marcello","full_name":"Copolla, Marcello","last_name":"Copolla"},{"last_name":"Djafarian","first_name":"Karim","full_name":"Djafarian, Karim"},{"first_name":"George","full_name":"Koranaros, George","last_name":"Koranaros"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"last_name":"Paolino","first_name":"Michele","full_name":"Paolino, Michele"},{"first_name":"Oliver","full_name":"Pell, Oliver","last_name":"Pell"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"D. Santambrogio","first_name":"Marco","full_name":"D. Santambrogio, Marco"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"date_created":"2018-03-26T13:45:35Z","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"status":"public","user_id":"15278","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","language":[{"iso":"eng"}],"citation":{"ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38."},"type":"conference","year":"2014","date_updated":"2023-09-26T13:36:20Z","_id":"1780","doi":"10.1007/978-3-319-05960-0_38"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"publication_identifier":{"issn":["0163-5964"]},"title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:35:58Z","doi":"10.1145/2641361.2641372","publisher":"ACM","quality_controlled":"1","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158"}],"publication":"ACM SIGARCH Computer Architecture News","keyword":["funding-maxup","tet_topic_hpc"],"status":"public","date_created":"2018-03-26T13:42:34Z","volume":41,"user_id":"15278","type":"journal_article","year":"2014","citation":{"apa":"Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372."},"page":"65-70","_id":"1779","intvolume":" 41","issue":"5"},{"_id":"11619","date_updated":"2022-01-06T06:51:04Z","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"citation":{"ama":"Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH.","chicago":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }","mla":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag Berlin GmbH, 2013.","short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.","ieee":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013."},"type":"dissertation","year":"2013","page":"249","place":"Berlin","abstract":[{"lang":"eng","text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches."}],"user_id":"3118","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-11T11:51:51Z","publication_identifier":{"isbn":["978-3-8325-3530-8"]},"publication_status":"published"},{"_id":"1786","date_updated":"2022-01-06T06:53:20Z","doi":"10.1109/SIU.2013.6531530","type":"conference","citation":{"mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.","short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013."},"year":"2013","user_id":"24135","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","department":[{"_id":"27"},{"_id":"78"}],"author":[{"last_name":"Kasap","first_name":"Server","full_name":"Kasap, Server"},{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"}],"publisher":"IEEE","date_created":"2018-03-26T14:48:53Z","status":"public"},{"_id":"1792","intvolume":" 22","date_updated":"2022-01-06T06:53:23Z","doi":"10.1109/TVLSI.2013.2248069","issue":"3","page":"522-536","type":"journal_article","citation":{"ieee":"S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013.","short":"S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.","ama":"Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069","apa":"Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3), 522–536. https://doi.org/10.1109/TVLSI.2013.2248069","chicago":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22, no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069."},"year":"2013","title":"Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices","user_id":"24135","department":[{"_id":"27"},{"_id":"78"}],"publication":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems","publisher":"IEEE","author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"}],"volume":22,"date_created":"2018-03-26T15:15:03Z","status":"public"},{"user_id":"477","abstract":[{"lang":"eng","text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. "}],"date_created":"2017-10-17T12:42:30Z","status":"public","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"}],"publisher":"Logos Verlag Berlin GmbH","_id":"501","supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"page":"220","year":"2013","type":"dissertation","citation":{"mla":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","apa":"Happe, M. (2013). Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH.","ama":"Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.","chicago":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.","ieee":"M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013."},"related_material":{"link":[{"relation":"confirmation","url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id="}]},"title":"Performance and thermal management on self-adaptive hybrid multi-cores","place":"Berlin","project":[{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"publication_identifier":{"isbn":["978-3-8325-3425-7"]},"publication_status":"published","department":[{"_id":"78"}],"date_updated":"2022-01-06T07:01:34Z","language":[{"iso":"eng"}]},{"title":"A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking","user_id":"398","volume":8,"status":"public","date_created":"2019-07-10T09:22:45Z","publisher":"Springer","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"International Journal of Real-time Image Processing","department":[{"_id":"78"}],"doi":"doi:10.1007/s11554-011-0212-y","issue":"1","_id":"10604","date_updated":"2022-01-06T06:50:47Z","intvolume":" 8","type":"journal_article","year":"2013","citation":{"short":"M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image Processing 8 (2013) 95–110.","ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” International Journal of Real-time Image Processing, vol. 8, no. 1, pp. 95–110, 2013.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” International Journal of Real-Time Image Processing 8, no. 1 (2013): 95–110. https://doi.org/doi:10.1007/s11554-011-0212-y.","apa":"Happe, M., Lübbers, E., & Platzner, M. (2013). A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. International Journal of Real-Time Image Processing, 8(1), 95–110. https://doi.org/doi:10.1007/s11554-011-0212-y","ama":"Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. International Journal of Real-time Image Processing. 2013;8(1):95-110. doi:doi:10.1007/s11554-011-0212-y","mla":"Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” International Journal of Real-Time Image Processing, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:doi:10.1007/s11554-011-0212-y.","bibtex":"@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8}, DOI={doi:10.1007/s11554-011-0212-y}, number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110} }"},"page":"95 - 110","language":[{"iso":"eng"}]},{"title":"Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime","user_id":"3118","date_created":"2019-07-10T09:32:57Z","status":"public","department":[{"_id":"78"}],"keyword":["fault tolerant computing","field programmable gate arrays","logic design","reliability","BYU-LANL tool","DRM tool flow","FPGA based hardware designs","avionic application","device technologies","dynamic reliability management","fault-tolerant operation","hardware designs","reconfiguring reliability levels","space applications","Field programmable gate arrays","Hardware","Redundancy","Reliability engineering","Runtime","Tunneling magnetoresistance"],"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"doi":"10.1109/ReConFig.2013.6732280","date_updated":"2022-01-06T06:50:48Z","_id":"10620","page":"1-6","citation":{"chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 1–6, 2013. https://doi.org/10.1109/ReConFig.2013.6732280.","ama":"Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280","apa":"Anwer, J., Meisner, S., & Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6). https://doi.org/10.1109/ReConFig.2013.6732280","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.","bibtex":"@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={10.1109/ReConFig.2013.6732280}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }","short":"J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6."},"type":"conference","year":"2013","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"short":"C. Bick, Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner, Paderborn University, 2013.","ieee":"C. Bick, Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner. Paderborn University, 2013.","apa":"Bick, C. (2013). Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner. Paderborn University.","ama":"Bick C. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University; 2013.","chicago":"Bick, Christian. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University, 2013.","bibtex":"@book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick, Christian}, year={2013} }","mla":"Bick, Christian. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University, 2013."},"year":"2013","type":"bachelorsthesis","_id":"10626","date_updated":"2022-01-06T06:50:48Z","status":"public","date_created":"2019-07-10T09:40:24Z","author":[{"first_name":"Christian","full_name":"Bick, Christian","last_name":"Bick"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"user_id":"3118","title":"Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner"},{"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"first_name":"Barbara","full_name":"Nofen, Barbara","last_name":"Nofen"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:03:00Z","user_id":"3118","title":"Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes","language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"A. Boschmann, B. Nofen, and M. Platzner, “Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.","short":"A. Boschmann, B. Nofen, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.","bibtex":"@inproceedings{Boschmann_Nofen_Platzner_2013, title={Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Nofen, Barbara and Platzner, Marco}, year={2013} }","mla":"Boschmann, Alexander, et al. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.","apa":"Boschmann, A., Nofen, B., & Platzner, M. (2013). Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC).","ama":"Boschmann A, Nofen B, Platzner M. Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2013.","chicago":"Boschmann, Alexander, Barbara Nofen, and Marco Platzner. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013."},"year":"2013","_id":"10634","date_updated":"2022-01-06T06:50:49Z"},{"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:03:01Z","title":"Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array","user_id":"3118","citation":{"short":"A. Boschmann, M. Platzner, in: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.","ieee":"A. Boschmann and M. Platzner, “Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array,” in Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.","apa":"Boschmann, A., & Platzner, M. (2013). Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array. In Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC).","ama":"Boschmann A, Platzner M. Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array. In: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC). ; 2013.","chicago":"Boschmann, Alexander, and Marco Platzner. “Reducing the Limb Position Effect in Pattern Recognition Based Myoelectric Control Using a High Density Electrode Array.” In Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.","mla":"Boschmann, Alexander, and Marco Platzner. “Reducing the Limb Position Effect in Pattern Recognition Based Myoelectric Control Using a High Density Electrode Array.” Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.","bibtex":"@inproceedings{Boschmann_Platzner_2013, title={Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array}, booktitle={Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2013} }"},"year":"2013","type":"conference","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10635"},{"title":"Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface","user_id":"3118","author":[{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"full_name":"Assad, Christopher","first_name":"Christopher","last_name":"Assad"},{"last_name":"Wolf","full_name":"Wolf, Michael","first_name":"Michael"}],"publisher":"Springer","department":[{"_id":"78"}],"publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","volume":1,"status":"public","date_created":"2019-07-10T11:13:16Z","intvolume":" 1","_id":"10655","date_updated":"2022-01-06T06:50:49Z","series_title":"LNCS","citation":{"mla":"Glette, Kyrre, et al. “Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 1, Springer, 2013, pp. 1–1.","bibtex":"@inproceedings{Glette_Kaufmann_Assad_Wolf_2013, series={LNCS}, title={Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface}, volume={1}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Kaufmann, Paul and Assad, Christopher and Wolf, Michael}, year={2013}, pages={1–1}, collection={LNCS} }","ama":"Glette K, Kaufmann P, Assad C, Wolf M. Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 1. LNCS. Springer; 2013:1-1.","apa":"Glette, K., Kaufmann, P., Assad, C., & Wolf, M. (2013). Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 1, pp. 1–1). Springer.","chicago":"Glette, Kyrre, Paul Kaufmann, Christopher Assad, and Michael Wolf. “Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 1:1–1. LNCS. Springer, 2013.","ieee":"K. Glette, P. Kaufmann, C. Assad, and M. Wolf, “Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2013, vol. 1, pp. 1–1.","short":"K. Glette, P. Kaufmann, C. Assad, M. Wolf, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2013, pp. 1–1."},"year":"2013","type":"conference","page":"1-1"},{"publisher":"Logos Verlag","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:27:24Z","place":"Berlin","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","user_id":"3118","year":"2013","citation":{"short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag, Berlin, 2013.","ieee":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag, 2013.","chicago":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag, 2013.","ama":"Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag; 2013.","apa":"Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag}, author={Kaufmann, Paul}, year={2013} }","mla":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag, 2013."},"type":"book","language":[{"iso":"eng"}],"_id":"10681","date_updated":"2022-01-06T06:50:49Z"},{"page":"46-63","type":"journal_article","citation":{"chicago":"Kaufmann, Paul, Kyrre Glette, Tiemo Gruber, Marco Platzner, Jim Torresen, and Bernhard Sick. “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers.” IEEE Transactions on Evolutionary Computation 17, no. 1 (2013): 46–63. https://doi.org/10.1109/TEVC.2012.2185845.","ama":"Kaufmann P, Glette K, Gruber T, Platzner M, Torresen J, Sick B. Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers. IEEE Transactions on Evolutionary Computation. 2013;17(1):46-63. doi:10.1109/TEVC.2012.2185845","apa":"Kaufmann, P., Glette, K., Gruber, T., Platzner, M., Torresen, J., & Sick, B. (2013). Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers. IEEE Transactions on Evolutionary Computation, 17(1), 46–63. https://doi.org/10.1109/TEVC.2012.2185845","bibtex":"@article{Kaufmann_Glette_Gruber_Platzner_Torresen_Sick_2013, title={Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers}, volume={17}, DOI={10.1109/TEVC.2012.2185845}, number={1}, journal={IEEE Transactions on Evolutionary Computation}, author={Kaufmann, Paul and Glette, Kyrre and Gruber, Tiemo and Platzner, Marco and Torresen, Jim and Sick, Bernhard}, year={2013}, pages={46–63} }","mla":"Kaufmann, Paul, et al. “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers.” IEEE Transactions on Evolutionary Computation, vol. 17, no. 1, 2013, pp. 46–63, doi:10.1109/TEVC.2012.2185845.","short":"P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, B. Sick, IEEE Transactions on Evolutionary Computation 17 (2013) 46–63.","ieee":"P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. 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Platzner, “On Semeai Detection in Monte-Carlo Go.,” in Proceedings of the International Conference on Computers and Games (CG), 2013.","apa":"Graf, T., Schäfers, L., & Platzner, M. (2013). On Semeai Detection in Monte-Carlo Go. In Proceedings of the International Conference on Computers and Games (CG). Springer.","ama":"Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proceedings of the International Conference on Computers and Games (CG). Springer; 2013.","chicago":"Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proceedings of the International Conference on Computers and Games (CG). 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Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"ddc":["040"],"user_id":"15278","type":"conference","citation":{"ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394"},"year":"2013","page":"386-389","_id":"528"},{"type":"conference","citation":{"mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"year":"2013","_id":"505","file":[{"date_created":"2018-03-15T13:38:56Z","file_name":"505-Plessl13_seus.pdf","access_level":"closed","file_size":1040834,"creator":"florida","file_id":"1308","content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","relation":"main_file","success":1}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","publisher":"IEEE","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:30Z","status":"public","has_accepted_license":"1","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:38:20Z","doi":"10.1109/ISORC.2013.6913232","department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services"},{"language":[{"iso":"eng"}],"page":"64-73","year":"2013","type":"conference","citation":{"mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73."},"doi":"10.1109/IPDPSW.2013.136","_id":"1787","date_updated":"2023-09-26T13:38:05Z","date_created":"2018-03-26T14:51:05Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publication":"Proc. Int. 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Conf. on Field Programmable Technology (ICFPT)","department":[{"_id":"27"},{"_id":"78"}],"status":"public","date_created":"2018-03-29T14:34:48Z","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","year":"2012","type":"conference","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140."},"page":"135-140","_id":"2097","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/FPT.2012.6412125"},{"_id":"2100","date_updated":"2022-01-06T06:54:42Z","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012."},"type":"conference","year":"2012","title":"FPGA implementation of a second-order convolutive blind signal separation algorithm","user_id":"24135","status":"public","date_created":"2018-03-29T14:43:18Z","author":[{"last_name":"Kasap","first_name":"Server","full_name":"Kasap, Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","department":[{"_id":"27"},{"_id":"78"}]},{"doi":"10.1109/CIG.2012.6374143","date_updated":"2022-01-06T06:54:42Z","_id":"2103","type":"conference","year":"2012","citation":{"ieee":"M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.","short":"M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.","mla":"Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.","bibtex":"@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }","chicago":"Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.","ama":"Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143","apa":"Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143"},"page":"91-99","title":"Comparison of Bayesian Move Prediction Systems for Computer Go","user_id":"24135","status":"public","date_created":"2018-03-29T14:59:35Z","publisher":"IEEE","author":[{"full_name":"Wistuba, Martin","first_name":"Martin","last_name":"Wistuba"},{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proc. IEEE Conf. on Computational Intelligence and Games (CIG)","department":[{"_id":"27"},{"_id":"78"}]},{"issue":"4","doi":"10.1088/0031-9155/57/4/867","_id":"2172","intvolume":" 57","date_updated":"2022-01-06T06:55:12Z","type":"journal_article","citation":{"ieee":"K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.","short":"K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883.","mla":"Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.","bibtex":"@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }","chicago":"Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel, Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no. 4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.","apa":"Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867","ama":"Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867"},"year":"2012","page":"867-883","user_id":"24135","title":"STIR: Software for Tomographic Image Reconstruction Release 2","status":"public","date_created":"2018-04-03T09:02:27Z","volume":57,"publisher":"IOP Publishing","author":[{"first_name":"Kris","full_name":"Thielemans, Kris","last_name":"Thielemans"},{"full_name":"Tsoumpas, Charalampos","first_name":"Charalampos","last_name":"Tsoumpas"},{"first_name":"Sanida","full_name":"Mustafovic, Sanida","last_name":"Mustafovic"},{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"first_name":"Pablo","full_name":"Aguiar, Pablo","last_name":"Aguiar"},{"first_name":"Nikolaos","full_name":"Dikaios, Nikolaos","last_name":"Dikaios"},{"last_name":"W Jacobson","full_name":"W Jacobson, Matthew","first_name":"Matthew"}],"publication":"Physics in Medicine and Biology","department":[{"_id":"27"},{"_id":"78"}]},{"publisher":"Taylor & Francis","author":[{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"},{"last_name":"Kasap","first_name":"Server","full_name":"Kasap, Server"}],"publication":"Int. Journal of Electronics","department":[{"_id":"27"},{"_id":"78"}],"volume":100,"status":"public","date_created":"2018-04-03T09:05:36Z","title":"Parallel algorithm for computation of second-order sequential best rotations","user_id":"24135","year":"2012","citation":{"chicago":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.","apa":"Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343","ama":"Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343","mla":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343.","bibtex":"@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }","short":"S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651.","ieee":"S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012."},"type":"journal_article","page":"1646-1651","intvolume":" 100","_id":"2173","date_updated":"2022-01-06T06:55:12Z","doi":"10.1080/00207217.2012.751343","issue":"12"},{"user_id":"24135","title":"Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer","status":"public","date_created":"2018-04-03T09:08:00Z","volume":7,"publisher":"Academy Publishers","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"last_name":"Benkrid","first_name":"Khaled","full_name":"Benkrid, Khaled"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Journal of Computers","issue":"6","_id":"2174","intvolume":" 7","date_updated":"2022-01-06T06:55:12Z","year":"2012","type":"journal_article","citation":{"short":"S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328.","ieee":"S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012.","ama":"Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.","apa":"Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328.","chicago":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.","mla":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.","bibtex":"@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }"},"page":"1312-1328"},{"file_date_updated":"2018-03-15T08:38:19Z","publisher":"Universität Paderborn","author":[{"first_name":"Stephanie","full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky"}],"file":[{"file_size":1438436,"file_id":"1261","creator":"florida","date_updated":"2018-03-15T08:38:19Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"586-Drzevitzky-PhD_01.pdf","date_created":"2018-03-15T08:38:19Z","access_level":"closed"}],"date_created":"2017-10-17T12:42:46Z","has_accepted_license":"1","status":"public","abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit.","lang":"ger"}],"ddc":["040"],"user_id":"477","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423"}],"page":"114","year":"2012","type":"dissertation","citation":{"bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","mla":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","ama":"Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.","apa":"Drzevitzky, S. (2012). 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In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.","lang":"eng"}],"publication_identifier":{"isbn":["978-3-8325-3165-2"]},"publication_status":"published","status":"public","date_created":"2019-07-10T11:13:12Z","publisher":"Logos Verlag Berlin GmbH","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"}],"department":[{"_id":"78"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10652","citation":{"bibtex":"@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }","mla":"Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Logos Verlag Berlin GmbH, 2012.","chicago":"Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.","ama":"Giefers H. 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Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go, Paderborn University, 2012.","bibtex":"@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }","mla":"Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012.","apa":"Graf, T. (2012). Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go. Paderborn University.","ama":"Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012.","chicago":"Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012."},"year":"2012","type":"mastersthesis"},{"date_created":"2019-07-10T11:15:12Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Hangmann","first_name":"Hendrik","full_name":"Hangmann, Hendrik"}],"publisher":"Paderborn University","title":"Generating Adjustable Temperature Gradients on modern FPGAs","user_id":"3118","year":"2012","citation":{"mla":"Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012.","bibtex":"@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }","ama":"Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012.","apa":"Hangmann, H. (2012). Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University.","chicago":"Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012.","ieee":"H. Hangmann, Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University, 2012.","short":"H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Paderborn University, 2012."},"type":"bachelorsthesis","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10667"},{"language":[{"iso":"eng"}],"page":"17-31","year":"2012","citation":{"chicago":"Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3, no. 4 (2012): 17–31. https://doi.org/10.4018/jaras.2012100102.","apa":"Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2012). 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Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31.","ieee":"P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012."},"type":"journal_article","date_updated":"2022-01-06T06:50:49Z","_id":"10685","intvolume":" 3","issue":"4","doi":"10.4018/jaras.2012100102","department":[{"_id":"78"}],"publication":"International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)","publisher":"IGI Global","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"}],"date_created":"2019-07-10T11:28:10Z","status":"public","volume":3,"user_id":"3118","title":"Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture"},{"language":[{"iso":"eng"}],"page":"6-11","citation":{"ama":"Platzner M, Boschmann A, Kaufmann P. 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Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.","apa":"Schmitz, H. (2012). Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University.","ama":"Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012.","chicago":"Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.","ieee":"H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.","short":"H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer, Paderborn University, 2012."},"year":"2012","type":"bachelorsthesis","_id":"10734","date_updated":"2022-01-06T06:50:50Z"},{"_id":"10747","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"C. Topmöller, Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System, Paderborn University, 2012.","ieee":"C. Topmöller, Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System. 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Paderborn University."},"type":"mastersthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10754"},{"author":[{"last_name":"Lewis","first_name":"Peter","full_name":"Lewis, Peter"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Xin","full_name":"Yao, Xin","last_name":"Yao"}],"publisher":"Awareness Magazine","department":[{"_id":"78"}],"status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2019-09-30T09:24:09Z","title":"An outlook for self-awareness in computing systems","user_id":"398","citation":{"ieee":"P. Lewis, M. Platzner, and X. Yao, An outlook for self-awareness in computing systems. Awareness Magazine, 2012.","short":"P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012.","mla":"Lewis, Peter, et al. An Outlook for Self-Awareness in Computing Systems. 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Awareness Magazine, 2012."},"year":"2012","type":"misc","language":[{"iso":"eng"}],"_id":"13462","date_updated":"2022-01-06T06:51:36Z"},{"date_created":"2018-03-29T15:04:25Z","status":"public","has_accepted_license":"1","file":[{"relation":"main_file","success":1,"date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","file_id":"7638","creator":"fossie","file_size":2148787,"access_level":"closed","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_created":"2019-02-13T09:04:46Z"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"158","last_name":"Förstner","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","first_name":"Jens"}],"user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"page":"189-196","type":"conference","year":"2012","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }"},"conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"_id":"2106","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z"},{"publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","date_created":"2018-03-29T15:12:38Z","status":"public","volume":36,"publication":"Microprocessors and Microsystems","keyword":["funding-altera"],"author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"quality_controlled":"1","user_id":"15278","page":"110-126","citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002."},"year":"2012","type":"journal_article","issue":"2","_id":"2108","intvolume":" 36"},{"user_id":"15278","ddc":["040"],"abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"date_created":"2017-10-17T12:42:51Z","has_accepted_license":"1","status":"public","file":[{"access_level":"closed","date_created":"2018-03-15T06:48:32Z","file_name":"615-ReConFig12_01.pdf","date_updated":"2018-03-15T06:48:32Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":730144,"file_id":"1246","creator":"florida"}],"file_date_updated":"2018-03-15T06:48:32Z","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"_id":"615","page":"1-8","year":"2012","type":"conference","citation":{"short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745."},"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","page":"1-8","citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773"},"type":"conference","year":"2012","_id":"591","file_date_updated":"2018-03-15T08:33:18Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"}],"publisher":"IEEE","file":[{"access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z","date_updated":"2018-03-15T08:33:18Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":371235,"creator":"florida","file_id":"1257"}],"date_created":"2017-10-17T12:42:47Z","has_accepted_license":"1","status":"public","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"ddc":["040"],"user_id":"15278"},{"title":"Hardware/Software Platform for Self-aware Compute Nodes","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"date_updated":"2023-09-26T13:41:36Z","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"ddc":["040"],"user_id":"15278","quality_controlled":"1","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-15T08:14:17Z","content_type":"application/pdf","file_id":"1249","creator":"florida","file_size":146789,"access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_created":"2018-03-15T08:14:17Z"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:50Z","_id":"609","citation":{"mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9."},"type":"conference","year":"2012","page":"8-9"},{"abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"ddc":["040"],"user_id":"15278","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"full_name":"Carreras, Carlos","first_name":"Carlos","last_name":"Carreras"},{"first_name":"Roberto","full_name":"Sierra, Roberto","last_name":"Sierra"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"IEEE","quality_controlled":"1","file":[{"file_size":288508,"creator":"florida","file_id":"1275","content_type":"application/pdf","date_updated":"2018-03-15T10:20:24Z","success":1,"relation":"main_file","file_name":"567-ba-ca-12a.pdf","date_created":"2018-03-15T10:20:24Z","access_level":"closed"}],"date_created":"2017-10-17T12:42:42Z","status":"public","has_accepted_license":"1","_id":"567","page":"559-565","type":"conference","citation":{"ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973."},"year":"2012","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","language":[{"iso":"eng"}]},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","quality_controlled":"1","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","file_date_updated":"2018-03-15T06:49:03Z","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file":[{"file_size":202923,"file_id":"1247","creator":"florida","date_updated":"2018-03-15T06:49:03Z","content_type":"application/pdf","relation":"main_file","success":1,"file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","access_level":"closed"}],"_id":"612","year":"2012","type":"conference","citation":{"short":"C. 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Berlin / Heidelberg: Springer, 2011. https://doi.org/10.1007/978-3-642-23397-5_36."},"_id":"2204","date_updated":"2022-01-06T06:55:23Z","intvolume":" 6853","doi":"10.1007/978-3-642-23397-5_36"},{"title":"Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach","project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"doi":"10.1109/ReCoSoC.2011.5981499","date_updated":"2022-01-06T07:03:14Z","language":[{"iso":"eng"}],"user_id":"477","ddc":["040"],"abstract":[{"lang":"eng","text":"Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. 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Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.","bibtex":"@inproceedings{Giefers_Platzner_2010, title={A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier}, booktitle={Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }","mla":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.","chicago":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2010.","apa":"Giefers, H., & Platzner, M. (2010). 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IEEE; 2010."}},{"type":"conference","year":"2010","citation":{"bibtex":"@inproceedings{Schäfer_Birattari_Blömer_Dorigo_Engels_O’Grady_Platzner_Rammig_Reif_Trächtler_2010, title={Engineering Self-Coordinating Software Intensive Systems}, booktitle={Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)}, author={Schäfer, Wilhelm and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O’Grady, Rehan and Platzner, Marco and Rammig, Franz-Josef and Reif, Wolfgang and Trächtler, Ansgar}, year={2010}, pages={321–324} }","mla":"Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–24.","chicago":"Schäfer, Wilhelm, Mauro Birattari, Johannes Blömer, Marco Dorigo, Gregor Engels, Rehan O’Grady, Marco Platzner, Franz-Josef Rammig, Wolfgang Reif, and Ansgar Trächtler. “Engineering Self-Coordinating Software Intensive Systems.” In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 321–24, 2010.","apa":"Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R., … Trächtler, A. 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