[{"page":"35-99","year":"2011","type":"book_chapter","citation":{"short":"J.A. Walker, J.F. Miller, P. Kaufmann, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","ieee":"J. A. Walker, J. F. Miller, P. Kaufmann, and M. Platzner, “Problem Decomposition in Cartesian Genetic Programming,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","chicago":"Walker, James Alfred, Julian F. Miller, Paul Kaufmann, and Marco Platzner. “Problem Decomposition in Cartesian Genetic Programming.” In Cartesian Genetic Programming, 35–99. Natural Computing Series. Springer Berlin Heidelberg, 2011.","apa":"Walker, J. A., Miller, J. F., Kaufmann, P., & Platzner, M. (2011). Problem Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming (pp. 35–99). Springer Berlin Heidelberg.","ama":"Walker JA, Miller JF, Kaufmann P, Platzner M. Problem Decomposition in Cartesian Genetic Programming. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:35-99.","mla":"Walker, James Alfred, et al. “Problem Decomposition in Cartesian Genetic Programming.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.","bibtex":"@inbook{Walker_Miller_Kaufmann_Platzner_2011, series={Natural Computing Series}, title={Problem Decomposition in Cartesian Genetic Programming}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}, year={2011}, pages={35–99}, collection={Natural Computing Series} }"},"language":[{"iso":"eng"}],"series_title":"Natural Computing Series","_id":"10748","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:02:57Z","status":"public","publication":"Cartesian Genetic Programming","department":[{"_id":"78"}],"author":[{"full_name":"Walker, James Alfred","first_name":"James Alfred","last_name":"Walker"},{"last_name":"Miller","first_name":"Julian F.","full_name":"Miller, Julian F."},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer Berlin Heidelberg","title":"Problem Decomposition in Cartesian Genetic Programming","user_id":"3118"},{"date_updated":"2022-01-06T06:50:50Z","_id":"10750","language":[{"iso":"eng"}],"citation":{"ieee":"D. Welp, User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.","short":"D. Welp, User Space Scheduling for Heterogeneous Systems, Paderborn University, 2011.","bibtex":"@book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems}, publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }","mla":"Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.","ama":"Welp D. User Space Scheduling for Heterogeneous Systems. Paderborn University; 2011.","apa":"Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University.","chicago":"Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011."},"type":"mastersthesis","year":"2011","user_id":"3118","title":"User Space Scheduling for Heterogeneous Systems","status":"public","date_created":"2019-07-10T12:03:00Z","publisher":"Paderborn University","author":[{"last_name":"Welp","first_name":"Daniel","full_name":"Welp, Daniel"}],"department":[{"_id":"78"}]},{"title":"Memory Virtualization for Multithreaded Reconfigurable Hardware","user_id":"398","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"}],"publisher":"IEEE","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"publication_identifier":{"isbn":["9781457714849"]},"publication_status":"published","status":"public","date_created":"2019-10-04T22:42:51Z","date_updated":"2022-01-06T06:51:40Z","_id":"13643","doi":"10.1109/fpl.2011.42","citation":{"chicago":"Agne, Andreas, Marco Platzner, and Enno Lübbers. “Memory Virtualization for Multithreaded Reconfigurable Hardware.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 185–88. IEEE, 2011. https://doi.org/10.1109/fpl.2011.42.","apa":"Agne, A., Platzner, M., & Lübbers, E. (2011). Memory Virtualization for Multithreaded Reconfigurable Hardware. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (pp. 185–188). IEEE. https://doi.org/10.1109/fpl.2011.42","ama":"Agne A, Platzner M, Lübbers E. Memory Virtualization for Multithreaded Reconfigurable Hardware. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2011:185-188. doi:10.1109/fpl.2011.42","bibtex":"@inproceedings{Agne_Platzner_Lübbers_2011, title={Memory Virtualization for Multithreaded Reconfigurable Hardware}, DOI={10.1109/fpl.2011.42}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Agne, Andreas and Platzner, Marco and Lübbers, Enno}, year={2011}, pages={185–188} }","mla":"Agne, Andreas, et al. “Memory Virtualization for Multithreaded Reconfigurable Hardware.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–88, doi:10.1109/fpl.2011.42.","short":"A. Agne, M. Platzner, E. Lübbers, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–188.","ieee":"A. Agne, M. Platzner, and E. Lübbers, “Memory Virtualization for Multithreaded Reconfigurable Hardware,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2011, pp. 185–188."},"type":"conference","year":"2011","page":"185-188","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"chicago":"Henkel, Jörg, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, et al. “Design and Architectures for Dependable Embedded Systems.” In Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011. https://doi.org/10.1145/2039370.2039384.","apa":"Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel, P., … Härtig, H. (2011). Design and architectures for dependable embedded systems. In Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11. https://doi.org/10.1145/2039370.2039384","ama":"Henkel J, Hedrich L, Herkersdorf A, et al. Design and architectures for dependable embedded systems. In: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11. ; 2011. doi:10.1145/2039370.2039384","mla":"Henkel, Jörg, et al. “Design and Architectures for Dependable Embedded Systems.” Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011, doi:10.1145/2039370.2039384.","bibtex":"@inproceedings{Henkel_Hedrich_Herkersdorf_Kapitza_Lohmann_Marwedel_Platzner_Rosenstiel_Schlichtmann_Spinczyk_et al._2011, title={Design and architectures for dependable embedded systems}, DOI={10.1145/2039370.2039384}, booktitle={Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11}, author={Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and et al.}, year={2011} }","short":"J. Henkel, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, L. Bauer, J. Teich, N. Wehn, H.-J. Wunderlich, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, in: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011.","ieee":"J. Henkel et al., “Design and architectures for dependable embedded systems,” in Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11, 2011."},"year":"2011","type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13644","doi":"10.1145/2039370.2039384","author":[{"last_name":"Henkel","first_name":"Jörg","full_name":"Henkel, Jörg"},{"last_name":"Hedrich","first_name":"Lars","full_name":"Hedrich, Lars"},{"full_name":"Herkersdorf, Andreas","first_name":"Andreas","last_name":"Herkersdorf"},{"last_name":"Kapitza","first_name":"Rüdiger","full_name":"Kapitza, Rüdiger"},{"full_name":"Lohmann, Daniel","first_name":"Daniel","last_name":"Lohmann"},{"last_name":"Marwedel","full_name":"Marwedel, Peter","first_name":"Peter"},{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Rosenstiel","full_name":"Rosenstiel, Wolfgang","first_name":"Wolfgang"},{"full_name":"Schlichtmann, Ulf","first_name":"Ulf","last_name":"Schlichtmann"},{"full_name":"Spinczyk, Olaf","first_name":"Olaf","last_name":"Spinczyk"},{"last_name":"Tahoori","full_name":"Tahoori, Mehdi","first_name":"Mehdi"},{"first_name":"Lars","full_name":"Bauer, Lars","last_name":"Bauer"},{"last_name":"Teich","full_name":"Teich, Jürgen","first_name":"Jürgen"},{"first_name":"Norbert","full_name":"Wehn, Norbert","last_name":"Wehn"},{"full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim","last_name":"Wunderlich"},{"first_name":"Joachim","full_name":"Becker, Joachim","last_name":"Becker"},{"first_name":"Oliver","full_name":"Bringmann, Oliver","last_name":"Bringmann"},{"last_name":"Brinkschulte","first_name":"Uwe","full_name":"Brinkschulte, Uwe"},{"last_name":"Chakraborty","full_name":"Chakraborty, Samarjit","first_name":"Samarjit"},{"last_name":"Engel","first_name":"Michael","full_name":"Engel, Michael"},{"last_name":"Ernst","first_name":"Rolf","full_name":"Ernst, Rolf"},{"last_name":"Härtig","first_name":"Hermann","full_name":"Härtig, Hermann"}],"department":[{"_id":"78"}],"publication":"Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11","status":"public","date_created":"2019-10-04T22:44:36Z","publication_status":"published","publication_identifier":{"isbn":["9781450307154"]},"user_id":"398","title":"Design and architectures for dependable embedded systems"},{"project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"date_created":"2018-04-03T14:55:57Z","status":"public","keyword":["tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Förstner","id":"158","first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862"}],"quality_controlled":"1","publisher":"IEEE Computer Society","user_id":"15278","title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","language":[{"iso":"eng"}],"page":"60-63","type":"conference","citation":{"short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.","ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.","apa":"Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12."},"year":"2011","doi":"10.1109/SAAHPC.2011.12","_id":"2194","date_updated":"2023-09-26T13:44:11Z"},{"language":[{"iso":"eng"}],"citation":{"chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273."},"year":"2011","type":"conference","page":"223-226","doi":"10.1109/ASAP.2011.6043273","_id":"2193","date_updated":"2023-09-26T13:43:48Z","status":"public","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"date_created":"2018-04-03T14:37:14Z","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"quality_controlled":"1","publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","user_id":"15278","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler"},{"_id":"656","year":"2011","citation":{"mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60."},"type":"conference","page":"55-60","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:59Z","file":[{"access_level":"closed","date_created":"2018-03-14T13:49:39Z","file_name":"656-2011_happe_reconfig.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-14T13:49:39Z","creator":"florida","file_id":"1220","file_size":502244}],"publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"file_date_updated":"2018-03-14T13:49:39Z","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2011.59","date_updated":"2023-09-26T13:46:08Z","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"doi":"10.1145/1950413.1950448","date_updated":"2023-09-26T13:45:04Z","_id":"2200","language":[{"iso":"eng"}],"page":"177-180","type":"conference","year":"2011","citation":{"ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448"},"user_id":"15278","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","place":"New York, NY, USA","date_created":"2018-04-03T15:08:13Z","status":"public","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"quality_controlled":"1","publisher":"ACM"},{"user_id":"15278","title":"FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Hindawi Publishing Corp.","quality_controlled":"1","publication":"Int. Journal of Recon- figurable Computing (IJRC)","keyword":["funding-altera"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-03T15:09:49Z","_id":"2201","date_updated":"2023-09-26T13:45:46Z","doi":"10.1155/2011/760954","language":[{"iso":"eng"}],"year":"2011","citation":{"short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC), 2011, doi: 10.1155/2011/760954.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), 2011. https://doi.org/10.1155/2011/760954.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC). https://doi.org/10.1155/2011/760954","mla":"Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.","bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={10.1155/2011/760954}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }"},"type":"journal_article"},{"doi":"10.1109/IPDPS.2011.153","_id":"2198","date_updated":"2023-09-26T13:44:39Z","page":"278-285","type":"conference","year":"2011","citation":{"short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153."},"language":[{"iso":"eng"}],"title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","user_id":"15278","date_created":"2018-04-03T15:05:52Z","status":"public","publication":"Proc. Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}]},{"type":"journal_article","year":"2010","citation":{"short":"S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable Computing 2010 (2010).","ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” International Journal of Reconfigurable Computing, vol. 2010, 2010.","chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” International Journal of Reconfigurable Computing 2010 (2010). https://doi.org/10.1155/2010/180242.","apa":"Drzevitzky, S., Kastens, U., & Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing, 2010. https://doi.org/10.1155/2010/180242","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing. 2010;2010. doi:10.1155/2010/180242","bibtex":"@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={10.1155/2010/180242}, journal={International Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010} }","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” International Journal of Reconfigurable Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242."},"language":[{"iso":"eng"}],"doi":"10.1155/2010/180242","_id":"10605","intvolume":" 2010","date_updated":"2022-01-06T06:50:47Z","volume":2010,"date_created":"2019-07-10T09:22:56Z","status":"public","publication":"International Journal of Reconfigurable Computing","department":[{"_id":"78"}],"publisher":"Hindawi Publishing Corporation","author":[{"last_name":"Drzevitzky","first_name":"Stephanie","full_name":"Drzevitzky, Stephanie"},{"last_name":"Kastens","first_name":"Uwe","full_name":"Kastens, Uwe"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification","user_id":"3118"},{"title":"Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen","user_id":"3118","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:25:12Z","date_updated":"2022-01-06T06:50:47Z","_id":"10614","type":"mastersthesis","citation":{"short":"A. Agne, Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen, Paderborn University, 2010.","ieee":"A. Agne, Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010.","chicago":"Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010.","apa":"Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University.","ama":"Agne A. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University; 2010.","bibtex":"@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne, Andreas}, year={2010} }","mla":"Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010."},"year":"2010","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:50:48Z","_id":"10629","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2010","citation":{"short":"A. Boschmann, EMG-Basierte Ganganalyse, Paderborn University, 2010.","ieee":"A. Boschmann, EMG-basierte Ganganalyse. Paderborn University, 2010.","apa":"Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University.","ama":"Boschmann A. EMG-Basierte Ganganalyse. Paderborn University; 2010.","chicago":"Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010.","bibtex":"@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2010} }","mla":"Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010."},"user_id":"3118","title":"EMG-basierte Ganganalyse","date_created":"2019-07-10T09:40:27Z","status":"public","alternative_title":["EMG-based Gait Analysis"],"department":[{"_id":"78"}],"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"}],"publisher":"Paderborn University"},{"title":"Evolvable Cache Controller","user_id":"3118","status":"public","date_created":"2019-07-10T11:03:43Z","author":[{"full_name":"Breitlauch, Daniel","first_name":"Daniel","last_name":"Breitlauch"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"_id":"10642","date_updated":"2022-01-06T06:50:49Z","year":"2010","citation":{"short":"D. Breitlauch, Evolvable Cache Controller, Paderborn University, 2010.","ieee":"D. Breitlauch, Evolvable Cache Controller. Paderborn University, 2010.","apa":"Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University.","ama":"Breitlauch D. Evolvable Cache Controller. Paderborn University; 2010.","chicago":"Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010.","bibtex":"@book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2010} }","mla":"Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010."},"type":"mastersthesis","supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}]},{"date_created":"2019-07-10T11:10:58Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Dridger","full_name":"Dridger, Denis","first_name":"Denis"}],"user_id":"3118","title":"Soft Microprocessors with tightly coupled Application-Specific Coprocessors","language":[{"iso":"eng"}],"citation":{"mla":"Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010.","bibtex":"@book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010} }","chicago":"Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010.","apa":"Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University.","ama":"Dridger D. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University; 2010.","ieee":"D. Dridger, Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University, 2010.","short":"D. Dridger, Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors, Paderborn University, 2010."},"type":"bachelorsthesis","year":"2010","date_updated":"2022-01-06T06:50:49Z","_id":"10649"},{"_id":"10657","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"apa":"Graf, T. (2010). Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University.","ama":"Graf T. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University; 2010.","chicago":"Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010.","mla":"Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010.","bibtex":"@book{Graf_2010, title={Parallelization of the UCT Algorithm on HPC-Clusters}, publisher={Paderborn University}, author={Graf, Tobias}, year={2010} }","short":"T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters, Paderborn University, 2010.","ieee":"T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010."},"type":"bachelorsthesis","year":"2010","user_id":"3118","title":"Parallelization of the UCT Algorithm on HPC-Clusters","date_created":"2019-07-10T11:13:33Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"}]},{"language":[{"iso":"eng"}],"type":"conference","year":"2010","citation":{"apa":"Kaufmann, P., Englehart, K., & Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 6357–6360). IEEE.","ama":"Kaufmann P, Englehart K, Platzner M. Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE; 2010:6357-6360.","chicago":"Kaufmann, Paul, Kevin Englehart, and Marco Platzner. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 6357–60. IEEE, 2010.","mla":"Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–60.","bibtex":"@inproceedings{Kaufmann_Englehart_Platzner_2010, title={Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}, booktitle={International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}, publisher={IEEE}, author={Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}, year={2010}, pages={6357–6360} }","short":"P. Kaufmann, K. Englehart, M. Platzner, in: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–6360.","ieee":"P. Kaufmann, K. Englehart, and M. Platzner, “Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms,” in International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2010, pp. 6357–6360."},"page":"6357-6360","date_updated":"2022-01-06T06:50:49Z","_id":"10683","status":"public","date_created":"2019-07-10T11:27:27Z","publisher":"IEEE","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Englehart","full_name":"Englehart, Kevin","first_name":"Kevin"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)","department":[{"_id":"78"}],"user_id":"3118","title":"Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms"},{"language":[{"iso":"eng"}],"year":"2010","type":"conference","citation":{"bibtex":"@inproceedings{Kaufmann_Knieper_Platzner_2010, title={A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}, booktitle={IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}, publisher={IEEE}, author={Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}, year={2010}, pages={541–548} }","mla":"Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–48.","ama":"Kaufmann P, Knieper T, Platzner M. A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC). IEEE; 2010:541-548.","apa":"Kaufmann, P., Knieper, T., & Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) (pp. 541–548). IEEE.","chicago":"Kaufmann, Paul, Tobias Knieper, and Marco Platzner. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), 541–48. IEEE, 2010.","ieee":"P. Kaufmann, T. Knieper, and M. Platzner, “A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers,” in IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), 2010, pp. 541–548.","short":"P. Kaufmann, T. Knieper, M. Platzner, in: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–548."},"page":"541-548","_id":"10686","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:28:11Z","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Knieper, Tobias","first_name":"Tobias","last_name":"Knieper"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","publication":"IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)","department":[{"_id":"78"}],"user_id":"3118","title":"A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers"},{"issue":"3","doi":"10.1049/iet-cdt.2010.9044","_id":"10694","intvolume":" 4","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"page":"157-158","citation":{"bibtex":"@article{Kebschull_Platzner_Teich_2010, title={Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}, volume={4}, DOI={10.1049/iet-cdt.2010.9044}, number={3}, journal={IET Computers Digital Techniques}, author={Kebschull, Udo and Platzner, Marco and Teich, Jürgen}, year={2010}, pages={157–158} }","mla":"Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” IET Computers Digital Techniques, vol. 4, no. 3, 2010, pp. 157–58, doi:10.1049/iet-cdt.2010.9044.","chicago":"Kebschull, Udo, Marco Platzner, and Jürgen Teich. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” IET Computers Digital Techniques 4, no. 3 (2010): 157–58. https://doi.org/10.1049/iet-cdt.2010.9044.","apa":"Kebschull, U., Platzner, M., & Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques, 4(3), 157–158. https://doi.org/10.1049/iet-cdt.2010.9044","ama":"Kebschull U, Platzner M, Teich J. Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques. 2010;4(3):157-158. doi:10.1049/iet-cdt.2010.9044","ieee":"U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” IET Computers Digital Techniques, vol. 4, no. 3, pp. 157–158, 2010.","short":"U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques 4 (2010) 157–158."},"type":"journal_article","year":"2010","user_id":"3118","title":"Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)","date_created":"2019-07-10T11:30:01Z","status":"public","publication_identifier":{"issn":["1751-8601"]},"volume":4,"publication":"IET Computers Digital Techniques","department":[{"_id":"78"}],"author":[{"last_name":"Kebschull","first_name":"Udo","full_name":"Kebschull, Udo"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Jürgen","full_name":"Teich, Jürgen","last_name":"Teich"}]},{"title":"Hybridization of Global Multi-Objective and Local Search Techniques","user_id":"3118","department":[{"_id":"78"}],"author":[{"last_name":"Knieper","first_name":"Tobias","full_name":"Knieper, Tobias"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:30:23Z","status":"public","date_updated":"2022-01-06T06:50:49Z","_id":"10697","type":"mastersthesis","year":"2010","citation":{"bibtex":"@book{Knieper_2010, title={Hybridization of Global Multi-Objective and Local Search Techniques}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2010} }","mla":"Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.","apa":"Knieper, T. (2010). Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University.","ama":"Knieper T. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University; 2010.","chicago":"Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.","ieee":"T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.","short":"T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques, Paderborn University, 2010."},"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}]},{"series_title":"LNCS","page":"250-261","type":"conference","citation":{"chicago":"Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner, and Jim Torresen. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 6274:250–61. LNCS. Springer, 2010.","apa":"Knieper, T., Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2010). Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 6274, pp. 250–261). Springer.","ama":"Knieper T, Kaufmann P, Glette K, Platzner M, Torresen J. Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 6274. LNCS. Springer; 2010:250-261.","bibtex":"@inproceedings{Knieper_Kaufmann_Glette_Platzner_Torresen_2010, series={LNCS}, title={Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture}, volume={6274}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Knieper, Tobias and Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2010}, pages={250–261}, collection={LNCS} }","mla":"Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 6274, Springer, 2010, pp. 250–61.","short":"T. Knieper, P. Kaufmann, K. Glette, M. Platzner, J. Torresen, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2010, pp. 250–261.","ieee":"T. Knieper, P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2010, vol. 6274, pp. 250–261."},"year":"2010","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10699","intvolume":" 6274","publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"Knieper, Tobias","first_name":"Tobias","last_name":"Knieper"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"}],"volume":6274,"date_created":"2019-07-10T11:38:03Z","status":"public","title":"Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture","user_id":"3118"},{"author":[{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"Springer-Verlag GmbH","department":[{"_id":"78"}],"publication":"Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications","status":"public","date_created":"2019-07-10T11:41:18Z","editor":[{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Teich","first_name":"Jürgen","full_name":"Teich, Jürgen"},{"last_name":"Wehn","first_name":"Norbert","full_name":"Wehn, Norbert"}],"user_id":"3118","title":"ReconOS: An Operating System for Dynamically Reconfigurable Hardware","language":[{"iso":"eng"}],"type":"book_chapter","citation":{"short":"E. Lübbers, M. Platzner, in: M. Platzner, J. Teich, N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010, pp. 269–290.","ieee":"E. Lübbers and M. Platzner, “ReconOS: An Operating System for Dynamically Reconfigurable Hardware,” in Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, M. Platzner, J. Teich, and N. Wehn, Eds. Springer-Verlag GmbH, 2010, pp. 269–290.","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” In Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner, Jürgen Teich, and Norbert Wehn, 269–90. Springer-Verlag GmbH, 2010. https://doi.org/10.1007/978-90-481-3485-4_13.","ama":"Lübbers E, Platzner M. ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In: Platzner M, Teich J, Wehn N, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH; 2010:269-290. doi:10.1007/978-90-481-3485-4_13","apa":"Lübbers, E., & Platzner, M. (2010). ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In M. Platzner, J. Teich, & N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications (pp. 269–290). Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4_13","bibtex":"@inbook{Lübbers_Platzner_2010, title={ReconOS: An Operating System for Dynamically Reconfigurable Hardware}, DOI={10.1007/978-90-481-3485-4_13}, booktitle={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, publisher={Springer-Verlag GmbH}, author={Lübbers, Enno and Platzner, Marco}, editor={Platzner, Marco and Teich, Jürgen and Wehn, NorbertEditors}, year={2010}, pages={269–290} }","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner et al., Springer-Verlag GmbH, 2010, pp. 269–90, doi:10.1007/978-90-481-3485-4_13."},"year":"2010","page":"269-290","_id":"10704","date_updated":"2022-01-06T06:50:50Z","doi":"10.1007/978-90-481-3485-4_13"},{"user_id":"3118","title":"FPGA/CPU Multicore-Plattform für ReconOS/eCos","department":[{"_id":"78"}],"author":[{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:43:35Z","status":"public","date_updated":"2022-01-06T06:50:50Z","_id":"10710","language":[{"iso":"eng"}],"year":"2010","citation":{"short":"R. Meiche, FPGA/CPU Multicore-Plattform Für ReconOS/ECos, Paderborn University, 2010.","ieee":"R. Meiche, FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University, 2010.","apa":"Meiche, R. (2010). FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University.","ama":"Meiche R. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University; 2010.","chicago":"Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010.","bibtex":"@book{Meiche_2010, title={FPGA/CPU Multicore-Plattform für ReconOS/eCos}, publisher={Paderborn University}, author={Meiche, Robert}, year={2010} }","mla":"Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010."},"type":"mastersthesis"},{"year":"2010","citation":{"ieee":"M. Niekamp, Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University, 2010.","short":"M. Niekamp, Transparente Hardwarebeschleunigung Durch Shared Library Interposing, Paderborn University, 2010.","bibtex":"@book{Niekamp_2010, title={Transparente Hardwarebeschleunigung durch Shared Library Interposing}, publisher={Paderborn University}, author={Niekamp, Manuel}, year={2010} }","mla":"Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010.","apa":"Niekamp, M. (2010). Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University.","ama":"Niekamp M. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University; 2010.","chicago":"Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010."},"type":"mastersthesis","supervisor":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10717","date_created":"2019-07-10T11:48:28Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Niekamp","first_name":"Manuel","full_name":"Niekamp, Manuel"}],"publisher":"Paderborn University","title":"Transparente Hardwarebeschleunigung durch Shared Library Interposing","user_id":"3118"},{"type":"mastersthesis","citation":{"short":"B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS, Paderborn University, 2010.","ieee":"B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.","apa":"Runde, B. (2010). A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University.","ama":"Runde B. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University; 2010.","chicago":"Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.","bibtex":"@book{Runde_2010, title={A Token-Ring Network-On-Chip for Message Passing in ReconOS}, publisher={Paderborn University}, author={Runde, Bodo}, year={2010} }","mla":"Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010."},"year":"2010","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10731","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Runde","full_name":"Runde, Bodo","first_name":"Bodo"}],"date_created":"2019-07-10T11:54:50Z","status":"public","title":"A Token-Ring Network-On-Chip for Message Passing in ReconOS","user_id":"3118"},{"title":"Scheduling Support for Heterogeneous Hardware Accelerators under Linux","user_id":"3118","department":[{"_id":"78"}],"author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"publisher":"Paderborn University","date_created":"2019-07-10T12:03:02Z","status":"public","_id":"10752","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux, Paderborn University, 2010.","ieee":"T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.","apa":"Wiersema, T. (2010). Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University.","ama":"Wiersema T. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University; 2010.","chicago":"Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.","mla":"Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.","bibtex":"@book{Wiersema_2010, title={Scheduling Support for Heterogeneous Hardware Accelerators under Linux}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2010} }"},"year":"2010","type":"mastersthesis","supervisor":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"}],"language":[{"iso":"eng"}]},{"type":"book_editor","citation":{"mla":"Platzner, Marco, et al., editors. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010, doi:10.1007/978-90-481-3485-4.","bibtex":"@book{Platzner_Teich_Wehn_2010, title={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, DOI={10.1007/978-90-481-3485-4}, publisher={Springer-Verlag GmbH}, year={2010} }","chicago":"Platzner, Marco, Jürgen Teich, and Norbert Wehn, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010. https://doi.org/10.1007/978-90-481-3485-4.","apa":"Platzner, M., Teich, J., & Wehn, N. (Eds.). (2010). Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4","ama":"Platzner M, Teich J, Wehn N, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH; 2010. doi:10.1007/978-90-481-3485-4","ieee":"M. Platzner, J. Teich, and N. Wehn, Eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010.","short":"M. Platzner, J. Teich, N. Wehn, eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010."},"year":"2010","language":[{"iso":"eng"}],"doi":"10.1007/978-90-481-3485-4","date_updated":"2022-01-06T06:50:50Z","_id":"10763","editor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Teich","first_name":"Jürgen","full_name":"Teich, Jürgen"},{"full_name":"Wehn, Norbert","first_name":"Norbert","last_name":"Wehn"}],"publication_identifier":{"isbn":["9048134846"]},"status":"public","date_created":"2019-07-10T12:07:04Z","publisher":"Springer-Verlag GmbH","department":[{"_id":"78"}],"title":"Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications","user_id":"3118"},{"status":"public","date_created":"2019-07-10T12:10:19Z","publisher":"IEEE","author":[{"full_name":"Khatir, Mehrdad","first_name":"Mehrdad","last_name":"Khatir"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"last_name":"Ejlali","full_name":"Ejlali, Alireza","first_name":"Alireza"}],"publication":"Computer Design (ICCD), 2010 IEEE International Conference on","department":[{"_id":"78"}],"title":"Sub-threshold charge recovery circuits","user_id":"3118","extern":"1","citation":{"chicago":"Khatir, Mehrdad, Hassan Ghasemzadeh Mohammadi, and Alireza Ejlali. “Sub-Threshold Charge Recovery Circuits.” In Computer Design (ICCD), 2010 IEEE International Conference On, 138–44. IEEE, 2010. https://doi.org/10.1109/ICCD.2010.5647815.","ama":"Khatir M, Ghasemzadeh Mohammadi H, Ejlali A. Sub-threshold charge recovery circuits. In: Computer Design (ICCD), 2010 IEEE International Conference On. IEEE; 2010:138-144. doi:10.1109/ICCD.2010.5647815","apa":"Khatir, M., Ghasemzadeh Mohammadi, H., & Ejlali, A. (2010). Sub-threshold charge recovery circuits. In Computer Design (ICCD), 2010 IEEE International Conference on (pp. 138–144). IEEE. https://doi.org/10.1109/ICCD.2010.5647815","mla":"Khatir, Mehrdad, et al. “Sub-Threshold Charge Recovery Circuits.” Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–44, doi:10.1109/ICCD.2010.5647815.","bibtex":"@inproceedings{Khatir_Ghasemzadeh Mohammadi_Ejlali_2010, title={Sub-threshold charge recovery circuits}, DOI={10.1109/ICCD.2010.5647815}, booktitle={Computer Design (ICCD), 2010 IEEE International Conference on}, publisher={IEEE}, author={Khatir, Mehrdad and Ghasemzadeh Mohammadi, Hassan and Ejlali, Alireza}, year={2010}, pages={138–144} }","short":"M. Khatir, H. Ghasemzadeh Mohammadi, A. Ejlali, in: Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–144.","ieee":"M. Khatir, H. Ghasemzadeh Mohammadi, and A. Ejlali, “Sub-threshold charge recovery circuits,” in Computer Design (ICCD), 2010 IEEE International Conference on, 2010, pp. 138–144."},"year":"2010","type":"conference","page":"138-144","language":[{"iso":"eng"}],"doi":"10.1109/ICCD.2010.5647815","_id":"10776","date_updated":"2022-01-06T06:50:50Z"},{"language":[{"iso":"eng"}],"year":"2010","citation":{"ieee":"H. Giefers and M. Platzner, “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), 2010.","short":"H. Giefers, M. Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.","mla":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.","bibtex":"@inproceedings{Giefers_Platzner_2010, title={A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier}, booktitle={Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }","chicago":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2010.","ama":"Giefers H, Platzner M. A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2010.","apa":"Giefers, H., & Platzner, M. (2010). A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE."},"type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13640","status":"public","date_created":"2019-10-04T22:31:38Z","publisher":"IEEE","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"user_id":"398","title":"A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier"},{"user_id":"398","title":"Engineering Self-Coordinating Software Intensive Systems","author":[{"last_name":"Schäfer","first_name":"Wilhelm","full_name":"Schäfer, Wilhelm"},{"last_name":"Birattari","full_name":"Birattari, Mauro","first_name":"Mauro"},{"first_name":"Johannes","full_name":"Blömer, Johannes","last_name":"Blömer"},{"first_name":"Marco","full_name":"Dorigo, Marco","last_name":"Dorigo"},{"last_name":"Engels","first_name":"Gregor","full_name":"Engels, Gregor"},{"last_name":"O'Grady","full_name":"O'Grady, Rehan","first_name":"Rehan"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Franz-Josef","full_name":"Rammig, Franz-Josef","last_name":"Rammig"},{"last_name":"Reif","full_name":"Reif, Wolfgang ","first_name":"Wolfgang "},{"last_name":"Trächtler","first_name":"Ansgar","full_name":"Trächtler, Ansgar"}],"department":[{"_id":"78"}],"publication":"Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)","status":"public","date_created":"2019-10-04T22:35:54Z","_id":"13641","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"2010","citation":{"ama":"Schäfer W, Birattari M, Blömer J, et al. Engineering Self-Coordinating Software Intensive Systems. In: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER). ; 2010:321-324.","apa":"Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R., … Trächtler, A. (2010). Engineering Self-Coordinating Software Intensive Systems. In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) (pp. 321–324).","chicago":"Schäfer, Wilhelm, Mauro Birattari, Johannes Blömer, Marco Dorigo, Gregor Engels, Rehan O’Grady, Marco Platzner, Franz-Josef Rammig, Wolfgang Reif, and Ansgar Trächtler. “Engineering Self-Coordinating Software Intensive Systems.” In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 321–24, 2010.","bibtex":"@inproceedings{Schäfer_Birattari_Blömer_Dorigo_Engels_O’Grady_Platzner_Rammig_Reif_Trächtler_2010, title={Engineering Self-Coordinating Software Intensive Systems}, booktitle={Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)}, author={Schäfer, Wilhelm and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O’Grady, Rehan and Platzner, Marco and Rammig, Franz-Josef and Reif, Wolfgang and Trächtler, Ansgar}, year={2010}, pages={321–324} }","mla":"Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–24.","short":"W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.","ieee":"W. Schäfer et al., “Engineering Self-Coordinating Software Intensive Systems,” in Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324."},"type":"conference","page":"321-324"},{"type":"conference","citation":{"short":"H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.","ieee":"H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010.","chicago":"Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","ama":"Giefers H, Platzner M. A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.","apa":"Giefers, H., & Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","mla":"Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.","bibtex":"@inproceedings{Giefers_Platzner_2010, title={A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics}, booktitle={Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }"},"year":"2010","language":[{"iso":"eng"}],"_id":"13642","date_updated":"2022-01-06T06:51:40Z","publisher":"CSREA Press","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2019-10-04T22:37:54Z","title":"A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics","user_id":"398"},{"page":"225-231","citation":{"mla":"Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.","bibtex":"@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }","chicago":"Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–31. CSREA Press, 2010.","apa":"Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.","ama":"Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:225-231.","ieee":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.","short":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231."},"year":"2010","type":"conference","language":[{"iso":"eng"}],"_id":"2223","date_updated":"2023-09-26T13:48:32Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","quality_controlled":"1","publisher":"CSREA Press","author":[{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Ariane","full_name":"Keller, Ariane","last_name":"Keller"},{"first_name":"Bernhard","full_name":"Plattner, Bernhard","last_name":"Plattner"}],"publication_identifier":{"isbn":["1-60132-140-6"]},"date_created":"2018-04-05T16:27:13Z","status":"public","title":"Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware","user_id":"15278"},{"language":[{"iso":"eng"}],"type":"conference","year":"2010","citation":{"mla":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.","bibtex":"@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={67–72} }","chicago":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010. https://doi.org/10.1109/ReConFig.2010.19.","apa":"Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19","ama":"Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19","ieee":"M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72."},"page":"67-72","doi":"10.1109/ReConFig.2010.19","_id":"2216","date_updated":"2023-09-26T13:47:11Z","status":"public","date_created":"2018-04-05T14:48:51Z","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","user_id":"15278","title":"Pruning the Design Space for Just-In-Time Processor Customization","place":"Los Alamitos, CA, USA"},{"date_created":"2018-04-05T16:28:38Z","status":"public","publication_identifier":{"isbn":["1-60132-140-6"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"CSREA Press","user_id":"15278","title":"An Open Source Circuit Library with Benchmarking Facilities","language":[{"iso":"eng"}],"page":"144-150","type":"conference","year":"2010","citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.","ieee":"M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.","ama":"Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.","apa":"Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.","chicago":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.","bibtex":"@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }","mla":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50."},"date_updated":"2023-09-26T13:48:59Z","_id":"2224"},{"title":"Configurable Processor Architectures: History and Trends","user_id":"15278","publisher":"CSREA Press","author":[{"last_name":"Andrews","first_name":"David","full_name":"Andrews, David"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publication_identifier":{"isbn":["1-60132-140-6"]},"status":"public","date_created":"2018-04-05T14:57:07Z","_id":"2220","date_updated":"2023-09-26T13:47:33Z","citation":{"short":"D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","ieee":"D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.","ama":"Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.","apa":"Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.","chicago":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165. CSREA Press, 2010.","mla":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","bibtex":"@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }"},"type":"conference","year":"2010","page":"165","language":[{"iso":"eng"}]},{"_id":"2222","date_updated":"2023-09-26T13:48:00Z","language":[{"iso":"eng"}],"type":"conference_editor","year":"2010","citation":{"bibtex":"@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, year={2010} }","mla":"Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","ama":"Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.","apa":"Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., & Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","chicago":"Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee, Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","ieee":"T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","short":"T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010."},"user_id":"15278","title":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","date_created":"2018-04-05T15:00:49Z","status":"public","publication_identifier":{"isbn":["1-60132-140-6"]},"editor":[{"last_name":"Plaks","full_name":"Plaks, Toomas P.","first_name":"Toomas P."},{"full_name":"Andrews, David","first_name":"David","last_name":"Andrews"},{"full_name":"DeMara, Ronald","first_name":"Ronald","last_name":"DeMara"},{"first_name":"Herman","full_name":"Lam, Herman","last_name":"Lam"},{"last_name":"Lee","first_name":"Jooheung","full_name":"Lee, Jooheung"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Stitt, Greg","first_name":"Greg","last_name":"Stitt"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"CSREA Press"},{"date_created":"2018-04-05T16:39:34Z","status":"public","publication_identifier":{"isbn":["978-1-4244-6965-9"]},"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"last_name":"Niekamp","full_name":"Niekamp, Manuel","first_name":"Manuel"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","publisher":"IEEE Computer Society","user_id":"15278","title":"Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators","language":[{"iso":"eng"}],"page":"65-72","type":"conference","citation":{"mla":"Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.","bibtex":"@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}, DOI={10.1109/ASAP.2010.5540798}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }","chicago":"Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.","apa":"Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798","ama":"Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798","ieee":"T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.","short":"T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72."},"year":"2010","doi":"10.1109/ASAP.2010.5540798","_id":"2226","date_updated":"2023-09-26T13:49:21Z"},{"publication":"Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE","author":[{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"full_name":"Plattner, Bernhard","first_name":"Bernhard","last_name":"Plattner"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","date_created":"2018-04-04T09:36:16Z","status":"public","publication_identifier":{"isbn":["978-1-4244-8864-3"]},"user_id":"15278","title":"Reconfigurable Nodes for Future Networks","language":[{"iso":"eng"}],"page":"372-376","year":"2010","citation":{"ieee":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.","short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341.","chicago":"Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.","apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341","ama":"Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341"},"type":"conference","_id":"2206","date_updated":"2023-09-26T13:51:00Z","doi":"10.1109/GLOCOMW.2010.5700341"},{"citation":{"ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). ; 2010.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)."},"type":"conference","year":"2010","language":[{"iso":"eng"}],"_id":"2228","date_updated":"2023-09-26T13:50:04Z","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Kauschke, Michael","first_name":"Michael","last_name":"Kauschke"}],"editor":[{"last_name":"Hammami","first_name":"Omar","full_name":"Hammami, Omar"},{"full_name":"Larrabee, Sandra","first_name":"Sandra","last_name":"Larrabee"}],"date_created":"2018-04-05T16:43:04Z","status":"public","title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","user_id":"15278"},{"language":[{"iso":"eng"}],"citation":{"ieee":"A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets,” in Proc. Technically Assisted Rehabilitation (TAR), 2009.","short":"A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically Assisted Rehabilitation (TAR), 2009.","bibtex":"@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009} }","mla":"Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted Rehabilitation (TAR), 2009.","apa":"Boschmann, A., Kaufmann, P., Platzner, M., & Winkler, M. (2009). Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In Proc. Technically Assisted Rehabilitation (TAR).","ama":"Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In: Proc. Technically Assisted Rehabilitation (TAR). ; 2009.","chicago":"Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” In Proc. Technically Assisted Rehabilitation (TAR), 2009."},"type":"conference","year":"2009","date_updated":"2022-01-06T06:50:49Z","_id":"10639","status":"public","date_created":"2019-07-10T11:03:25Z","author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Winkler","first_name":"Michael","full_name":"Winkler, Michael"}],"department":[{"_id":"78"}],"publication":"Proc. Technically Assisted Rehabilitation (TAR)","user_id":"3118","title":"Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets"},{"_id":"10702","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"citation":{"bibtex":"@book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn University}, author={Kostin, Alexander}, year={2009} }","mla":"Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009.","chicago":"Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009.","apa":"Kostin, A. (2009). Evolvable Robot Controller. Paderborn University.","ama":"Kostin A. Evolvable Robot Controller. Paderborn University; 2009.","ieee":"A. Kostin, Evolvable Robot Controller. Paderborn University, 2009.","short":"A. Kostin, Evolvable Robot Controller, Paderborn University, 2009."},"type":"mastersthesis","year":"2009","user_id":"3118","title":"Evolvable Robot Controller","date_created":"2019-07-10T11:38:28Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Kostin","first_name":"Alexander","full_name":"Kostin, Alexander"}],"publisher":"Paderborn University"},{"user_id":"3118","title":"ReconOS: Multithreaded Programming for Reconfigurable Computers","status":"public","date_created":"2019-07-10T11:41:17Z","publication_identifier":{"issn":["1539-9087"]},"volume":9,"author":[{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["Reconfigurable computing","multithreading","operating systems"],"department":[{"_id":"78"}],"publication":"ACM Transactions on Embedded Computing Systems","issue":"1","doi":"10.1145/1596532.1596540","_id":"10703","intvolume":" 9","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"type":"journal_article","citation":{"bibtex":"@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={10.1145/1596532.1596540}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.","ama":"Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems. 2009;9(1):8:1-8:33. doi:10.1145/1596532.1596540","apa":"Lübbers, E., & Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems, 9(1), 8:1-8:33. https://doi.org/10.1145/1596532.1596540","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems 9, no. 1 (2009): 8:1-8:33. https://doi.org/10.1145/1596532.1596540.","ieee":"E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, pp. 8:1-8:33, 2009.","short":"E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33."},"year":"2009","page":"8:1-8:33"},{"_id":"10746","date_updated":"2022-01-06T06:50:50Z","year":"2009","type":"mastersthesis","citation":{"mla":"Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.","bibtex":"@book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Tofall, Martin}, year={2009} }","apa":"Tofall, M. (2009). Compiler for a Custom Instruction Set CPU. Paderborn University.","ama":"Tofall M. Compiler for a Custom Instruction Set CPU. Paderborn University; 2009.","chicago":"Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.","ieee":"M. Tofall, Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.","short":"M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University, 2009."},"language":[{"iso":"eng"}],"title":"Compiler for a Custom Instruction Set CPU","user_id":"3118","author":[{"last_name":"Tofall","full_name":"Tofall, Martin","first_name":"Martin"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:01:52Z"},{"title":"Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units","user_id":"3118","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Warkentin, Alexander","first_name":"Alexander","last_name":"Warkentin"}],"date_created":"2019-07-10T12:02:58Z","status":"public","date_updated":"2022-01-06T06:50:50Z","_id":"10749","type":"mastersthesis","citation":{"bibtex":"@book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin, Alexander}, year={2009} }","mla":"Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009.","chicago":"Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009.","ama":"Warkentin A. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University; 2009.","apa":"Warkentin, A. (2009). Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units. Paderborn University.","ieee":"A. Warkentin, Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009.","short":"A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units, Paderborn University, 2009."},"year":"2009","supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}]},{"_id":"10753","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.","ieee":"B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.","chicago":"Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.","apa":"Wildenhain, B. (2009). Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University.","ama":"Wildenhain B. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University; 2009.","mla":"Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.","bibtex":"@book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain, Benedikt}, year={2009} }"},"type":"bachelorsthesis","year":"2009","language":[{"iso":"eng"}],"title":"Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS","user_id":"3118","date_created":"2019-07-10T12:05:17Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Wildenhain","full_name":"Wildenhain, Benedikt","first_name":"Benedikt"}]},{"user_id":"3118","title":"Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors","extern":"1","date_created":"2019-07-10T12:11:34Z","status":"public","department":[{"_id":"78"}],"publication":"Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"Miremadi","first_name":"Seyed Ghassem","full_name":"Miremadi, Seyed Ghassem"},{"last_name":"Ejlali","first_name":"Alireza","full_name":"Ejlali, Alireza"}],"publisher":"IEEE","doi":"10.1109/PRDC.2009.69","_id":"10777","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"page":"252-255","citation":{"apa":"Ghasemzadeh Mohammadi, H., Miremadi, S. G., & Ejlali, A. (2009). Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on (pp. 252–255). IEEE. https://doi.org/10.1109/PRDC.2009.69","ama":"Ghasemzadeh Mohammadi H, Miremadi SG, Ejlali A. Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On. IEEE; 2009:252-255. doi:10.1109/PRDC.2009.69","chicago":"Ghasemzadeh Mohammadi, Hassan, Seyed Ghassem Miremadi, and Alireza Ejlali. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, 252–55. IEEE, 2009. https://doi.org/10.1109/PRDC.2009.69.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–55, doi:10.1109/PRDC.2009.69.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Miremadi_Ejlali_2009, title={Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}, DOI={10.1109/PRDC.2009.69}, booktitle={Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2009}, pages={252–255} }","short":"H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.","ieee":"H. Ghasemzadeh Mohammadi, S. G. Miremadi, and A. Ejlali, “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors,” in Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on, 2009, pp. 252–255."},"year":"2009","type":"conference"},{"publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2019-10-04T22:13:24Z","status":"public","user_id":"398","title":"A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms","language":[{"iso":"eng"}],"citation":{"ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2009.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.","mla":"Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }","apa":"Happe, M., Lübbers, E., & Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer.","ama":"Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer; 2009.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer, 2009."},"year":"2009","type":"conference","_id":"13632","date_updated":"2022-01-06T06:51:40Z"},{"status":"public","date_created":"2019-10-04T22:16:01Z","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)","user_id":"398","title":"Towards Models for Many-Cores: The Case for the Reconfigurable Mesh","language":[{"iso":"eng"}],"citation":{"mla":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","apa":"Giefers, H., & Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS).","ama":"Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS). ; 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.","ieee":"H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh,” in Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.","short":"H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009."},"year":"2009","type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13634"},{"title":"ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores","user_id":"398","date_created":"2019-10-04T22:17:57Z","status":"public","publication":"Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium","department":[{"_id":"78"}],"author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","_id":"13635","date_updated":"2022-01-06T06:51:40Z","type":"conference","year":"2009","citation":{"short":"H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.","ieee":"H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores,” in Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, 2009.","apa":"Giefers, H., & Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE.","ama":"Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE; 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE, 2009.","mla":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }"},"language":[{"iso":"eng"}]},{"year":"2009","citation":{"short":"E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","ieee":"E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable Systems,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009.","chicago":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009.","apa":"Lübbers, E., & Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.","ama":"Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable Systems. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.","bibtex":"@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2009} }","mla":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","_id":"13636","status":"public","date_created":"2019-10-04T22:20:12Z","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","title":"Cooperative Multithreading in Dynamically Reconfigurable Systems","user_id":"398"},{"year":"2009","type":"conference","citation":{"bibtex":"@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","mla":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","apa":"Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.","ama":"Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009.","ieee":"H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009.","short":"H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009."},"language":[{"iso":"eng"}],"_id":"13637","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T22:22:02Z","status":"public","publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","department":[{"_id":"78"}],"author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","title":"Program-driven Fine-grained Power Management for the Reconfigurable Mesh","user_id":"398"},{"user_id":"398","title":"An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning","status":"public","date_created":"2019-10-04T22:22:52Z","publication_status":"published","publication_identifier":{"isbn":["9781424443758"]},"author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","publication":"Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"78"}],"doi":"10.1109/fpt.2009.5377645","date_updated":"2022-01-06T06:51:40Z","_id":"13638","language":[{"iso":"eng"}],"year":"2009","type":"conference","citation":{"ieee":"M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), 2009.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }","mla":"Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645.","apa":"Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645","ama":"Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645"}},{"status":"public","date_created":"2019-10-04T22:25:10Z","publisher":"IEEE","author":[{"full_name":"Drzevitzky, Stephanie","first_name":"Stephanie","last_name":"Drzevitzky"},{"full_name":"Kastens, Uwe","first_name":"Uwe","last_name":"Kastens"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"user_id":"398","title":"Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules","language":[{"iso":"eng"}],"year":"2009","citation":{"ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.","short":"S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.","bibtex":"@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.","apa":"Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.","chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2009."},"type":"conference","_id":"13639","date_updated":"2022-01-06T06:51:40Z"},{"_id":"2350","year":"2009","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25."},"type":"conference","page":"275-278","abstract":[{"lang":"eng","text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. "}],"user_id":"15278","publisher":"IEEE Computer Society","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","keyword":["IMORC","interconnect","performance"],"status":"public","date_created":"2018-04-16T15:05:52Z","date_updated":"2023-09-26T13:51:44Z","doi":"10.1109/FCCM.2009.25","language":[{"iso":"eng"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]}},{"_id":"2262","date_updated":"2023-09-26T13:53:11Z","language":[{"iso":"eng"}],"page":"11-18","citation":{"short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18."},"year":"2009","type":"conference","user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"place":"Los Alamitos, CA, USA","date_created":"2018-04-06T15:18:24Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","keyword":["EvoCache","evolvable hardware","computer architecture"],"publisher":"IEEE Computer Society","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","graphics"],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"full_name":"Süß, Tim","first_name":"Tim","last_name":"Süß"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication_identifier":{"isbn":["978-0-7695-3917-1"]},"date_created":"2018-04-05T17:11:28Z","status":"public","place":"Los Alamitos, CA, USA","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","user_id":"15278","page":"119-124","type":"conference","year":"2009","citation":{"ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32"},"language":[{"iso":"eng"}],"_id":"2238","date_updated":"2023-09-26T13:52:32Z","doi":"10.1109/ReConFig.2009.32"},{"date_updated":"2023-09-26T13:52:52Z","_id":"2261","page":"338-344","year":"2009","type":"conference","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009."},"language":[{"iso":"eng"}],"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","user_id":"15278","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["IMORC","NOC","KNN","accelerator"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"date_created":"2018-04-06T15:15:47Z","status":"public"},{"date_updated":"2023-09-26T13:53:30Z","_id":"2263","type":"conference","citation":{"ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009."},"year":"2009","page":"319-322","language":[{"iso":"eng"}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","place":"USA","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}],"publication_identifier":{"isbn":["1-60132-101-5"]},"status":"public","date_created":"2018-04-06T15:19:51Z","quality_controlled":"1","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"CSREA Press","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"title":"A method for OSEM PET reconstruction on parallel architectures using STIR","user_id":"24135","publication":"IEEE Nuclear Science Symposium Conference Record (NSS)","department":[{"_id":"27"},{"_id":"78"}],"publisher":"IEEE","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"first_name":"Stefan","full_name":"Lietsch, Stefan","last_name":"Lietsch"},{"full_name":"Thielemans, Kris","first_name":"Kris","last_name":"Thielemans"}],"date_created":"2018-04-17T10:59:40Z","status":"public","_id":"2358","date_updated":"2022-01-06T06:55:57Z","doi":"10.1109/NSSMIC.2008.4774198","page":"4161-4168","year":"2008","citation":{"bibtex":"@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }","mla":"Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198.","chicago":"Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198.","apa":"Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198","ama":"Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198","ieee":"T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference Record (NSS), 2008, pp. 4161–4168.","short":"T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–4168."},"type":"conference"},{"year":"2008","type":"conference","citation":{"mla":"Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.","bibtex":"@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }","chicago":"Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.","apa":"Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.","ama":"Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.","ieee":"M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","short":"M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251."},"page":"245-251","_id":"2365","date_updated":"2022-01-06T06:55:58Z","publication_identifier":{"isbn":["1-60132-064-7"]},"status":"public","date_created":"2018-04-17T11:34:35Z","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Sven","full_name":"Döhre, Sven","last_name":"Döhre"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Lorenz, Ulf","first_name":"Ulf","last_name":"Lorenz"},{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"full_name":"Send, Andre","first_name":"Andre","last_name":"Send"},{"last_name":"Warkentin","full_name":"Warkentin, Alexander","first_name":"Alexander"}],"publisher":"CSREA Press","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","title":"The GOmputer: Accelerating GO with FPGAs","user_id":"24135"},{"date_created":"2019-07-10T09:40:26Z","status":"public","alternative_title":["Effects of Pattern Matching Algorithms on Long-term Electromyography Signals"],"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"}],"user_id":"3118","title":"Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"type":"bachelorsthesis","year":"2008","citation":{"ieee":"A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","short":"A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen, Paderborn University, 2008.","bibtex":"@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }","mla":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","chicago":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","apa":"Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University.","ama":"Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University; 2008."},"date_updated":"2022-01-06T06:50:48Z","_id":"10628"},{"title":"Selbstoptimierender Cache-Kontroller","user_id":"3118","alternative_title":["Self-optimizing Cache Controller"],"date_created":"2019-07-10T11:03:42Z","status":"public","department":[{"_id":"78"}],"author":[{"full_name":"Breitlauch, Daniel","first_name":"Daniel","last_name":"Breitlauch"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","_id":"10641","citation":{"short":"D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008.","ieee":"D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.","ama":"Breitlauch D. Selbstoptimierender Cache-Kontroller. Paderborn University; 2008.","apa":"Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn University.","chicago":"Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.","mla":"Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.","bibtex":"@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }"},"type":"bachelorsthesis","year":"2008","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}]},{"alternative_title":["Distributed Simulation of mobile Robots using EyeSim"],"status":"public","date_created":"2019-07-10T11:03:45Z","author":[{"first_name":"Toni","full_name":"Ceylan, Toni","last_name":"Ceylan"},{"last_name":"Yalcin","full_name":"Yalcin, Coni","first_name":"Coni"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"title":"Verteilte Simulation von mobilen Robotern mit EyeSim","user_id":"3118","type":"bachelorsthesis","year":"2008","citation":{"short":"T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008.","ieee":"T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University, 2008.","chicago":"Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008.","ama":"Ceylan T, Yalcin C. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University; 2008.","apa":"Ceylan, T., & Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University.","bibtex":"@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }","mla":"Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008."},"language":[{"iso":"eng"}],"supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10644"},{"language":[{"iso":"eng"}],"page":"32-39","year":"2008","citation":{"bibtex":"@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }","mla":"Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.","apa":"Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., & Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp. 32–39). IEEE.","ama":"Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: IEEE Adaptive Hardware and Systems (AHS). IEEE; 2008:32-39.","chicago":"Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” In IEEE Adaptive Hardware and Systems (AHS), 32–39. IEEE, 2008.","ieee":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS), 2008, pp. 32–39.","short":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39."},"type":"conference","_id":"10653","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:13:13Z","status":"public","department":[{"_id":"78"}],"publication":"IEEE Adaptive Hardware and Systems (AHS)","publisher":"IEEE","author":[{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"last_name":"Gruber","full_name":"Gruber, Thiemo","first_name":"Thiemo"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"last_name":"Sick","first_name":"Bernhard","full_name":"Sick, Bernhard"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"3118","title":"Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control"},{"series_title":"LNCS","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={22–33}, collection={LNCS} }","mla":"Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 5216, Springer, 2008, pp. 22–33.","apa":"Glette, K., Torresen, J., Kaufmann, P., & Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer.","ama":"Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 5216. LNCS. Springer; 2008:22-33.","chicago":"Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 5216:22–33. LNCS. Springer, 2008.","ieee":"K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2008, vol. 5216, pp. 22–33.","short":"K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33."},"type":"conference","year":"2008","page":"22-33","_id":"10656","date_updated":"2022-01-06T06:50:49Z","intvolume":" 5216","publisher":"Springer","author":[{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:13:31Z","volume":5216,"user_id":"3118","title":"A Comparison of Evolvable Hardware Architectures for Classification Tasks"},{"user_id":"3118","title":"Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern","date_created":"2019-07-10T11:15:14Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10669","language":[{"iso":"eng"}],"year":"2008","type":"mastersthesis","citation":{"mla":"Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","bibtex":"@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }","apa":"Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University.","ama":"Happe M. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University; 2008.","chicago":"Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","ieee":"M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","short":"M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008."}},{"title":"Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)","user_id":"398","date_created":"2019-07-10T11:29:14Z","status":"public","department":[{"_id":"78"}],"author":[{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"_id":"10690","date_updated":"2022-01-06T06:50:49Z","year":"2008","citation":{"apa":"Torresen, J., Glette, K., Platzner, M., & Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).","ama":"Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","chicago":"Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008.","mla":"Torresen, Jim, et al. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","bibtex":"@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }","short":"J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).","ieee":"J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008."},"type":"preprint","language":[{"iso":"eng"}]},{"user_id":"3118","title":"Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming","publication":"Genetic and Evolutionary Computation (GECCO)","department":[{"_id":"78"}],"publisher":"ACM Press","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T11:29:57Z","status":"public","_id":"10691","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"page":"1219 - 1226","citation":{"ieee":"P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), 2008, pp. 1219–1226.","short":"P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.","bibtex":"@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }","mla":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–26.","chicago":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), 1219–26. ACM Press, 2008.","ama":"Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO). ACM Press; 2008:1219-1226.","apa":"Kaufmann, P., & Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press."},"type":"conference","year":"2008"},{"user_id":"3118","title":"Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Knieper","full_name":"Knieper, Tobias","first_name":"Tobias"}],"date_created":"2019-07-10T11:30:22Z","status":"public","alternative_title":["Multi-objective Optimizer IBEA for Digital Logic Design"],"_id":"10696","date_updated":"2022-01-06T06:50:49Z","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"year":"2008","citation":{"short":"T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.","ieee":"T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008.","chicago":"Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008.","apa":"Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University.","ama":"Knieper T. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University; 2008.","bibtex":"@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }","mla":"Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008."},"type":"bachelorsthesis"},{"intvolume":" 268","_id":"10698","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"type":"conference","year":"2008","citation":{"ieee":"T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC), 2008, vol. 268, pp. 2313–222.","short":"T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.","bibtex":"@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={2313–222}, collection={IFIP International Federation for Information Processing} }","mla":"Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” Biologically Inspired Collaborative Computing (BICC), vol. 268, Springer, 2008, pp. 2313–222.","apa":"Knieper, T., Defo, B., Kaufmann, P., & Platzner, M. (2008). On Robust Evolution of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC) (Vol. 268, pp. 2313–222). Springer.","ama":"Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: Biologically Inspired Collaborative Computing (BICC). Vol 268. IFIP International Federation for Information Processing. Springer; 2008:2313-222.","chicago":"Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In Biologically Inspired Collaborative Computing (BICC), 268:2313–222. IFIP International Federation for Information Processing. Springer, 2008."},"page":"2313-222","series_title":"IFIP International Federation for Information Processing","user_id":"3118","title":"On Robust Evolution of Digital Hardware","status":"public","date_created":"2019-07-10T11:38:02Z","volume":268,"publisher":"Springer","author":[{"last_name":"Knieper","full_name":"Knieper, Tobias","first_name":"Tobias"},{"last_name":"Defo","first_name":"Bertrand","full_name":"Defo, Bertrand"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Biologically Inspired Collaborative Computing (BICC)","department":[{"_id":"78"}]},{"date_updated":"2022-01-06T06:50:50Z","_id":"10718","language":[{"iso":"eng"}],"year":"2008","citation":{"chicago":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","apa":"Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University.","ama":"Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University; 2008.","bibtex":"@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }","mla":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","short":"J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008.","ieee":"J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008."},"type":"bachelorsthesis","user_id":"3118","title":"Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Jörg","full_name":"Niklas, Jörg","last_name":"Niklas"}],"date_created":"2019-07-10T11:48:29Z","status":"public"},{"_id":"10721","date_updated":"2022-01-06T06:50:50Z","year":"2008","citation":{"short":"M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008.","ieee":"M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","apa":"Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University.","ama":"Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University; 2008.","chicago":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","bibtex":"@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }","mla":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008."},"type":"bachelorsthesis","language":[{"iso":"eng"}],"title":"Raytracing on a Custom Instruction Set CPU","user_id":"3118","department":[{"_id":"78"}],"author":[{"full_name":"Östermann, Marco","first_name":"Marco","last_name":"Östermann"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:52:51Z","status":"public"},{"user_id":"3118","title":"Design and Evaluation of MicroBlaze Multi-core Architectures","publisher":"Paderborn University","author":[{"last_name":"Westerheide","first_name":"Nico","full_name":"Westerheide, Nico"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:03:01Z","date_updated":"2022-01-06T06:50:50Z","_id":"10751","language":[{"iso":"eng"}],"citation":{"short":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008.","ieee":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008.","chicago":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008.","apa":"Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University.","ama":"Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University; 2008.","bibtex":"@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }","mla":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008."},"type":"bachelorsthesis","year":"2008"},{"title":"A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic","user_id":"3118","extern":"1","date_created":"2019-07-10T12:11:35Z","status":"public","publication":"2008 International Conference on Microelectronics","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"first_name":"Hamed","full_name":"Tabkhi, Hamed","last_name":"Tabkhi"},{"last_name":"Miremadi","first_name":"Seyed Ghassem","full_name":"Miremadi, Seyed Ghassem"},{"last_name":"Ejlali","full_name":"Ejlali, Alireza","first_name":"Alireza"}],"doi":"10.1109/ICM.2008.5393497","_id":"10778","date_updated":"2022-01-06T06:50:50Z","page":"444-447","citation":{"short":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.","ieee":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447.","apa":"Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497","ama":"Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497","chicago":"Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In 2008 International Conference on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={10.1109/ICM.2008.5393497}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }"},"year":"2008","type":"conference","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"short":"H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.","ieee":"H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008.","chicago":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE, 2008.","ama":"Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE; 2008.","apa":"Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE.","bibtex":"@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }","mla":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008."},"type":"conference","year":"2008","date_updated":"2022-01-06T06:51:40Z","_id":"13629","publisher":"IEEE","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)","status":"public","date_created":"2019-10-04T22:05:22Z","user_id":"398","title":"Realizing Reconfigurable Mesh Algorithms on Softcore Arrays"},{"status":"public","date_created":"2019-10-04T22:07:14Z","author":[{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","department":[{"_id":"78"}],"publication":"Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","user_id":"398","title":"Communication and Synchronization in Multithreaded Reconfigurable Computing Systems","language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","mla":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","apa":"Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","ama":"Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008.","chicago":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2008."},"year":"2008","_id":"13630","date_updated":"2022-01-06T06:51:40Z"},{"publication":"Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","date_created":"2019-10-04T22:07:43Z","status":"public","publication_status":"published","publication_identifier":{"isbn":["9781424419609"]},"user_id":"398","title":"A portable abstraction layer for hardware threads","language":[{"iso":"eng"}],"year":"2008","type":"conference","citation":{"short":"E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.","ieee":"E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), 2008.","ama":"Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901","apa":"Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901","chicago":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901.","mla":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={10.1109/fpl.2008.4629901}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }"},"_id":"13631","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/fpl.2008.4629901"},{"date_updated":"2023-09-26T13:54:24Z","_id":"2364","language":[{"iso":"eng"}],"page":"245-251","type":"conference","citation":{"bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.","ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.","ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251."},"year":"2008","user_id":"15278","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"CSREA Press","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","date_created":"2018-04-17T11:33:32Z","status":"public","publication_identifier":{"isbn":["1-60132-064-7"]}},{"user_id":"15278","title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","status":"public","date_created":"2018-04-17T12:05:28Z","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1","keyword":["IMORC","IP core","interconnect"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)","date_updated":"2023-09-26T13:55:51Z","_id":"2372","language":[{"iso":"eng"}],"citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008."},"type":"conference","year":"2008"},{"language":[{"iso":"eng"}],"doi":"10.1109/ahs.2007.73","date_updated":"2022-01-06T07:03:08Z","publication_status":"published","publication_identifier":{"isbn":["076952866X","9780769528663"]},"department":[{"_id":"78"}],"title":"MOVES: A Modular Framework for Hardware Evolution","citation":{"short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK, 2007, pp. 447–454.","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.","apa":"Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={10.1109/ahs.2007.73}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }"},"year":"2007","type":"conference","page":"447-454","_id":"6508","conference":{"location":"Edinburgh, UK","start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","end_date":"2007-08-08"},"status":"public","date_created":"2019-01-08T09:52:43Z","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"user_id":"3118","abstract":[{"text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.","lang":"eng"}]},{"language":[{"iso":"eng"}],"year":"2007","type":"mastersthesis","citation":{"mla":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007.","bibtex":"@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }","chicago":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007.","apa":"Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University.","ama":"Beisel T. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University; 2007.","ieee":"T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007.","short":"T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007."},"_id":"10623","date_updated":"2022-01-06T06:50:48Z","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:36:57Z","user_id":"3118","title":"Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen"},{"user_id":"398","title":"Dynamically Reconfigurable Architectures (editorial)","date_created":"2019-07-10T09:40:11Z","status":"public","volume":2007,"department":[{"_id":"78"}],"publication":"{EURASIP} Journal on Embedded Systems","publisher":"Springer Science+Business Media","author":[{"last_name":"Bergmann","first_name":"Neil","full_name":"Bergmann, Neil"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Teich, Jürgen","first_name":"Jürgen","last_name":"Teich"}],"doi":"10.1155/2007/28405","_id":"10625","date_updated":"2022-01-06T06:50:48Z","intvolume":" 2007","language":[{"iso":"eng"}],"page":"1-2","type":"journal_article","citation":{"ieee":"N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” {EURASIP} Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007.","short":"N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2.","bibtex":"@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }","mla":"Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405.","chicago":"Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems 2007 (2007): 1–2. https://doi.org/10.1155/2007/28405.","ama":"Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405","apa":"Bergmann, N., Platzner, M., & Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems, 2007, 1–2. https://doi.org/10.1155/2007/28405"},"year":"2007"},{"publisher":"Paderborn University","author":[{"last_name":"Ceylan","first_name":"Toni","full_name":"Ceylan, Toni"},{"first_name":"Coni","full_name":"Yalcin, Coni","last_name":"Yalcin"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:03:44Z","title":"Distributed Simulation of mobile Robots using EyeSim","user_id":"3118","type":"bachelorsthesis","citation":{"ieee":"T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007.","short":"T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007.","bibtex":"@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }","mla":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007.","ama":"Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007.","apa":"Ceylan, T., & Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University.","chicago":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007."},"year":"2007","supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10643"},{"title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware","user_id":"3118","volume":1,"publication_identifier":{"issn":["1751-8601"]},"status":"public","date_created":"2019-07-10T11:10:54Z","author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"last_name":"Mühlenbernd","first_name":"Roland","full_name":"Mühlenbernd, Roland"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"],"department":[{"_id":"78"}],"publication":"IET Computers Digital Techniques","doi":"10.1049/iet-cdt:20060186","issue":"4","intvolume":" 1","_id":"10646","date_updated":"2022-01-06T06:50:49Z","citation":{"ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.","short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques 1, no. 4 (2007): 295–302. https://doi.org/10.1049/iet-cdt:20060186.","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186","apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302. https://doi.org/10.1049/iet-cdt:20060186"},"year":"2007","type":"journal_article","page":"295-302","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"citation":{"short":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007.","ieee":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","ama":"Defo B. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University; 2007.","apa":"Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University.","chicago":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","mla":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","bibtex":"@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }"},"type":"mastersthesis","year":"2007","date_updated":"2022-01-06T06:50:49Z","_id":"10647","date_created":"2019-07-10T11:10:55Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Defo, Bertrand","first_name":"Bertrand","last_name":"Defo"}],"user_id":"3118","title":"A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization"},{"_id":"10648","date_updated":"2022-01-06T06:50:49Z","type":"mastersthesis","year":"2007","citation":{"mla":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","bibtex":"@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }","chicago":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","apa":"Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University.","ama":"Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007.","ieee":"S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007.","short":"S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007."},"language":[{"iso":"eng"}],"title":"Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme","user_id":"3118","date_created":"2019-07-10T11:10:56Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Döhre","full_name":"Döhre, Sven","first_name":"Sven"}],"publisher":"Paderborn University"},{"language":[{"iso":"eng"}],"type":"conference","year":"2007","citation":{"short":"P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208.","ieee":"P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208.","chicago":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” In Architecture of Computing Systems (ARCS), 4415:199–208. LNCS. Springer, 2007.","apa":"Kaufmann, P., & Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.","ama":"Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In: Architecture of Computing Systems (ARCS). Vol 4415. LNCS. Springer; 2007:199-208.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }","mla":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” Architecture of Computing Systems (ARCS), vol. 4415, Springer, 2007, pp. 199–208."},"page":"199-208","series_title":"LNCS","_id":"10689","intvolume":" 4415","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:29:03Z","volume":4415,"publisher":"Springer","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Architecture of Computing Systems (ARCS)","user_id":"3118","title":"Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution"},{"user_id":"3118","title":"VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen","author":[{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:43:33Z","alternative_title":["k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving Mechanism Acceleration"],"_id":"10709","date_updated":"2022-01-06T06:50:50Z","supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"year":"2007","type":"bachelorsthesis","citation":{"short":"R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007.","ieee":"R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","chicago":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","apa":"Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University.","ama":"Meiche R. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University; 2007.","mla":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","bibtex":"@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }"}},{"date_updated":"2022-01-06T06:50:50Z","_id":"10728","language":[{"iso":"eng"}],"citation":{"chicago":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","ama":"Reisch W. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University; 2007.","apa":"Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University.","bibtex":"@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }","mla":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","short":"W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007.","ieee":"W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007."},"type":"mastersthesis","year":"2007","user_id":"3118","title":"Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Reisch","full_name":"Reisch, Waldemar","first_name":"Waldemar"}],"date_created":"2019-07-10T11:54:46Z","status":"public"},{"author":[{"last_name":"Rethmeier","first_name":"Eike","full_name":"Rethmeier, Eike"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:54:47Z","title":"Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem","user_id":"3118","citation":{"ieee":"E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007.","short":"E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007.","bibtex":"@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }","mla":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007.","chicago":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007.","ama":"Rethmeier E. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University; 2007.","apa":"Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University."},"year":"2007","type":"mastersthesis","language":[{"iso":"eng"}],"_id":"10729","date_updated":"2022-01-06T06:50:50Z"},{"series_title":"Advances in Parallel Computing","language":[{"iso":"eng"}],"page":"749-756","citation":{"ieee":"T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.","short":"T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.","bibtex":"@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances in Parallel Computing} }","mla":"Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), vol. 15, IOS Press, 2007, pp. 749–56.","chicago":"Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 15:749–56. Advances in Parallel Computing. IOS Press, 2007.","apa":"Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.","ama":"Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756."},"type":"conference","year":"2007","intvolume":" 15","_id":"10735","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"publication":"Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)","publisher":"IOS Press","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:58:09Z","status":"public","volume":15,"user_id":"398","title":"Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster"},{"language":[{"iso":"eng"}],"citation":{"ieee":"H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable Mesh Model,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.","short":"H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.","bibtex":"@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation Based on the Reconfigurable Mesh Model}, DOI={10.1109/fpl.2007.4380623}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2007} }","mla":"Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380623.","ama":"Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable Mesh Model. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380623","apa":"Giefers, H., & Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380623","chicago":"Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380623."},"type":"conference","year":"2007","_id":"13627","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/fpl.2007.4380623","publication":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-10-04T21:57:25Z","status":"public","publication_identifier":{"isbn":["9781424410590","9781424410606"]},"publication_status":"published","user_id":"398","title":"A Many-Core Implementation Based on the Reconfigurable Mesh Model"},{"title":"ReconOS: An RTOS Supporting Hard-and Software Threads","user_id":"398","publication_identifier":{"isbn":["9781424410590","9781424410606"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:58:35Z","publisher":"IEEE","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"doi":"10.1109/fpl.2007.4380686","date_updated":"2022-01-06T06:51:40Z","_id":"13628","type":"conference","year":"2007","citation":{"ieee":"E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.","bibtex":"@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.","apa":"Lübbers, E., & Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380686","ama":"Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380686."},"language":[{"iso":"eng"}]},{"page":"345-348","year":"2006","citation":{"short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348.","apa":"Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344."},"type":"conference","doi":"10.1109/FPT.2006.270344","date_updated":"2022-01-06T06:56:05Z","_id":"2401","date_created":"2018-04-17T13:43:21Z","status":"public","department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","keyword":["temporal partitioning","retiming","ILP"],"author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE Computer Society","title":"Optimal Temporal Partitioning based on Slowdown and Retiming","user_id":"24135","abstract":[{"text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ","lang":"eng"}]},{"date_updated":"2022-01-06T06:50:49Z","_id":"10688","type":"conference","year":"2006","citation":{"ieee":"P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","short":"P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","mla":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","bibtex":"@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }","chicago":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","apa":"Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD).","ama":"Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006."},"language":[{"iso":"eng"}],"title":"Multi-objective Intrinsic Hardware Evolution","user_id":"3118","department":[{"_id":"78"}],"publication":"Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T11:28:14Z","status":"public"},{"year":"2006","citation":{"short":"R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006.","ieee":"R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006.","ama":"Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006.","apa":"Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University.","chicago":"Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006.","bibtex":"@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }","mla":"Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006."},"type":"bachelorsthesis","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10716","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland","first_name":"Roland"}],"date_created":"2019-07-10T11:48:27Z","status":"public","title":"FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks","user_id":"3118"},{"_id":"13624","date_updated":"2022-01-06T06:51:40Z","citation":{"bibtex":"@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE.","ama":"Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006.","ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006.","short":"K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006."},"year":"2006","type":"conference","language":[{"iso":"eng"}],"title":"Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions","user_id":"398","publication":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland","first_name":"Roland"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","date_created":"2019-10-04T21:48:42Z","status":"public"},{"title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices","user_id":"398","publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","department":[{"_id":"78"}],"author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-10-04T21:51:29Z","status":"public","date_updated":"2022-01-06T06:51:40Z","_id":"13625","citation":{"chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","ama":"Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.","apa":"Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","short":"K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","ieee":"K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006."},"type":"conference","year":"2006","language":[{"iso":"eng"}]},{"_id":"13626","date_updated":"2022-01-06T06:51:40Z","type":"conference","citation":{"ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006.","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006."},"year":"2006","language":[{"iso":"eng"}],"title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","user_id":"398","date_created":"2019-10-04T21:53:12Z","status":"public","publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE CS Press"},{"year":"2005","type":"conference","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69","apa":"Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69."},"page":"213-218","_id":"2411","date_updated":"2022-01-06T06:56:07Z","doi":"10.1109/ASAP.2005.69","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE Computer Society","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-17T14:34:03Z","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","user_id":"24135"}]