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We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"status":"public","date_created":"2018-04-16T15:05:52Z","publisher":"IEEE Computer Society","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","_id":"2350","year":"2009","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25."},"type":"conference","page":"275-278","title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/FCCM.2009.25","date_updated":"2023-09-26T13:51:44Z","language":[{"iso":"eng"}]},{"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"place":"Los Alamitos, CA, USA","date_created":"2018-04-06T15:18:24Z","status":"public","keyword":["EvoCache","evolvable hardware","computer architecture"],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_updated":"2023-09-26T13:53:11Z","_id":"2262","language":[{"iso":"eng"}],"page":"11-18","year":"2009","citation":{"chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18."},"type":"conference"},{"doi":"10.1109/ReConFig.2009.32","_id":"2238","date_updated":"2023-09-26T13:52:32Z","citation":{"short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }"},"type":"conference","year":"2009","page":"119-124","language":[{"iso":"eng"}],"title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","user_id":"15278","place":"Los Alamitos, CA, USA","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"status":"public","date_created":"2018-04-05T17:11:28Z","quality_controlled":"1","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. 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(2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. 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The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"CSREA Press","quality_controlled":"1","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["1-60132-101-5"]},"status":"public","date_created":"2018-04-06T15:19:51Z","date_updated":"2023-09-26T13:53:30Z","_id":"2263","type":"conference","citation":{"ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009."},"year":"2009","page":"319-322","language":[{"iso":"eng"}]},{"user_id":"24135","title":"A method for OSEM PET reconstruction on parallel architectures using STIR","date_created":"2018-04-17T10:59:40Z","status":"public","publication":"IEEE Nuclear Science Symposium Conference Record (NSS)","department":[{"_id":"27"},{"_id":"78"}],"publisher":"IEEE","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"first_name":"Stefan","full_name":"Lietsch, Stefan","last_name":"Lietsch"},{"last_name":"Thielemans","full_name":"Thielemans, Kris","first_name":"Kris"}],"doi":"10.1109/NSSMIC.2008.4774198","date_updated":"2022-01-06T06:55:57Z","_id":"2358","page":"4161-4168","year":"2008","citation":{"mla":"Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198.","bibtex":"@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }","chicago":"Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198.","apa":"Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198","ama":"Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198","ieee":"T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference Record (NSS), 2008, pp. 4161–4168.","short":"T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–4168."},"type":"conference"},{"_id":"2365","date_updated":"2022-01-06T06:55:58Z","page":"245-251","citation":{"ieee":"M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","short":"M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","mla":"Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.","bibtex":"@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }","apa":"Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.","ama":"Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.","chicago":"Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008."},"year":"2008","type":"conference","title":"The GOmputer: Accelerating GO with FPGAs","user_id":"24135","publication_identifier":{"isbn":["1-60132-064-7"]},"date_created":"2018-04-17T11:34:35Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. 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Paderborn University, 2008.","short":"A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen, Paderborn University, 2008.","bibtex":"@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }","mla":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","ama":"Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University; 2008.","apa":"Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University.","chicago":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. 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Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","short":"K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","apa":"Danne, K., & Platzner, M. (2006). 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In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006."},"year":"2006","date_updated":"2022-01-06T06:51:40Z","_id":"13625","date_created":"2019-10-04T21:51:29Z","status":"public","department":[{"_id":"78"}],"publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"398","title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices"},{"user_id":"398","title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE CS Press","date_created":"2019-10-04T21:53:12Z","status":"public","_id":"13626","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"2006","type":"conference","citation":{"ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006.","short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006."}},{"keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","publisher":"IEEE Computer Society","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2018-04-17T14:34:03Z","status":"public","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"user_id":"24135","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","page":"213-218","citation":{"mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. 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Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004","apa":"Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. 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By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"user_id":"24135","title":"System-level performance evaluation of reconfigurable processors","publication":"Microprocessors and Microsystems","department":[{"_id":"518"},{"_id":"78"}],"keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"publisher":"Elsevier","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2018-04-17T14:36:10Z","status":"public","volume":29},{"user_id":"398","title":"Periodic real-time scheduling for FPGA computers","publication":"Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)","department":[{"_id":"78"}],"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-10-04T21:38:53Z","status":"public","publication_identifier":{"isbn":["3902463031"]},"publication_status":"published","_id":"13621","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/wises.2005.1438720","language":[{"iso":"eng"}],"type":"conference","year":"2005","citation":{"apa":"Danne, K., & Platzner, M. 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Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","ieee":"K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005."}},{"date_updated":"2022-01-06T06:51:40Z","_id":"13622","language":[{"iso":"eng"}],"type":"conference","year":"2005","citation":{"short":"K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","ieee":"K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005.","chicago":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","ama":"Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.","apa":"Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. 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Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84.","bibtex":"@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }","mla":"Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84."},"type":"conference","year":"2004","page":"831-835"},{"citation":{"short":"H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","ieee":"H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.","chicago":"Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.","apa":"Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","ama":"Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.","mla":"Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","bibtex":"@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }"},"year":"2004","type":"conference","language":[{"iso":"eng"}],"_id":"13619","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T21:31:54Z","status":"public","publication":"Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"author":[{"last_name":"Walder","full_name":"Walder, Hebert","first_name":"Hebert"},{"last_name":"Nobs","full_name":"Nobs, Samuel","first_name":"Samuel"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"CSREA Press","title":"XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems","user_id":"398","extern":"1"},{"publication_identifier":{"isbn":["0769522300"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:32:57Z","author":[{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE CS Press","publication":"Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"78"}],"title":"Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine","user_id":"398","citation":{"ieee":"M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.","short":"M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.","bibtex":"@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }","mla":"Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31.","apa":"Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31","ama":"Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31","chicago":"Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31."},"year":"2004","type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/fccm.2004.31","date_updated":"2022-01-06T06:51:40Z","_id":"13620"},{"doi":"10.1109/FPT.2003.1275755","_id":"2418","date_updated":"2022-01-06T06:56:09Z","type":"conference","year":"2003","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259.","chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.","apa":"Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }"},"page":"252-259","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","user_id":"24135","abstract":[{"lang":"eng","text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. "}],"status":"public","date_created":"2018-04-17T15:03:34Z","publisher":"IEEE Computer Society","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)"},{"title":"The Case for Reconfigurable Hardware in Wearable Computing","department":[{"_id":"518"},{"_id":"78"}],"date_updated":"2022-01-06T06:56:09Z","doi":"10.1007/s00779-003-0243-x","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM."}],"extern":"1","user_id":"398","publication":"Personal and Ubiquitous Computing","publisher":"Springer","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"last_name":"Beutel","full_name":"Beutel, Jan","first_name":"Jan"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"full_name":"Tröster, Gerhard","first_name":"Gerhard","last_name":"Tröster"}],"date_created":"2018-04-17T15:04:47Z","status":"public","volume":7,"_id":"2419","intvolume":" 7","issue":"5","page":"299-308","year":"2003","citation":{"chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x","bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.","ieee":"C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003."},"type":"journal_article"},{"title":"Instance-Specific Accelerators for Minimum Covering","publication_identifier":{"issn":["0920-8542"]},"department":[{"_id":"518"},{"_id":"78"}],"doi":"10.1023/a:1024443416592","date_updated":"2022-01-06T06:56:10Z","language":[{"iso":"eng"}],"user_id":"398","abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"extern":"1","status":"public","date_created":"2018-04-17T15:10:00Z","volume":26,"author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Kluwer Academic Publishers","publication":"Journal of Supercomputing","keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"issue":"2","intvolume":" 26","_id":"2420","type":"journal_article","year":"2003","citation":{"short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592","apa":"Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592."},"page":"109-129"},{"date_created":"2018-04-17T15:11:25Z","status":"public","volume":2778,"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","multi-context","FPGA"],"author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer","user_id":"24135","title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","abstract":[{"text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.","lang":"eng"}],"page":"151-160","type":"conference","year":"2003","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007."},"series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/b12007","_id":"2421","intvolume":" 2778","date_updated":"2022-01-06T06:56:13Z"},{"_id":"2422","date_updated":"2022-01-06T06:56:13Z","page":"174-180","citation":{"bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180."},"type":"conference","year":"2003","abstract":[{"lang":"eng","text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs."}],"user_id":"24135","title":"Co-simulation of a Hybrid Multi-Context Architecture","keyword":["Zippy","co-simulation"],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"CSREA Press","date_created":"2018-04-17T15:12:56Z","status":"public","publication_identifier":{"isbn":["1-932415-05-X"]}},{"publication_status":"published","publication_identifier":{"isbn":["0769518702"]},"status":"public","date_created":"2019-10-04T21:15:31Z","publisher":"IEEE CS Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proceedings Design, Automation and Test in Europe Conference (DATE)","department":[{"_id":"78"}],"title":"Online scheduling for block-partitioned reconfigurable devices","user_id":"398","extern":"1","citation":{"mla":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }","chicago":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622.","apa":"Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622","ama":"Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622","ieee":"H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295.","short":"H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295."},"year":"2003","type":"conference","page":"290-295","language":[{"iso":"eng"}],"doi":"10.1109/date.2003.1253622","date_updated":"2022-01-06T06:51:40Z","_id":"13612"},{"_id":"13613","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/ipdps.2003.1213329","language":[{"iso":"eng"}],"year":"2003","citation":{"ieee":"H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.","short":"H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.","bibtex":"@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }","mla":"Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.","ama":"Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329","apa":"Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329","chicago":"Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329."},"type":"conference","extern":"1","user_id":"398","title":"Fast online task placement on FPGAs: free space partitioning and 2D-hashing","publisher":"IEEE CS Press","author":[{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"last_name":"Steiger","full_name":"Steiger, Christoph","first_name":"Christoph"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Proceedings International Parallel and Distributed Processing Symposium","status":"public","date_created":"2019-10-04T21:17:07Z","publication_status":"published","publication_identifier":{"isbn":["0769519261"]}},{"user_id":"398","title":"Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations","extern":"1","status":"public","date_created":"2019-10-04T21:20:30Z","publisher":"CSREA Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"date_updated":"2022-01-06T06:51:40Z","_id":"13614","language":[{"iso":"eng"}],"year":"2003","type":"conference","citation":{"ieee":"H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.","short":"H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.","mla":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }","chicago":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.","apa":"Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.","ama":"Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287."},"page":"284-287"},{"place":"Berlin, Heidelberg","extern":"1","user_id":"398","title":"Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices","publication":"Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"first_name":"Christoph","full_name":"Steiger, Christoph","last_name":"Steiger"},{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","date_created":"2019-10-04T21:20:41Z","status":"public","publication_status":"published","publication_identifier":{"isbn":["9783540408222","9783540452348"],"issn":["0302-9743","1611-3349"]},"date_updated":"2022-01-06T06:51:40Z","_id":"13615","doi":"10.1007/978-3-540-45234-8_56","language":[{"iso":"eng"}],"page":"575-584","citation":{"short":"C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.","ieee":"C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584.","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.","apa":"Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. 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Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56","bibtex":"@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }","mla":"Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56."},"type":"conference","year":"2003"},{"user_id":"398","title":"Online scheduling and placement of real-time tasks to partially reconfigurable devices","status":"public","date_created":"2019-10-04T21:22:53Z","publication_identifier":{"isbn":["0769520448"]},"publication_status":"published","publisher":"IEEE CS Press","author":[{"first_name":"Christoph","full_name":"Steiger, Christoph","last_name":"Steiger"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"publication":"Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)","department":[{"_id":"78"}],"doi":"10.1109/real.2003.1253269","_id":"13617","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"citation":{"short":"C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.","ieee":"C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235.","ama":"Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269","apa":"Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). 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IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269.","bibtex":"@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }","mla":"Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269."},"type":"conference","year":"2003","page":"252-235"},{"doi":"10.1109/ISWC.2002.1167250","_id":"2423","date_updated":"2022-01-06T06:56:13Z","year":"2002","citation":{"mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250.","ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222."},"type":"conference","page":"215-222","user_id":"24135","title":"Reconfigurable Hardware in Wearable Computing Nodes","abstract":[{"text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.","lang":"eng"}],"status":"public","date_created":"2018-04-17T15:13:50Z","publication_identifier":{"isbn":["0-7695-1816-8"]},"publisher":"IEEE Computer Society","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["wearable computing"]},{"keyword":["partial reconfiguration"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","author":[{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","volume":2438,"date_created":"2018-04-17T15:14:39Z","status":"public","abstract":[{"text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ","lang":"eng"}],"title":"Partially Reconfigurable Cores for Xilinx Virtex","user_id":"24135","series_title":"Lecture Notes in Computer Science (LNCS)","page":"292-301","type":"conference","year":"2002","citation":{"short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5","apa":"Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5.","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5."},"_id":"2424","intvolume":" 2438","date_updated":"2022-01-06T06:56:13Z","doi":"10.1007/3-540-46117-5"},{"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society","date_created":"2018-04-17T15:15:44Z","status":"public","abstract":[{"lang":"eng","text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. "}],"title":"Custom Computing Machines for the Set Covering Problem","user_id":"24135","page":"163-172","year":"2002","citation":{"ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","apa":"Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671."},"type":"conference","date_updated":"2022-01-06T06:56:13Z","_id":"2425","doi":"10.1109/FPGA.2002.1106671"},{"intvolume":" 21","_id":"10651","date_updated":"2022-01-06T06:50:49Z","doi":"10.1023/a:1013627403946","issue":"2","page":"145-159","year":"2002","citation":{"chicago":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.","apa":"Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946","ama":"Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946","mla":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.","bibtex":"@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }","short":"M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159.","ieee":"M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002."},"type":"journal_article","language":[{"iso":"eng"}],"extern":"1","title":"A Framework for Run-time Reconfigurable Systems","user_id":"398","publication":"The Journal of Supercomputing","department":[{"_id":"78"}],"author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Kluwer Academic Publishers","volume":21,"date_created":"2019-07-10T11:13:11Z","status":"public"},{"_id":"13611","date_updated":"2022-01-06T06:51:40Z","year":"2002","type":"conference","citation":{"mla":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","bibtex":"@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }","ama":"Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.","apa":"Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.","chicago":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 24–30. CSREA Press, 2002.","ieee":"H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.","short":"H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30."},"page":"24-30","language":[{"iso":"eng"}],"extern":"1","title":"Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform","user_id":"398","publisher":"CSREA Press","author":[{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2019-10-04T21:13:46Z"},{"status":"public","date_created":"2018-04-17T15:39:17Z","author":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","keyword":["minimum covering","accelerator","funding-sundance"],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"user_id":"24135","title":"Instance-Specific Accelerators for Minimum Covering","abstract":[{"lang":"eng","text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. "}],"citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. 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Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91."},"year":"2001","type":"conference","page":"85-91","_id":"2428","date_updated":"2022-01-06T06:56:17Z"},{"doi":"10.1117/12.434376","intvolume":" 4525","_id":"2432","date_updated":"2022-01-06T06:56:17Z","year":"2001","citation":{"short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.","bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={10.1117/12.434376}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }"},"type":"conference","page":"135-146","series_title":"Proc. SPIE","user_id":"24135","title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","abstract":[{"text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.","lang":"eng"}],"status":"public","date_created":"2018-04-17T15:51:39Z","volume":4525,"author":[{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"last_name":"Tröster","full_name":"Tröster, Gerhard","first_name":"Gerhard"}],"department":[{"_id":"518"},{"_id":"78"}],"keyword":["benchmark"],"publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III"},{"user_id":"398","title":"Object-oriented domain specific compilers for programming FPGAs","extern":"1","date_created":"2019-07-10T11:47:42Z","status":"public","volume":9,"department":[{"_id":"78"}],"publication":"{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems","author":[{"last_name":"Mencer","full_name":"Mencer, Oskar","first_name":"Oskar"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Morf","full_name":"Morf, Martin","first_name":"Martin"},{"full_name":"J. Flynn, Michael","first_name":"Michael","last_name":"J. Flynn"}],"issue":"1","doi":"10.1109/92.920835","_id":"10713","intvolume":" 9","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"page":"205-210","citation":{"mla":"Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.","bibtex":"@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }","chicago":"Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. 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Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210."},"year":"2001","type":"journal_article"},{"date_updated":"2022-01-06T06:51:36Z","_id":"13463","type":"misc","citation":{"chicago":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ama":"Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.","apa":"Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).","mla":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","bibtex":"@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }","short":"R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ieee":"R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001."},"year":"2001","language":[{"iso":"eng"}],"extern":"1","title":"Dynamically Reconfigurable Processors","user_id":"398","department":[{"_id":"78"}],"author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)","date_created":"2019-09-30T09:27:00Z","status":"public"},{"status":"public","date_created":"2019-01-08T09:45:03Z","volume":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Computer","user_id":"398","extern":"1","citation":{"ama":"Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322","apa":"Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322","chicago":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.","mla":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.","bibtex":"@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={10.1109/2.839322}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }","short":"M. Platzner, Computer 33 (2000) 58–60.","ieee":"M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000."},"type":"journal_article","year":"2000","page":"58-60","issue":"4","_id":"6507","intvolume":" 33","publication_status":"published","publication_identifier":{"issn":["0018-9162"]},"department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"title":"Reconfigurable accelerators for combinatorial problems","language":[{"iso":"eng"}],"doi":"10.1109/2.839322","date_updated":"2022-01-06T07:03:08Z"},{"date_created":"2019-07-10T09:22:58Z","status":"public","volume":147,"publication":"IEE Proceedings -- Computers & Digital Techniques","department":[{"_id":"78"}],"author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IET","user_id":"398","title":"Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems","extern":"1","language":[{"iso":"eng"}],"page":"159-165","type":"journal_article","citation":{"chicago":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.","ama":"Eisenring M, Platzner M. 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Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques 147 (2000) 159–165.","ieee":"M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital Techniques, vol. 147, pp. 159–165, 2000."},"year":"2000","doi":"10.1049/ip-cdt:20000496","intvolume":" 147","_id":"10606","date_updated":"2022-01-06T06:50:47Z"}]