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In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.","apa":"Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).","chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006."},"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","_id":"13625","status":"public","date_created":"2019-10-04T21:51:29Z","author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","department":[{"_id":"78"}],"title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices","user_id":"398"},{"user_id":"398","title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","status":"public","date_created":"2019-10-04T21:53:12Z","author":[{"last_name":"Danne","full_name":"Danne, Klaus","first_name":"Klaus"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE CS Press","department":[{"_id":"78"}],"publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","_id":"13626","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"citation":{"short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006.","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006."},"type":"conference","year":"2006"},{"year":"2005","type":"conference","citation":{"ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. 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IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69."},"page":"213-218","_id":"2411","date_updated":"2022-01-06T06:56:07Z","doi":"10.1109/ASAP.2005.69","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE Computer Society","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy"],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","status":"public","date_created":"2018-04-17T14:34:03Z","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. 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In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.","lang":"eng"}],"citation":{"short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. 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Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","ieee":"K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","apa":"Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720","ama":"Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. 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Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005."}},{"doi":"10.1109/fpl.2005.1515787","date_updated":"2022-01-06T06:51:40Z","_id":"13623","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","mla":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787.","ama":"Danne K, Platzner M. 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For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. "}],"status":"public","date_created":"2018-04-17T14:45:57Z","publisher":"CSREA Press","author":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"keyword":["hardware virtualization"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. 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Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835.","short":"H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835."},"page":"831-835","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }","mla":"Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","ama":"Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.","apa":"Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","chicago":"Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.","ieee":"H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.","short":"H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004."},"year":"2004","type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13619","date_created":"2019-10-04T21:31:54Z","status":"public","publication":"Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"author":[{"last_name":"Walder","full_name":"Walder, Hebert","first_name":"Hebert"},{"last_name":"Nobs","full_name":"Nobs, Samuel","first_name":"Samuel"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"CSREA Press","user_id":"398","title":"XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems","extern":"1"},{"date_created":"2019-10-04T21:32:57Z","status":"public","publication_identifier":{"isbn":["0769522300"]},"publication_status":"published","department":[{"_id":"78"}],"publication":"Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":[{"full_name":"Dyer, Matthias","first_name":"Matthias","last_name":"Dyer"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE CS Press","user_id":"398","title":"Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine","language":[{"iso":"eng"}],"year":"2004","citation":{"ieee":"M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.","short":"M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.","mla":"Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31.","bibtex":"@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }","apa":"Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31","ama":"Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31","chicago":"Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31."},"type":"conference","doi":"10.1109/fccm.2004.31","date_updated":"2022-01-06T06:51:40Z","_id":"13620"},{"abstract":[{"text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ","lang":"eng"}],"title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","user_id":"24135","publisher":"IEEE Computer Society","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"status":"public","date_created":"2018-04-17T15:03:34Z","_id":"2418","date_updated":"2022-01-06T06:56:09Z","doi":"10.1109/FPT.2003.1275755","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259.","chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755","apa":"Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }"},"type":"conference","year":"2003","page":"252-259"},{"user_id":"398","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM."}],"extern":"1","status":"public","date_created":"2018-04-17T15:04:47Z","volume":7,"publisher":"Springer","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"first_name":"Gerhard","full_name":"Tröster, Gerhard","last_name":"Tröster"}],"publication":"Personal and Ubiquitous Computing","issue":"5","_id":"2419","intvolume":" 7","year":"2003","citation":{"bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x","ieee":"C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308."},"type":"journal_article","page":"299-308","title":"The Case for Reconfigurable Hardware in Wearable Computing","department":[{"_id":"518"},{"_id":"78"}],"doi":"10.1007/s00779-003-0243-x","date_updated":"2022-01-06T06:56:09Z","language":[{"iso":"eng"}]},{"page":"109-129","citation":{"ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.","short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.","apa":"Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592"},"type":"journal_article","year":"2003","_id":"2420","intvolume":" 26","issue":"2","publication":"Journal of Supercomputing","keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Kluwer Academic Publishers","date_created":"2018-04-17T15:10:00Z","status":"public","volume":26,"abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"extern":"1","user_id":"398","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:56:10Z","doi":"10.1023/a:1024443416592","department":[{"_id":"518"},{"_id":"78"}],"publication_identifier":{"issn":["0920-8542"]},"title":"Instance-Specific Accelerators for Minimum Covering"},{"doi":"10.1007/b12007","date_updated":"2022-01-06T06:56:13Z","_id":"2421","intvolume":" 2778","page":"151-160","year":"2003","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007."},"type":"conference","series_title":"Lecture Notes in Computer Science (LNCS)","user_id":"24135","title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","abstract":[{"text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.","lang":"eng"}],"date_created":"2018-04-17T15:11:25Z","status":"public","volume":2778,"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["Zippy","multi-context","FPGA"],"author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer"},{"title":"Co-simulation of a Hybrid Multi-Context Architecture","user_id":"24135","abstract":[{"lang":"eng","text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs."}],"publication_identifier":{"isbn":["1-932415-05-X"]},"date_created":"2018-04-17T15:12:56Z","status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","keyword":["Zippy","co-simulation"],"department":[{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","date_updated":"2022-01-06T06:56:13Z","_id":"2422","page":"174-180","citation":{"short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80."},"type":"conference","year":"2003"},{"language":[{"iso":"eng"}],"page":"290-295","citation":{"ama":"Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622","apa":"Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622","chicago":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622.","mla":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }","short":"H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295.","ieee":"H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295."},"year":"2003","type":"conference","doi":"10.1109/date.2003.1253622","date_updated":"2022-01-06T06:51:40Z","_id":"13612","date_created":"2019-10-04T21:15:31Z","status":"public","publication_identifier":{"isbn":["0769518702"]},"publication_status":"published","department":[{"_id":"78"}],"publication":"Proceedings Design, Automation and Test in Europe Conference (DATE)","publisher":"IEEE CS Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"user_id":"398","title":"Online scheduling for block-partitioned reconfigurable devices","extern":"1"},{"_id":"13613","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/ipdps.2003.1213329","language":[{"iso":"eng"}],"year":"2003","type":"conference","citation":{"ama":"Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329","apa":"Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329","chicago":"Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329.","bibtex":"@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }","mla":"Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.","short":"H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.","ieee":"H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003."},"extern":"1","user_id":"398","title":"Fast online task placement on FPGAs: free space partitioning and 2D-hashing","department":[{"_id":"78"}],"publication":"Proceedings International Parallel and Distributed Processing Symposium","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"last_name":"Steiger","full_name":"Steiger, Christoph","first_name":"Christoph"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE CS Press","date_created":"2019-10-04T21:17:07Z","status":"public","publication_identifier":{"isbn":["0769519261"]},"publication_status":"published"},{"_id":"13614","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"page":"284-287","year":"2003","citation":{"mla":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }","chicago":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.","apa":"Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.","ama":"Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.","ieee":"H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.","short":"H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287."},"type":"conference","user_id":"398","title":"Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations","extern":"1","date_created":"2019-10-04T21:20:30Z","status":"public","publication":"Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"author":[{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"CSREA Press"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13615","doi":"10.1007/978-3-540-45234-8_56","language":[{"iso":"eng"}],"citation":{"ama":"Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56","apa":"Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.","bibtex":"@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }","mla":"Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56.","short":"C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.","ieee":"C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584."},"type":"conference","year":"2003","page":"575-584","place":"Berlin, Heidelberg","extern":"1","user_id":"398","title":"Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices","publisher":"Springer","author":[{"last_name":"Steiger","full_name":"Steiger, Christoph","first_name":"Christoph"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)","status":"public","date_created":"2019-10-04T21:20:41Z","publication_status":"published","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540408222","9783540452348"]}},{"user_id":"398","title":"Online scheduling and placement of real-time tasks to partially reconfigurable devices","status":"public","date_created":"2019-10-04T21:22:53Z","publication_identifier":{"isbn":["0769520448"]},"publication_status":"published","author":[{"last_name":"Steiger","full_name":"Steiger, Christoph","first_name":"Christoph"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE CS Press","publication":"Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)","department":[{"_id":"78"}],"doi":"10.1109/real.2003.1253269","_id":"13617","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"citation":{"apa":"Steiger, C., Walder, H., Platzner, M., & Thiele, L. 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IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269.","bibtex":"@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }","mla":"Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269.","short":"C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.","ieee":"C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235."},"year":"2003","type":"conference","page":"252-235"},{"doi":"10.1109/ISWC.2002.1167250","_id":"2423","date_updated":"2022-01-06T06:56:13Z","page":"215-222","year":"2002","type":"conference","citation":{"bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250","ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222."},"user_id":"24135","title":"Reconfigurable Hardware in Wearable Computing Nodes","abstract":[{"text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.","lang":"eng"}],"date_created":"2018-04-17T15:13:50Z","status":"public","publication_identifier":{"isbn":["0-7695-1816-8"]},"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. 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With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ","lang":"eng"}],"title":"Partially Reconfigurable Cores for Xilinx Virtex","user_id":"24135","author":[{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["partial reconfiguration"],"volume":2438,"status":"public","date_created":"2018-04-17T15:14:39Z","intvolume":" 2438","_id":"2424","date_updated":"2022-01-06T06:56:13Z","doi":"10.1007/3-540-46117-5","series_title":"Lecture Notes in Computer Science (LNCS)","year":"2002","type":"conference","citation":{"chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5","apa":"Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.","short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301."},"page":"292-301"},{"user_id":"24135","title":"Custom Computing Machines for the Set Covering Problem","abstract":[{"text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ","lang":"eng"}],"date_created":"2018-04-17T15:15:44Z","status":"public","department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"doi":"10.1109/FPGA.2002.1106671","_id":"2425","date_updated":"2022-01-06T06:56:13Z","page":"163-172","type":"conference","year":"2002","citation":{"bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.","apa":"Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172."}},{"language":[{"iso":"eng"}],"page":"145-159","citation":{"mla":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.","bibtex":"@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }","ama":"Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946","apa":"Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946","chicago":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.","ieee":"M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.","short":"M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159."},"year":"2002","type":"journal_article","issue":"2","doi":"10.1023/a:1013627403946","_id":"10651","date_updated":"2022-01-06T06:50:49Z","intvolume":" 21","date_created":"2019-07-10T11:13:11Z","status":"public","volume":21,"publication":"The Journal of Supercomputing","department":[{"_id":"78"}],"publisher":"Kluwer Academic Publishers","author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"398","title":"A Framework for Run-time Reconfigurable Systems","extern":"1"},{"extern":"1","title":"Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform","user_id":"398","author":[{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","publication":"Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T21:13:46Z","_id":"13611","date_updated":"2022-01-06T06:51:40Z","year":"2002","type":"conference","citation":{"apa":"Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.","ama":"Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.","chicago":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 24–30. CSREA Press, 2002.","bibtex":"@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }","mla":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","short":"H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","ieee":"H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30."},"page":"24-30","language":[{"iso":"eng"}]},{"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["minimum covering","accelerator","funding-sundance"],"publisher":"CSREA Press","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2018-04-17T15:39:17Z","status":"public","abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}],"title":"Instance-Specific Accelerators for Minimum Covering","user_id":"24135","page":"85-91","citation":{"bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. 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This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.","lang":"eng"}],"page":"135-146","citation":{"short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. 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