[{"project":[{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"publication_status":"published","publication_identifier":{"isbn":["978-1-4503-7127-8"]},"department":[{"_id":"78"}],"title":"Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold","place":"New York, NY, United States","language":[{"iso":"eng"}],"doi":"10.1145/3377929.3389968","date_updated":"2022-01-06T06:52:49Z","status":"public","date_created":"2020-04-02T10:07:10Z","publisher":"Association for Computing Machinery (ACM)","author":[{"first_name":"Tim","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","last_name":"Hansmeier","id":"49992"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion","user_id":"477","citation":{"apa":"Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126). New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968","ama":"Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York, NY, United States: Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968","chicago":"Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 125–26. New York, NY, United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3389968.","mla":"Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125–26, doi:10.1145/3377929.3389968.","bibtex":"@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}, DOI={10.1145/3377929.3389968}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126} }","short":"T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.","ieee":"T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126."},"year":"2020","type":"conference","page":"125-126","_id":"16363","conference":{"location":"Cancún, Mexico","name":"The Genetic and Evolutionary Computation Conference (GECCO 2020)","start_date":"2020-07-08","end_date":"2020-07-12"}},{"_id":"20838","date_updated":"2023-01-03T22:07:12Z","doi":"10.1109/ipdpsw50202.2020.00012","citation":{"short":"A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020.","ieee":"A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.","chicago":"Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.","apa":"Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012","ama":"Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012","bibtex":"@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012}, booktitle={2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }","mla":"Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012."},"type":"conference","year":"2020","language":[{"iso":"eng"}],"title":"MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes","user_id":"398","publication":"2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","department":[{"_id":"78"}],"author":[{"full_name":"Lösch, Achim","first_name":"Achim","last_name":"Lösch"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication_status":"published","publication_identifier":{"isbn":["9781728174457"]},"date_created":"2020-12-23T09:07:11Z","status":"public"},{"_id":"21433","date_updated":"2023-07-09T17:12:52Z","type":"mastersthesis","citation":{"bibtex":"@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020} }","mla":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture. 2020.","chicago":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020.","ama":"Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture.; 2020.","apa":"Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture.","ieee":"F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.","short":"F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020."},"year":"2020","supervisor":[{"id":"60323","last_name":"Lienen","full_name":"Lienen, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"language":[{"iso":"eng"}],"title":"Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture","user_id":"398","abstract":[{"text":"Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.","lang":"eng"}],"status":"public","date_created":"2021-03-10T07:09:14Z","project":[{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"}],"author":[{"first_name":"Felix P.","full_name":"Jentzsch, Felix P.","last_name":"Jentzsch"}],"department":[{"_id":"78"}]},{"date_created":"2018-07-20T14:08:49Z","status":"public","volume":99,"publication":"Microelectronics Reliability","keyword":["Approximate Computing","Framework","Pareto Front","Accuracy"],"publisher":"Elsevier","author":[{"last_name":"Witschen","id":"49051","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"last_name":"Awais","id":"64665","first_name":"Muhammad","full_name":"Awais, Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"49051","abstract":[{"text":"Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.","lang":"eng"}],"page":"277-290","type":"journal_article","year":"2019","citation":{"ieee":"L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.","short":"L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability 99 (2019) 277–290.","bibtex":"@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }","mla":"Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019): 277–90. https://doi.org/10.1016/j.microrel.2019.04.003.","apa":"Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003","ama":"Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003"},"intvolume":" 99","_id":"3585","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication_status":"published","publication_identifier":{"issn":["0026-2714"]},"department":[{"_id":"78"}],"title":"CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation","language":[{"iso":"eng"}],"doi":"10.1016/j.microrel.2019.04.003","date_updated":"2022-01-06T06:59:25Z"},{"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"accepted","department":[{"_id":"78"}],"title":"Jump Search: A Fast Technique for the Synthesis of Approximate Circuits","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:52:57Z","date_created":"2020-04-25T08:02:07Z","has_accepted_license":"1","status":"public","file":[{"access_level":"closed","date_created":"2020-04-25T08:00:35Z","file_name":"AxC19_paper_3.pdf","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2020-04-25T08:00:35Z","file_id":"16854","creator":"witschen","file_size":152806}],"keyword":["Approximate computing","parameter selection","search space exploration","verification","circuit synthesis"],"file_date_updated":"2020-04-25T08:00:35Z","publication":"Fourth Workshop on Approximate Computing (AxC 2019)","author":[{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","id":"49051","last_name":"Witschen"},{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"first_name":"Matthias","full_name":"Artmann, Matthias","last_name":"Artmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"49051","ddc":["006"],"abstract":[{"text":"State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.","lang":"eng"}],"page":"2","citation":{"bibtex":"@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }","mla":"Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).","chicago":"Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.","apa":"Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).","ama":"Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).","ieee":"L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .","short":"L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.)."},"type":"preprint","year":"2019","_id":"16853"},{"department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["9781450362528"]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"place":"New York, NY, USA","title":"Jump Search: A Fast Technique for the Synthesis of Approximate Circuits","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:45Z","doi":"10.1145/3299874.3317998","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"last_name":"Ghasemzadeh Mohammadi","id":"61186","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"first_name":"Matthias","full_name":"Artmann, Matthias","last_name":"Artmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"ACM","publication":"Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19","keyword":["Approximate computing","design automation","parameter selection","circuit synthesis"],"status":"public","date_created":"2019-07-08T15:13:10Z","abstract":[{"text":"State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution.\r\n\r\nIn this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.","lang":"eng"}],"user_id":"49051","year":"2019","citation":{"bibtex":"@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, DOI={10.1145/3299874.3317998}, booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }","mla":"Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.","chicago":"Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.","apa":"Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998","ama":"Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM; 2019. doi:10.1145/3299874.3317998","ieee":"L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.","short":"L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY, USA, 2019."},"type":"conference","_id":"10577","conference":{"start_date":"2019-05-09","name":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","location":"Tysons Corner, VA, USA","end_date":"2019-05-11"}},{"user_id":"398","abstract":[{"lang":"eng","text":"Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels."}],"date_created":"2019-07-12T13:13:55Z","status":"public","volume":123,"keyword":["High density electromyography","FPGA acceleration","Medical signal processing","Pattern recognition","Prosthetics"],"publication":"Journal of Parallel and Distributed Computing","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Thombansen","full_name":"Thombansen, Georg","first_name":"Georg"},{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"full_name":"Kraus, Florian","first_name":"Florian","last_name":"Kraus"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Elsevier","intvolume":" 123","_id":"11950","page":"77-89","year":"2019","type":"journal_article","citation":{"ieee":"A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.","short":"A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner, Journal of Parallel and Distributed Computing 123 (2019) 77–89.","bibtex":"@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based acceleration of robust high density myoelectric signal processing}, volume={123}, DOI={10.1016/j.jpdc.2018.07.004}, journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier}, author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen, Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89} }","mla":"Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing, vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.","chicago":"Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen, Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing 123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.","apa":"Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., & Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing, 123, 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004","ama":"Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004"},"title":"Zynq-based acceleration of robust high density myoelectric signal processing","publication_status":"published","publication_identifier":{"issn":["0743-7315"]},"department":[{"_id":"78"}],"doi":"10.1016/j.jpdc.2018.07.004","date_updated":"2022-01-06T06:51:13Z","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"doi":"10.1007/s11265-018-1435-y","date_updated":"2022-01-06T06:51:27Z","publication_status":"published","publication_identifier":{"issn":["1939-8018","1939-8115"]},"department":[{"_id":"78"}],"title":"An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology","page":"1259 - 1272","citation":{"apa":"Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems, 91(11), 1259–1272. https://doi.org/10.1007/s11265-018-1435-y","ama":"Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y","chicago":"Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019): 1259–72. https://doi.org/10.1007/s11265-018-1435-y.","bibtex":"@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}, volume={91}, DOI={10.1007/s11265-018-1435-y}, number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019}, pages={1259–1272} }","mla":"Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems, vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.","short":"T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing Systems 91 (2019) 1259–1272.","ieee":"T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019."},"year":"2019","type":"journal_article","issue":"11","_id":"12967","intvolume":" 91","volume":91,"date_created":"2019-08-26T13:41:57Z","status":"public","publication":"Journal of Signal Processing Systems","author":[{"last_name":"Hansmeier","id":"49992","first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Pantho, Md Jubaer Hossain","first_name":"Md Jubaer Hossain","last_name":"Pantho"},{"first_name":"David","full_name":"Andrews, David","last_name":"Andrews"}],"user_id":"49992","abstract":[{"text":"Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.","lang":"eng"}]},{"user_id":"398","title":"Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor","publication":"World Congress on Nature and Biologically Inspired Computing (NaBIC)","department":[{"_id":"78"}],"author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","date_created":"2019-12-30T13:55:49Z","status":"public","date_updated":"2022-01-06T06:52:25Z","_id":"15422","series_title":"Advances in Nature and Biologically Inspired Computing","language":[{"iso":"eng"}],"type":"conference","year":"2019","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and Biologically Inspired Computing}, title={Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances in Nature and Biologically Inspired Computing} }","mla":"Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.","ama":"Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In: World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer; 2019.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In World Congress on Nature and Biologically Inspired Computing (NaBIC). Springer.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer, 2019.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.","short":"N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019."}},{"title":"Incremental learning with Support Vector Machine on embedded platforms","user_id":"61186","date_created":"2020-02-11T16:43:38Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Kumar Jeyakumar","first_name":"Shankar","full_name":"Kumar Jeyakumar, Shankar"}],"_id":"15883","date_updated":"2022-01-06T06:52:39Z","type":"mastersthesis","year":"2019","citation":{"ama":"Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded Platforms.; 2019.","apa":"Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine on embedded platforms.","chicago":"Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms, 2019.","bibtex":"@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019} }","mla":"Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms. 2019.","short":"S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded Platforms, 2019.","ieee":"S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019."},"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"}]},{"date_updated":"2022-01-06T06:52:41Z","_id":"15920","citation":{"mla":"Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.","bibtex":"@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati, Monica}, year={2019} }","chicago":"Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.","apa":"Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn.","ama":"Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn; 2019.","ieee":"M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.","short":"M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking, Universität Paderborn, 2019."},"year":"2019","type":"mastersthesis","supervisor":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille","id":"209","last_name":"Hellebrand"}],"language":[{"iso":"eng"}],"title":"A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking","user_id":"477","abstract":[{"lang":"eng","text":"Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs.\r\nThis master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis."}],"status":"public","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"date_created":"2020-02-17T12:03:40Z","author":[{"last_name":"Keerthipati","first_name":"Monica","full_name":"Keerthipati, Monica"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}]},{"date_created":"2019-11-06T12:06:09Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Sabu, Nithin S.","first_name":"Nithin S.","last_name":"Sabu"}],"user_id":"3118","title":"FPGA Acceleration of String Search Techniques in Huge Data Sets","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Böttcher","full_name":"Böttcher, Stefan","first_name":"Stefan"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"}],"type":"mastersthesis","year":"2019","citation":{"short":"N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets, Paderborn University, 2019.","ieee":"N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.","ama":"Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University; 2019.","apa":"Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University.","chicago":"Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.","bibtex":"@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019} }","mla":"Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019."},"_id":"14831","date_updated":"2022-01-06T06:52:07Z"},{"date_created":"2020-02-20T14:47:12Z","status":"public","department":[{"_id":"78"}],"author":[{"full_name":"Mehta, Jinay","first_name":"Jinay","last_name":"Mehta"}],"user_id":"398","title":"Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"}],"language":[{"iso":"eng"}],"citation":{"ieee":"J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip. 2019.","short":"J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recongurable System-on-Chip, 2019.","mla":"Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recongurable System-on-Chip. 2019.","bibtex":"@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip}, author={Mehta, Jinay}, year={2019} }","chicago":"Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recongurable System-on-Chip, 2019.","apa":"Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip.","ama":"Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recongurable System-on-Chip.; 2019."},"type":"mastersthesis","year":"2019","_id":"15946","date_updated":"2022-01-06T06:52:41Z"},{"_id":"14546","date_updated":"2022-01-06T06:52:02Z","citation":{"ieee":"T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.","short":"T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.","bibtex":"@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }","mla":"Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.","chicago":"Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.","ama":"Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.","apa":"Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn."},"year":"2019","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"title":"Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers","user_id":"477","status":"public","date_created":"2019-11-05T14:32:46Z","project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901","_id":"1"}],"author":[{"first_name":"Tim","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","last_name":"Hansmeier","id":"49992"}],"publisher":"Universität Paderborn","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}]},{"citation":{"short":"Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.","ieee":"Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.","ama":"Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027","apa":"Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw.2019.00027","chicago":"Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.” In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027.","mla":"Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.","bibtex":"@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027}, booktitle={2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner, Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }"},"year":"2019","type":"conference","language":[{"iso":"eng"}],"_id":"31067","date_updated":"2022-05-05T07:43:29Z","doi":"10.1109/ipdpsw.2019.00027","department":[{"_id":"78"}],"publication":"2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","author":[{"full_name":"Guettatfi, Zakarya","first_name":"Zakarya","last_name":"Guettatfi"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Kermia, Omar","first_name":"Omar","last_name":"Kermia"},{"last_name":"Khouas","full_name":"Khouas, Abdelhakim","first_name":"Abdelhakim"}],"publisher":"IEEE","publication_status":"published","date_created":"2022-05-05T07:42:26Z","status":"public","title":"An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware","user_id":"398"},{"place":"Cham","title":"Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan","department":[{"_id":"78"}],"publication_identifier":{"isbn":["978-3-030-17227-5"]},"publication_status":"published","editor":[{"full_name":"Hochberger, Christian","first_name":"Christian","last_name":"Hochberger"},{"last_name":"Nelson","full_name":"Nelson, Brent","first_name":"Brent"},{"last_name":"Koch","first_name":"Andreas","full_name":"Koch, Andreas"},{"last_name":"Woods","first_name":"Roger","full_name":"Woods, Roger"},{"last_name":"Diniz","first_name":"Pedro","full_name":"Diniz, Pedro"}],"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"}],"date_updated":"2023-05-15T08:13:37Z","doi":"10.1007/978-3-030-17227-5_10","oa":"1","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"abstract":[{"text":"Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.","lang":"eng"}],"ddc":["000"],"user_id":"72764","file_date_updated":"2023-05-11T09:12:33Z","publication":"Applied Reconfigurable Computing","author":[{"first_name":"Qazi Arbab","orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","id":"72764"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer International Publishing","file":[{"date_created":"2023-05-11T09:12:33Z","file_name":"978-3-030-17227-5_10.pdf","access_level":"closed","file_size":661354,"creator":"qazi","file_id":"44749","content_type":"application/pdf","date_updated":"2023-05-11T09:12:33Z","success":1,"relation":"main_file"}],"volume":11444,"date_created":"2019-05-22T07:36:05Z","has_accepted_license":"1","status":"public","conference":{"location":"Darmstadt, Germany","name":"15th International Symposium on Applied Reconfigurable Computing (ARC 2019)","start_date":"2019-04-09","end_date":"2019-04-11"},"intvolume":" 11444","_id":"9913","main_file_link":[{"open_access":"1"}],"page":"127-136","type":"conference","citation":{"ieee":"Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.","short":"Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch, R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International Publishing, Cham, 2019, pp. 127–136.","mla":"Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36, doi:10.1007/978-3-030-17227-5_10.","bibtex":"@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10}, booktitle={Applied Reconfigurable Computing}, publisher={Springer International Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in Computer Science} }","ama":"Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10","apa":"Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson, A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing (Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10","chicago":"Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10."},"year":"2019"},{"_id":"15874","supervisor":[{"full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille","id":"209","last_name":"Hellebrand"}],"type":"mastersthesis","citation":{"ieee":"C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.","short":"C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with ReconOS, Universität Paderborn, n.d.","bibtex":"@book{Lienen, title={Implementing a Real-time System on a Platform FPGA operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian} }","mla":"Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn.","chicago":"Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn, n.d.","ama":"Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn","apa":"Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn."},"year":"2019","user_id":"60323","ddc":["004"],"has_accepted_license":"1","status":"public","date_created":"2020-02-11T10:22:06Z","file":[{"date_updated":"2021-02-13T16:46:58Z","content_type":"application/pdf","relation":"main_file","file_size":5920668,"creator":"clienen","file_id":"17351","access_level":"open_access","file_name":"thesis_main.pdf","date_created":"2020-07-01T11:46:49Z"}],"author":[{"id":"60323","last_name":"Lienen","full_name":"Lienen, Christian","first_name":"Christian"}],"publisher":"Universität Paderborn","file_date_updated":"2021-02-13T16:46:58Z","oa":"1","date_updated":"2023-07-31T11:58:50Z","language":[{"iso":"eng"}],"title":"Implementing a Real-time System on a Platform FPGA operated with ReconOS","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"},{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"}],"publication_status":"submitted","department":[{"_id":"78"}]},{"language":[{"iso":"ger"}],"date_updated":"2023-09-26T11:45:57Z","doi":"10.1007/s00287-019-01187-w","oa":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"issn":["0170-6012","1432-122X"]},"publication_status":"published","title":"FPGAs im Rechenzentrum","citation":{"bibtex":"@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }","mla":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w.","chicago":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.","apa":"Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w","ama":"Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w","ieee":"M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.","short":"M. Platzner, C. Plessl, Informatik Spektrum (2019)."},"type":"journal_article","year":"2019","_id":"12871","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","file_date_updated":"2019-07-22T12:45:02Z","publication":"Informatik Spektrum","file":[{"date_created":"2019-07-22T12:45:02Z","file_name":"plessl19_informatik_spektrum.pdf","access_level":"open_access","file_id":"12872","creator":"plessl","file_size":248360,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-07-22T12:45:02Z"}],"has_accepted_license":"1","status":"public","date_created":"2019-07-22T12:42:44Z","ddc":["004"],"user_id":"15278"},{"title":"Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip","user_id":"74287","status":"public","date_created":"2024-03-11T15:57:13Z","author":[{"last_name":"Mehta","full_name":"Mehta, Jinay D","first_name":"Jinay D"}],"department":[{"_id":"78"}],"_id":"52478","date_updated":"2024-03-11T15:57:39Z","citation":{"chicago":"Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip, 2019.","ama":"Mehta JD. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip.; 2019.","apa":"Mehta, J. D. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip.","bibtex":"@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D}, year={2019} }","mla":"Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip. 2019.","short":"J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip, 2019.","ieee":"J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. 2019."},"type":"mastersthesis","year":"2019","supervisor":[{"first_name":"Lennart","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing","id":"74287"}],"language":[{"iso":"eng"}]},{"department":[{"_id":"78"}],"publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783319776095","9783319776101"]},"publication_status":"published","project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}],"place":"Cham","title":"Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes","series_title":"Lecture Notes in Computer Science","date_updated":"2022-01-06T06:59:13Z","doi":"10.1007/978-3-319-77610-1_6","file_date_updated":"2018-06-26T13:58:28Z","publication":"Proceedings of the International Conference on Architecture of Computing Systems (ARCS)","author":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"last_name":"Wiens","first_name":"Alex","full_name":"Wiens, Alex"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer International Publishing","file":[{"file_size":1114026,"creator":"aloesch","file_id":"3363","content_type":"application/pdf","date_updated":"2018-06-26T13:58:28Z","success":1,"relation":"main_file","date_created":"2018-06-26T13:58:28Z","file_name":"loesch2017_arcs.pdf","access_level":"closed"}],"volume":10793,"date_created":"2018-06-26T13:47:52Z","has_accepted_license":"1","status":"public","abstract":[{"text":"Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node.","lang":"eng"}],"ddc":["040"],"user_id":"477","page":"73-84","year":"2018","citation":{"ieee":"A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes,” in Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793, pp. 73–84.","short":"A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference on Architecture of Computing Systems (ARCS), Springer International Publishing, Cham, 2018, pp. 73–84.","mla":"Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.” Proceedings of the International Conference on Architecture of Computing Systems (ARCS), vol. 10793, Springer International Publishing, 2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.","bibtex":"@inproceedings{Lösch_Wiens_Platzner_2018, place={Cham}, series={Lecture Notes in Computer Science}, title={Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}, volume={10793}, DOI={10.1007/978-3-319-77610-1_6}, booktitle={Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}, publisher={Springer International Publishing}, author={Lösch, Achim and Wiens, Alex and Platzner, Marco}, year={2018}, pages={73–84}, collection={Lecture Notes in Computer Science} }","apa":"Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In Proceedings of the International Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6","ama":"Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In: Proceedings of the International Conference on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6","chicago":"Lösch, Achim, Alex Wiens, and Marco Platzner. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.” In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 10793:73–84. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-77610-1_6."},"type":"conference","_id":"3362","intvolume":" 10793"},{"publisher":"Universität Paderborn","author":[{"full_name":"Schnuer, Jan-Philip","first_name":"Jan-Philip","last_name":"Schnuer"}],"department":[{"_id":"78"}],"status":"public","date_created":"2018-06-26T14:10:18Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"user_id":"477","title":"Static Scheduling Algorithms for Heterogeneous Compute Nodes","supervisor":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","citation":{"ieee":"J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.","short":"J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes, Universität Paderborn, 2018.","mla":"Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.","bibtex":"@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }","chicago":"Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.","apa":"Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn.","ama":"Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn; 2018."},"year":"2018","date_updated":"2022-01-06T06:59:13Z","_id":"3365"},{"department":[{"_id":"78"}],"publisher":"Universität Paderborn","author":[{"last_name":"Croce","full_name":"Croce, Marcel","first_name":"Marcel"}],"project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_created":"2018-06-26T14:12:00Z","status":"public","title":"Evaluation of OpenCL-based Compilation for FPGAs","user_id":"477","year":"2018","type":"bachelorsthesis","citation":{"short":"M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn, 2018.","ieee":"M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn, 2018.","chicago":"Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018.","apa":"Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn.","ama":"Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn; 2018.","mla":"Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018.","bibtex":"@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }"},"supervisor":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}],"_id":"3366","date_updated":"2022-01-06T06:59:13Z"},{"doi":"10.1007/978-3-319-78890-6_13","date_updated":"2022-01-06T06:59:13Z","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","title":"An FPGA/HMC-Based Accelerator for Resolution Proof Checking","publication_status":"published","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783319788890","9783319788906"]},"project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"conference":{"end_date":"2018-05-04","name":"ARC: International Symposium on Applied Reconfigurable Computing","start_date":"2018-05-02","location":"Santorini, Greece"},"intvolume":" 10824","_id":"3373","page":"153-165","year":"2018","type":"conference","citation":{"short":"T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2018, pp. 153–165.","ieee":"T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824, pp. 153–165.","chicago":"Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.","apa":"Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini, Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13","ama":"Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13","mla":"Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, vol. 10824, Springer International Publishing, 2018, pp. 153–65, doi:10.1007/978-3-319-78890-6_13.","bibtex":"@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking}, volume={10824}, DOI={10.1007/978-3-319-78890-6_13}, booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture Notes in Computer Science} }"},"ddc":["000"],"user_id":"3118","abstract":[{"lang":"eng","text":"Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory."}],"volume":10824,"date_created":"2018-06-27T09:30:24Z","status":"public","has_accepted_license":"1","publication":"ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications","file_date_updated":"2018-11-02T13:55:07Z","author":[{"last_name":"Hansmeier","id":"49992","first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Andrews","first_name":"David","full_name":"Andrews, David"}],"publisher":"Springer International Publishing","file":[{"access_level":"closed","date_created":"2018-11-02T13:55:07Z","file_name":"AnFPGAHMC-BasedAcceleratorForR.pdf","content_type":"application/pdf","date_updated":"2018-11-02T13:55:07Z","success":1,"relation":"main_file","file_size":612367,"creator":"ups","file_id":"5257"}]},{"page":"6","year":"2018","type":"preprint","citation":{"short":"L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Third Workshop on Approximate Computing (AxC 2018) (n.d.).","ieee":"L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). .","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018), n.d.","ama":"Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).","apa":"Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).","mla":"Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).","bibtex":"@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco} }"},"_id":"3586","date_created":"2018-07-20T14:10:46Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-07-20T14:13:31Z","keyword":["Approximate Computing","Framework","Pareto Front","Accuracy"],"publication":"Third Workshop on Approximate Computing (AxC 2018)","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","first_name":"Muhammad","id":"64665","last_name":"Awais"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"file":[{"date_created":"2018-07-20T14:13:31Z","file_name":"WitschenWMAP2018.pdf","access_level":"closed","file_id":"3587","creator":"tobias82","file_size":285348,"success":1,"relation":"main_file","date_updated":"2018-07-20T14:13:31Z","content_type":"application/pdf"}],"ddc":["000"],"user_id":"49051","abstract":[{"text":"Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.","lang":"eng"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:59:26Z","publication_status":"accepted","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"78"}],"title":"CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation"},{"abstract":[{"text":"Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.","lang":"eng"},{"text":"Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion. Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen, kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware. Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen, wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz im Vergleich zu konventionellen Caches erhöhen können.","lang":"ger"}],"title":"FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization","user_id":"477","department":[{"_id":"78"}],"author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"}],"publisher":"Universität Paderborn","publication_status":"published","date_created":"2018-07-27T06:41:13Z","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"status":"public","date_updated":"2022-01-06T06:59:31Z","_id":"3720","doi":"10.17619/UNIPB/1-376","page":"139","type":"dissertation","year":"2018","citation":{"ieee":"N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018.","short":"N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization, Universität Paderborn, 2018.","bibtex":"@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }","mla":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.","chicago":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.","ama":"Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376","apa":"Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376"},"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"type":"preprint","citation":{"short":"L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018).","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.","ama":"Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018).","bibtex":"@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018} }","mla":"Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018."},"year":"2018","date_updated":"2022-01-06T06:51:06Z","_id":"1165","file":[{"file_id":"5821","creator":"tobias82","file_size":287224,"success":1,"relation":"main_file","date_updated":"2018-11-26T08:00:53Z","content_type":"application/pdf","file_name":"WitschenWP2018[1].pdf","date_created":"2018-11-26T08:00:53Z","access_level":"closed"}],"publication":"4th Workshop On Approximate Computing (WAPCO 2018)","file_date_updated":"2018-11-26T08:00:53Z","department":[{"_id":"7"},{"_id":"34"},{"_id":"78"}],"author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-02-01T14:24:54Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","has_accepted_license":"1","user_id":"49051","ddc":["000"],"title":"Making the Case for Proof-carrying Approximate Circuits"},{"date_updated":"2022-01-06T07:01:59Z","doi":"10.1109/asap.2018.8445098","language":[{"iso":"eng"}],"title":"A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes","department":[{"_id":"78"}],"publication_identifier":{"isbn":["9781538674796"]},"publication_status":"published","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"}],"conference":{"location":"Milan, Italy","name":"The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors","start_date":"2018-07-10","end_date":"2018-07-12"},"_id":"5547","citation":{"ieee":"A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 2018.","short":"A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.","mla":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018, doi:10.1109/asap.2018.8445098.","bibtex":"@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }","ama":"Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018. doi:10.1109/asap.2018.8445098","apa":"Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098","chicago":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098."},"type":"conference","year":"2018","ddc":["040"],"user_id":"43646","publication":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file_date_updated":"2018-11-14T09:40:42Z","publisher":"IEEE","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"file":[{"access_level":"closed","file_name":"loesch_asap2018.pdf","date_created":"2018-11-14T09:40:42Z","relation":"main_file","success":1,"date_updated":"2018-11-14T09:40:42Z","content_type":"application/pdf","creator":"aloesch","file_id":"5552","file_size":2464949}],"date_created":"2018-11-14T09:26:53Z","status":"public","has_accepted_license":"1"},{"keyword":["Approximate computing","High-level synthesis","Accuracy","Monte-Carlo tree search","Circuit simulation"],"department":[{"_id":"78"}],"publication":"26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","author":[{"last_name":"Awais","id":"64665","first_name":"Muhammad","full_name":"Awais, Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969"},{"last_name":"Ghasemzadeh Mohammadi","id":"61186","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-07-10T09:21:38Z","status":"public","abstract":[{"lang":"eng","text":"Approximate computing has become a very popular design\r\nstrategy that exploits error resilient computations to achieve higher\r\nperformance and energy efficiency. Automated synthesis of approximate\r\ncircuits is performed via functional approximation, in which various\r\nparts of the target circuit are extensively examined with a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy and computational budget (i.e., power). However, as the number\r\nof possible approximate transformations increases, traditional search\r\ntechniques suffer from a combinatorial explosion due to the large\r\nbranching factor. In this work, we present a comprehensive framework\r\nfor automated synthesis of approximate circuits from either structural\r\nor behavioral descriptions. We adapt the Monte Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the large design\r\nspace exploration, which enables a broader range of potential possible\r\napproximations through lightweight random simulations. The proposed\r\nframework is able to recognize the design Pareto set even with low\r\ncomputational budgets. Experimental results highlight the capabilities of\r\nthe proposed synthesis framework by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined quality constraints."}],"user_id":"64665","title":"An MCTS-based Framework for Synthesis of Approximate Circuits","language":[{"iso":"eng"}],"page":"219-224","type":"conference","year":"2018","citation":{"ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026}, booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2018}, pages={219–224} }","mla":"Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.","apa":"Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 219–24, 2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026."},"date_updated":"2022-01-06T06:50:46Z","_id":"10598","doi":"10.1109/VLSI-SoC.2018.8645026"},{"department":[{"_id":"78"}],"publisher":"Ruhr-University Bochum","author":[{"id":"74287","last_name":"Clausing","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart"}],"date_created":"2019-07-10T12:13:18Z","status":"public","extern":"1","user_id":"3118","title":"Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data","language":[{"iso":"eng"}],"type":"mastersthesis","citation":{"bibtex":"@book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }","mla":"Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.","ama":"Clausing L. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.","apa":"Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum.","chicago":"Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.","ieee":"L. Clausing, Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum, 2018.","short":"L. Clausing, Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018."},"year":"2018","_id":"10782","date_updated":"2022-01-06T06:50:50Z"},{"status":"public","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"date_created":"2018-01-15T16:48:05Z","author":[{"full_name":"Jentzsch, Felix Paul","first_name":"Felix Paul","last_name":"Jentzsch"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"keyword":["Approximate Computing","Proof-Carrying Hardware","Formal Verification"],"title":"Enforcing IP Core Connection Properties with Verifiable Security Monitors","user_id":"477","type":"bachelorsthesis","citation":{"ieee":"F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.","short":"F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.","mla":"Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.","bibtex":"@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }","chicago":"Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.","apa":"Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn.","ama":"Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018."},"year":"2018","supervisor":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"language":[{"iso":"eng"}],"_id":"1097","date_updated":"2022-01-06T06:50:54Z"},{"department":[{"_id":"78"}],"publication":"IEEE Access","author":[{"last_name":"Ghribi","full_name":"Ghribi, Ines","first_name":"Ines"},{"last_name":"Abdallah","full_name":"Abdallah, Riadh Ben","first_name":"Riadh Ben"},{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"first_name":"Zhiwu","full_name":"Li, Zhiwu","last_name":"Li"},{"last_name":"Alnowibet","full_name":"Alnowibet, Khalid","first_name":"Khalid"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-08-26T13:33:00Z","status":"public","publication_status":"published","publication_identifier":{"issn":["2169-3536"]},"user_id":"398","title":"R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints","language":[{"iso":"eng"}],"page":"14078-14092","citation":{"short":"I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018) 14078–14092.","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet, and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92. https://doi.org/10.1109/access.2018.2799852.","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner, M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852","ama":"Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852","mla":"Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92, doi:10.1109/access.2018.2799852.","bibtex":"@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={10.1109/access.2018.2799852}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }"},"year":"2018","type":"journal_article","_id":"12965","date_updated":"2022-01-06T06:51:27Z","doi":"10.1109/access.2018.2799852"},{"language":[{"iso":"eng"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"citation":{"short":"T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität Paderborn, 2017.","ieee":"T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.","chicago":"Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.","apa":"Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn.","ama":"Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn; 2017.","bibtex":"@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }","mla":"Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017."},"type":"bachelorsthesis","year":"2017","_id":"3580","date_updated":"2022-01-06T06:59:25Z","author":[{"first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","last_name":"Hansmeier","id":"49992"}],"publisher":"Universität Paderborn","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"status":"public","date_created":"2018-07-20T13:44:34Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"user_id":"3118","title":"An FPGA Accelerator for Checking Resolution Proofs"},{"language":[{"iso":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"type":"mastersthesis","citation":{"short":"L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität Paderborn, 2017.","ieee":"L. M. Witschen, A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.","ama":"Witschen LM. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn; 2017.","apa":"Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits. Universität Paderborn.","chicago":"Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.","mla":"Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.","bibtex":"@book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }"},"year":"2017","date_updated":"2022-01-06T06:51:03Z","_id":"1157","status":"public","date_created":"2018-02-01T14:21:19Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"author":[{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","id":"49051","last_name":"Witschen"}],"publisher":"Universität Paderborn","department":[{"_id":"78"},{"_id":"7"}],"user_id":"477","title":"A Framework for the Synthesis of Approximate Circuits"},{"publisher":"Universität Paderborn","author":[{"last_name":"Knorr","full_name":"Knorr, Christoph","first_name":"Christoph"}],"department":[{"_id":"78"}],"status":"public","date_created":"2017-10-17T12:41:05Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"title":"OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten","user_id":"477","type":"mastersthesis","year":"2017","citation":{"ieee":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.","short":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten, Universität Paderborn, 2017.","bibtex":"@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }","mla":"Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.","apa":"Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn.","ama":"Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn; 2017.","chicago":"Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017."},"supervisor":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"ger"}],"_id":"74","date_updated":"2022-01-06T07:03:36Z"},{"doi":"10.1016/j.ijepes.2017.07.007","_id":"9919","intvolume":" 94","date_updated":"2019-10-06T21:56:18Z","citation":{"ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017;94:287-299. doi:10.1016/j.ijepes.2017.07.007","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 94, 287–299. https://doi.org/10.1016/j.ijepes.2017.07.007","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017): 287–99. https://doi.org/10.1016/j.ijepes.2017.07.007.","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={287–299} }","short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017) 287–299.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017."},"year":"2017","type":"journal_article","page":"287-299","language":[{"iso":"eng"}],"title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies","user_id":"3118","abstract":[{"lang":"eng","text":"This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network."}],"publication_status":"published","volume":94,"status":"public","date_created":"2019-05-22T13:14:20Z","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"first_name":"Martin","full_name":"Braun, Martin","last_name":"Braun"}],"publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)","department":[{"_id":"78"}],"keyword":["Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations"]},{"date_updated":"2022-01-06T07:03:08Z","_id":"65","doi":"10.1109/ASAP.2017.7995272","citation":{"chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.","apa":"Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272","mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.","bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017."},"year":"2017","type":"conference","language":[{"iso":"eng"}],"abstract":[{"text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.","lang":"eng"}],"ddc":["040"],"title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements","user_id":"477","department":[{"_id":"78"}],"file_date_updated":"2018-11-14T09:37:55Z","publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"file":[{"creator":"aloesch","file_id":"5550","file_size":467545,"relation":"main_file","success":1,"date_updated":"2018-11-14T09:37:55Z","content_type":"application/pdf","date_created":"2018-11-14T09:37:55Z","file_name":"loesch_asap2017.pdf","access_level":"closed"}],"date_created":"2017-10-17T12:41:04Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"has_accepted_license":"1","status":"public"},{"type":"journal_article","citation":{"ama":"Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems. 2017;(4):61:1--61:23. doi:10.1145/3054743","apa":"Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743","chicago":"Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.","mla":"Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743.","bibtex":"@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={10.1145/3054743}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }","short":"T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23.","ieee":"T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017."},"year":"2017","page":"61:1--61:23","issue":"4","_id":"68","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:04Z","file":[{"access_level":"closed","date_created":"2018-11-02T16:08:17Z","file_name":"a61-isenberg.pdf","date_updated":"2018-11-02T16:08:17Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":806356,"creator":"ups","file_id":"5324"}],"author":[{"first_name":"Tobias","full_name":"Isenberg, Tobias","last_name":"Isenberg"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Heike","full_name":"Wehrheim, Heike","last_name":"Wehrheim","id":"573"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"publisher":"ACM","file_date_updated":"2018-11-02T16:08:17Z","publication":"ACM Transactions on Design Automation of Electronic Systems","user_id":"3118","ddc":["000"],"abstract":[{"lang":"eng","text":"Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits."}],"language":[{"iso":"eng"}],"doi":"10.1145/3054743","date_updated":"2022-01-06T07:03:20Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"77"},{"_id":"78"}],"title":"Proof-Carrying Hardware via Inductive Invariants"},{"date_updated":"2022-01-06T06:50:47Z","_id":"10600","doi":"10.1145/2996468","year":"2017","citation":{"short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017).","ieee":"P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017. https://doi.org/10.1145/2996468.","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468","ama":"H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. 2017. doi:10.1145/2996468","bibtex":"@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={10.1145/2996468}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }","mla":"H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017, doi:10.1145/2996468."},"type":"journal_article","language":[{"iso":"eng"}],"title":"The First 25 Years of the FPL Conference – Significant Papers","user_id":"398","author":[{"last_name":"H.W. Leong","full_name":"H.W. Leong, Philip","first_name":"Philip"},{"last_name":"Amano","full_name":"Amano, Hideharu","first_name":"Hideharu"},{"last_name":"Anderson","first_name":"Jason","full_name":"Anderson, Jason"},{"full_name":"Bertels, Koen","first_name":"Koen","last_name":"Bertels"},{"last_name":"M.P. Cardoso","full_name":"M.P. Cardoso, Jo\\~{a}o","first_name":"Jo\\~{a}o"},{"full_name":"Diessel, Oliver","first_name":"Oliver","last_name":"Diessel"},{"last_name":"Gogniat","full_name":"Gogniat, Guy","first_name":"Guy"},{"full_name":"Hutton, Mike","first_name":"Mike","last_name":"Hutton"},{"full_name":"Lee, JunKyu","first_name":"JunKyu","last_name":"Lee"},{"full_name":"Luk, Wayne","first_name":"Wayne","last_name":"Luk"},{"last_name":"Lysaght","first_name":"Patrick","full_name":"Lysaght, Patrick"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"K. Prasanna","full_name":"K. Prasanna, Viktor","first_name":"Viktor"},{"full_name":"Rissa, Tero","first_name":"Tero","last_name":"Rissa"},{"first_name":"Cristina","full_name":"Silvano, Cristina","last_name":"Silvano"},{"full_name":"So, Hayden","first_name":"Hayden","last_name":"So"},{"first_name":"Yu","full_name":"Wang, Yu","last_name":"Wang"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:22:27Z"},{"doi":"10.1109/TETC.2016.2641599","date_updated":"2022-01-06T06:50:47Z","_id":"10601","language":[{"iso":"eng"}],"citation":{"mla":"F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.","bibtex":"@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }","chicago":"F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017. https://doi.org/10.1109/TETC.2016.2641599.","apa":"F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599","ama":"F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. 2017. doi:10.1109/TETC.2016.2641599","ieee":"R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.","short":"R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017)."},"type":"journal_article","year":"2017","user_id":"398","title":"Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)","status":"public","date_created":"2019-07-10T09:22:28Z","author":[{"full_name":"F. DeMara, Ronald","first_name":"Ronald","last_name":"F. DeMara"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Ottavi","full_name":"Ottavi, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing"},{"language":[{"iso":"eng"}],"page":"160-172","year":"2017","type":"journal_article","citation":{"bibtex":"@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }","mla":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.","apa":"Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems, 160–172. https://doi.org/10.1016/j.micpro.2017.06.002","ama":"Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172. doi:10.1016/j.micpro.2017.06.002","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, 2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.","ieee":"J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” Microprocessors and Microsystems, pp. 160–172, 2017.","short":"J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172."},"_id":"10611","date_updated":"2022-01-06T06:50:47Z","doi":"10.1016/j.micpro.2017.06.002","department":[{"_id":"78"}],"publication":"Microprocessors and Microsystems","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Elsevier","date_created":"2019-07-10T09:23:11Z","status":"public","user_id":"3118","title":"Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus"},{"user_id":"3118","title":"An AR-based Training and Assessment System for Myoelectrical Prosthetic Control","department":[{"_id":"78"}],"author":[{"first_name":"Christian","full_name":"Kaltschmidt, Christian","last_name":"Kaltschmidt"}],"publisher":"Paderborn University","date_created":"2019-07-10T09:25:11Z","status":"public","_id":"10613","date_updated":"2022-01-06T06:50:47Z","language":[{"iso":"eng"}],"citation":{"bibtex":"@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }","mla":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","apa":"Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University.","ama":"Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University; 2017.","chicago":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","ieee":"C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","short":"C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control, Paderborn University, 2017."},"year":"2017","type":"bachelorsthesis"},{"user_id":"3118","title":"A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller","status":"public","date_created":"2019-07-10T11:02:56Z","author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"full_name":"Thombansen, Georg","first_name":"Georg","last_name":"Thombansen"},{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","id":"49051","last_name":"Witschen"},{"last_name":"Wiens","first_name":"Alex","full_name":"Wiens, Alex"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Design, Automation and Test in Europe (DATE)","doi":"10.23919/DATE.2017.7927137","date_updated":"2022-01-06T06:50:49Z","_id":"10630","language":[{"iso":"eng"}],"citation":{"short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017.","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in Design, Automation and Test in Europe (DATE), 2017.","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137","chicago":"Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens, and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” In Design, Automation and Test in Europe (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927137.","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={10.23919/DATE.2017.7927137}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” Design, Automation and Test in Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137."},"year":"2017","type":"conference"},{"user_id":"3118","title":"Acceleration of Industrial Analytics Functions on a Platform FPGA","date_created":"2019-07-10T11:15:10Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Riaz","first_name":"Umair","full_name":"Riaz, Umair"}],"_id":"10666","date_updated":"2022-01-06T06:50:49Z","supervisor":[{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"}],"language":[{"iso":"eng"}],"citation":{"apa":"Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University.","ama":"Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University; 2017.","chicago":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","mla":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","bibtex":"@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017} }","short":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA, Paderborn University, 2017.","ieee":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017."},"year":"2017","type":"mastersthesis"},{"doi":"10.23919/DATE.2017.7927096","_id":"10672","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"ieee":"N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.","short":"N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.","mla":"Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design, Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.","bibtex":"@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}, DOI={10.23919/DATE.2017.7927096}, booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017} }","ama":"Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096","apa":"Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE). https://doi.org/10.23919/DATE.2017.7927096","chicago":"Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096."},"type":"conference","year":"2017","user_id":"3118","title":"Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor","status":"public","date_created":"2019-07-10T11:17:58Z","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"last_name":"Ashraf","full_name":"Ashraf, Ishraq Ibne","first_name":"Ishraq Ibne"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proc. Design, Automation and Test in Europe Conf. (DATE)","department":[{"_id":"78"}]},{"date_created":"2019-07-10T11:22:59Z","status":"public","publication":"2017 International Conference on Field Programmable Technology (ICFPT)","keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"department":[{"_id":"78"}],"author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","user_id":"398","page":"215-218","year":"2017","citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218."},"type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2017.8280144","_id":"10676","date_updated":"2022-01-06T06:50:49Z"},{"_id":"10692","date_updated":"2022-01-06T06:50:49Z","citation":{"apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES).","ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017} }","short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) (2017).","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017."},"type":"journal_article","year":"2017","user_id":"3118","title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies","date_created":"2019-07-10T11:29:58Z","status":"public","publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)","department":[{"_id":"78"}],"author":[{"last_name":"Shen","full_name":"Shen, Cong","first_name":"Cong"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}]},{"status":"public","date_created":"2019-07-10T11:43:32Z","publisher":"Paderborn University","author":[{"first_name":"Andreas","full_name":"Dietrich, Andreas","last_name":"Dietrich"}],"department":[{"_id":"78"}],"user_id":"3118","title":"Reconfigurable Cryptographic Services","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"type":"mastersthesis","citation":{"bibtex":"@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn University}, author={Dietrich, Andreas}, year={2017} }","mla":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.","apa":"Dietrich, A. (2017). Reconfigurable Cryptographic Services. Paderborn University.","ama":"Dietrich A. Reconfigurable Cryptographic Services. Paderborn University; 2017.","chicago":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.","ieee":"A. Dietrich, Reconfigurable Cryptographic Services. Paderborn University, 2017.","short":"A. Dietrich, Reconfigurable Cryptographic Services, Paderborn University, 2017."},"year":"2017","_id":"10708","date_updated":"2022-01-06T06:50:50Z"},{"title":"Fast Network Restoration by Partitioning of Parallel Black Start Zones","user_id":"3118","status":"public","date_created":"2019-07-10T11:59:38Z","author":[{"last_name":"Shen","full_name":"Shen, Cong","first_name":"Cong"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"publication":"The Journal of Engineering","department":[{"_id":"78"}],"doi":"10.1049/joe.2017.0032","_id":"10740","date_updated":"2022-01-06T06:50:50Z","citation":{"mla":"Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032}, journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={19pp} }","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering, 19pp. https://doi.org/10.1049/joe.2017.0032","ama":"Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, 19pp. https://doi.org/10.1049/joe.2017.0032.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.","short":"C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017) 19pp."},"type":"journal_article","year":"2017","page":"19pp"},{"citation":{"chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Lecture Notes in Computer Science. Springer, 2017.","ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer; 2017.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2017). Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer.","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2017, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 20th European Conference, EvoApplications}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2017}, collection={Lecture Notes in Computer Science} }","short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 20th European Conference, EvoApplications, Springer, 2017.","ieee":"G. Squillero et al., Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017."},"type":"book","year":"2017","series_title":"Lecture Notes in Computer Science","date_updated":"2022-01-06T06:50:50Z","_id":"10759","status":"public","date_created":"2019-07-10T12:06:37Z","publisher":"Springer","author":[{"first_name":"Giovanni","full_name":"Squillero, Giovanni","last_name":"Squillero"},{"last_name":"Burelli","full_name":"Burelli, Paolo","first_name":"Paolo"},{"first_name":"Antonio","full_name":"M. Mora, Antonio","last_name":"M. Mora"},{"full_name":"Agapitos, Alexandros","first_name":"Alexandros","last_name":"Agapitos"},{"first_name":"William","full_name":"S. Bush, William","last_name":"S. Bush"},{"full_name":"Cagnoni, Stefano","first_name":"Stefano","last_name":"Cagnoni"},{"first_name":"Carlos","full_name":"Cotta, Carlos","last_name":"Cotta"},{"last_name":"De Falco","first_name":"Ivanoe","full_name":"De Falco, Ivanoe"},{"last_name":"Della Cioppa","first_name":"Antonio","full_name":"Della Cioppa, Antonio"},{"last_name":"Divina","full_name":"Divina, Federico","first_name":"Federico"},{"first_name":"A.E.","full_name":"Eiben, A.E.","last_name":"Eiben"},{"full_name":"I. Esparcia-Alc{\\'a}zar, Anna","first_name":"Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"last_name":"Fern{\\'a}ndez de Vega","first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"full_name":"Haasdijk, Evert","first_name":"Evert","last_name":"Haasdijk"},{"last_name":"Ignacio Hidalgo","full_name":"Ignacio Hidalgo, J.","first_name":"J."},{"last_name":"Kampouridis","full_name":"Kampouridis, Michael","first_name":"Michael"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Mavrovouniotis","full_name":"Mavrovouniotis, Michalis","first_name":"Michalis"},{"last_name":"Thanh Nguyen","full_name":"Thanh Nguyen, Trung","first_name":"Trung"},{"first_name":"Robert","full_name":"Schaefer, Robert","last_name":"Schaefer"},{"first_name":"Kevin","full_name":"Sim, Kevin","last_name":"Sim"},{"last_name":"Tarantino","full_name":"Tarantino, Ernesto","first_name":"Ernesto"},{"last_name":"Urquhart","full_name":"Urquhart, Neil","first_name":"Neil"},{"first_name":"Mengjie","full_name":"Zhang (editors), Mengjie","last_name":"Zhang (editors)"}],"department":[{"_id":"78"}],"title":"Applications of Evolutionary Computation - 20th European Conference, EvoApplications","user_id":"3118"},{"title":"Parametrizing Cartesian Genetic Programming: An Empirical Study","user_id":"3118","publication":"KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI","department":[{"_id":"78"}],"publisher":"Springer International Publishing","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Roman","full_name":"Kalkreuth, Roman","last_name":"Kalkreuth"}],"date_created":"2019-07-10T12:06:38Z","status":"public","_id":"10760","date_updated":"2022-01-06T06:50:50Z","doi":"10.1007/978-3-319-67190-1_26","type":"conference","year":"2017","citation":{"bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={Parametrizing Cartesian Genetic Programming: An Empirical Study}, DOI={10.1007/978-3-319-67190-1_26}, booktitle={KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}, publisher={Springer International Publishing}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","mla":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.","ama":"Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26","apa":"Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26","chicago":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing, 2017. https://doi.org/10.1007/978-3-319-67190-1_26.","ieee":"P. Kaufmann and R. Kalkreuth, “Parametrizing Cartesian Genetic Programming: An Empirical Study,” in KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, 2017.","short":"P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017."},"language":[{"iso":"eng"}]},{"user_id":"3118","title":"Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","publication":"Adaptive Hardware and Systems (AHS)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:07:01Z","_id":"10761","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/AHS.2017.8046380","language":[{"iso":"eng"}],"year":"2017","type":"conference","citation":{"ieee":"P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,” in Adaptive Hardware and Systems (AHS), 2017.","short":"P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017.","bibtex":"@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}, DOI={10.1109/AHS.2017.8046380}, booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann, Paul and Ho, Nam and Platzner, Marco}, year={2017} }","mla":"Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” Adaptive Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.","ama":"Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380","apa":"Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380","chicago":"Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” In Adaptive Hardware and Systems (AHS). IEEE, 2017. https://doi.org/10.1109/AHS.2017.8046380."}},{"title":"An Empirical Study on the Parametrization of Cartesian Genetic Programming","user_id":"3118","department":[{"_id":"78"}],"publication":"Genetic and Evolutionary Computation (GECCO), Compendium","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Kalkreuth","first_name":"Roman","full_name":"Kalkreuth, Roman"}],"publisher":"ACM","date_created":"2019-07-10T12:07:03Z","status":"public","_id":"10762","date_updated":"2022-01-06T06:50:50Z","doi":"10.1145/3067695.3075980","citation":{"chicago":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), Compendium. ACM, 2017. https://doi.org/10.1145/3067695.3075980.","ama":"Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium. ACM; 2017. doi:10.1145/3067695.3075980","apa":"Kaufmann, P., & Kalkreuth, R. (2017). An Empirical Study on the Parametrization of Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO), Compendium. ACM. https://doi.org/10.1145/3067695.3075980","bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={An Empirical Study on the Parametrization of Cartesian Genetic Programming}, DOI={10.1145/3067695.3075980}, booktitle={Genetic and Evolutionary Computation (GECCO), Compendium}, publisher={ACM}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","mla":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017, doi:10.1145/3067695.3075980.","short":"P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017.","ieee":"P. Kaufmann and R. Kalkreuth, “An Empirical Study on the Parametrization of Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), Compendium, 2017."},"year":"2017","type":"conference"},{"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"department":[{"_id":"78"}],"author":[{"last_name":"Guettatfi","first_name":"Zakarya","full_name":"Guettatfi, Zakarya"},{"first_name":"Philipp","full_name":"Hübner, Philipp","last_name":"Hübner"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"}],"date_created":"2019-07-10T12:13:15Z","status":"public","title":"Computational self-awareness as design approach for visual sensor nodes","user_id":"3118","page":"1-8","type":"conference","year":"2017","citation":{"bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147","apa":"Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8."},"language":[{"iso":"eng"}],"_id":"10780","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/ReCoSoC.2017.8016147"},{"date_created":"2019-11-12T08:33:13Z","status":"public","publication_status":"published","publication_identifier":{"isbn":["9783319625683","9783319625690"],"issn":["1865-0929","1865-0937"]},"publication":"Communications in Computer and Information Science","department":[{"_id":"78"}],"author":[{"full_name":"Ghribi, Ines","first_name":"Ines","last_name":"Ghribi"},{"last_name":"Abdallah","full_name":"Abdallah, Riadh Ben","first_name":"Riadh Ben"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"Springer ","user_id":"398","title":"I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems","place":"Cham","language":[{"iso":"eng"}],"type":"conference","citation":{"bibtex":"@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={10.1007/978-3-319-62569-0_8}, booktitle={Communications in Computer and Information Science}, publisher={Springer }, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}, year={2017} }","mla":"Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” Communications in Computer and Information Science, Springer , 2017, doi:10.1007/978-3-319-62569-0_8.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In Communications in Computer and Information Science. Cham: Springer , 2017. https://doi.org/10.1007/978-3-319-62569-0_8.","ama":"Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: Communications in Computer and Information Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In Communications in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems,” in Communications in Computer and Information Science, 2017.","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017."},"year":"2017","doi":"10.1007/978-3-319-62569-0_8","date_updated":"2022-01-06T06:52:10Z","_id":"14893"},{"_id":"222","page":"112--122","year":"2016","citation":{"apa":"Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005.","mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={10.1016/j.compeleceng.2016.04.005}, journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering (2016) 112--122.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers & Electrical Engineering, pp. 112--122, 2016."},"type":"journal_article","user_id":"477","ddc":["040"],"abstract":[{"text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.","lang":"eng"}],"date_created":"2017-10-17T12:41:35Z","status":"public","has_accepted_license":"1","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T10:36:08Z","file_id":"1511","creator":"florida","file_size":931048,"access_level":"closed","file_name":"222-1-s2.0-S0045790616300684-main.pdf","date_created":"2018-03-21T10:36:08Z"}],"publication":"Computers & Electrical Engineering","file_date_updated":"2018-03-21T10:36:08Z","author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Bockhorn","full_name":"Bockhorn, Arne","first_name":"Arne"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Elsevier","doi":"10.1016/j.compeleceng.2016.04.005","date_updated":"2022-01-06T06:55:29Z","language":[{"iso":"eng"}],"title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}]},{"date_created":"2018-11-23T15:00:28Z","status":"public","publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Witschen","full_name":"Witschen, Linus","first_name":"Linus"},{"full_name":"Thombansen, Georg","first_name":"Georg","last_name":"Thombansen"},{"full_name":"Kraus, Florian","first_name":"Florian","id":"14053","last_name":"Kraus"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","user_id":"14053","title":"FPGA-based acceleration of high density myoelectric signal processing","extern":"1","language":[{"iso":"eng"}],"citation":{"chicago":"Boschmann, Alexander, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","ama":"Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","apa":"Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. https://doi.org/10.1109/reconfig.2015.7393312","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.","short":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ieee":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2016."},"type":"conference","year":"2016","doi":"10.1109/reconfig.2015.7393312","_id":"5812","date_updated":"2022-01-06T07:02:42Z"},{"date_updated":"2022-01-06T06:50:47Z","_id":"10612","year":"2016","type":"mastersthesis","citation":{"short":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion, Paderborn University, 2016.","ieee":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","chicago":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","apa":"Cedric Mertens, J. (2016). Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University.","ama":"Cedric Mertens J. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University; 2016.","bibtex":"@book{Cedric Mertens_2016, title={Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion}, publisher={Paderborn University}, author={Cedric Mertens, Jan}, year={2016} }","mla":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016."},"language":[{"iso":"eng"}],"title":"Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion","user_id":"3118","publisher":"Paderborn University","author":[{"last_name":"Cedric Mertens","first_name":"Jan","full_name":"Cedric Mertens, Jan"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:23:26Z"},{"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2016","citation":{"mla":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","bibtex":"@book{Nassery_2016, title={Implementation of Bilinear Pairings on Reconfigurable Hardware}, publisher={Paderborn University}, author={Nassery, Abdul Sami}, year={2016} }","ama":"Nassery AS. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University; 2016.","apa":"Nassery, A. S. (2016). Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University.","chicago":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","ieee":"A. S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","short":"A.S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware, Paderborn University, 2016."},"_id":"10616","date_updated":"2022-01-06T06:50:47Z","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Abdul Sami","full_name":"Nassery, Abdul Sami","last_name":"Nassery"}],"date_created":"2019-07-10T09:25:14Z","status":"public","user_id":"3118","title":"Implementation of Bilinear Pairings on Reconfigurable Hardware"},{"year":"2016","citation":{"short":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method, Paderborn University, 2016.","ieee":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University, 2016.","chicago":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.","ama":"Amin O. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University; 2016.","apa":"Amin, O. (2016). Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University.","mla":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.","bibtex":"@book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }"},"type":"mastersthesis","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"_id":"10617","date_updated":"2022-01-06T06:50:47Z","date_created":"2019-07-10T09:25:15Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Amin","full_name":"Amin, Omair","first_name":"Omair"}],"publisher":"Paderborn University","title":"Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method","user_id":"3118"},{"type":"conference","year":"2016","citation":{"short":"J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.","ieee":"J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs,” in Euromicro Conference on Digital System Design (DSD), 2016.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” In Euromicro Conference on Digital System Design (DSD), 2016. https://doi.org/10.1109/DSD.2016.35.","ama":"Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System Design (DSD). ; 2016. doi:10.1109/DSD.2016.35","apa":"Anwer, J., & Platzner, M. (2016). Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In Euromicro Conference on Digital System Design (DSD). https://doi.org/10.1109/DSD.2016.35","mla":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” Euromicro Conference on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.","bibtex":"@inproceedings{Anwer_Platzner_2016, title={Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}, DOI={10.1109/DSD.2016.35}, booktitle={Euromicro Conference on Digital System Design (DSD)}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2016} }"},"language":[{"iso":"eng"}],"doi":"10.1109/DSD.2016.35","_id":"10622","date_updated":"2022-01-06T06:50:48Z","date_created":"2019-07-10T09:33:00Z","status":"public","department":[{"_id":"78"}],"publication":"Euromicro Conference on Digital System Design (DSD)","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"title":"Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs","user_id":"3118"},{"date_updated":"2022-01-06T06:50:49Z","_id":"10631","citation":{"ieee":"A. Boschmann, S. Dosen, A. Werner, A. Raies, and D. Farina, “A novel immersive augmented reality system for prosthesis training and assessment,” in Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","short":"A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","mla":"Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","bibtex":"@inproceedings{Boschmann_Dosen_Werner_Raies_Farina_2016, title={A novel immersive augmented reality system for prosthesis training and assessment}, booktitle={Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)}, author={Boschmann, Alexander and Dosen, Strahinja and Werner, Andreas and Raies, Ali and Farina, Dario}, year={2016} }","apa":"Boschmann, A., Dosen, S., Werner, A., Raies, A., & Farina, D. (2016). A novel immersive augmented reality system for prosthesis training and assessment. In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI).","ama":"Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016.","chicago":"Boschmann, Alexander, Strahinja Dosen, Andreas Werner, Ali Raies, and Dario Farina. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016."},"year":"2016","type":"conference","title":"A novel immersive augmented reality system for prosthesis training and assessment","user_id":"3118","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"full_name":"Dosen, Strahinja","first_name":"Strahinja","last_name":"Dosen"},{"last_name":"Werner","full_name":"Werner, Andreas","first_name":"Andreas"},{"first_name":"Ali","full_name":"Raies, Ali","last_name":"Raies"},{"last_name":"Farina","first_name":"Dario","full_name":"Farina, Dario"}],"department":[{"_id":"78"}],"publication":"Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)","status":"public","date_created":"2019-07-10T11:02:57Z"},{"volume":644,"status":"public","date_created":"2019-07-10T11:14:43Z","publisher":"Elsevier","author":[{"first_name":"Tobias","full_name":"Graf, Tobias","last_name":"Graf"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"Journal Theoretical Computer Science","title":"Adaptive playouts for online learning of policies during Monte Carlo Tree Search","user_id":"3118","citation":{"short":"T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62.","ieee":"T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016.","ama":"Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62. doi:10.1016/j.tcs.2016.06.029","apa":"Graf, T., & Platzner, M. (2016). Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science, 644, 53–62. https://doi.org/10.1016/j.tcs.2016.06.029","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science 644 (2016): 53–62. https://doi.org/10.1016/j.tcs.2016.06.029.","bibtex":"@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029."},"year":"2016","type":"journal_article","page":"53-62","language":[{"iso":"eng"}],"doi":"10.1016/j.tcs.2016.06.029","_id":"10661","intvolume":" 644","date_updated":"2022-01-06T06:50:49Z"},{"language":[{"iso":"eng"}],"supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"year":"2016","citation":{"chicago":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","apa":"Horstmann, J. (2016). Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University.","ama":"Horstmann J. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University; 2016.","mla":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","bibtex":"@book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }","short":"J. Horstmann, Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs, Paderborn University, 2016.","ieee":"J. Horstmann, Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University, 2016."},"type":"bachelorsthesis","date_updated":"2022-01-06T06:50:49Z","_id":"10695","department":[{"_id":"78"}],"author":[{"last_name":"Horstmann","full_name":"Horstmann, Jens","first_name":"Jens"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:30:20Z","status":"public","user_id":"3118","title":"Beschleunigte Simulation elektrischer Stromnetze mit GPUs"},{"user_id":"3118","title":"Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control","status":"public","date_created":"2019-07-10T11:42:59Z","volume":87,"author":[{"last_name":"Ma","first_name":"Chenjie","full_name":"Ma, Chenjie"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Töbermann","first_name":"J.-Christian","full_name":"Töbermann, J.-Christian"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"publisher":"Elsevier","publication":"Renewable Energy","department":[{"_id":"78"}],"issue":"(part 2)","doi":"10.1016/j.renene.2015.07.083","date_updated":"2022-01-06T06:50:50Z","_id":"10705","intvolume":" 87","language":[{"iso":"eng"}],"year":"2016","citation":{"ieee":"C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016.","short":"C. Ma, P. Kaufmann, J.-C. Töbermann, M. Braun, Renewable Energy 87 (2016) 946–953.","mla":"Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083.","bibtex":"@article{Ma_Kaufmann_Töbermann_Braun_2016, title={Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}, volume={87}, DOI={10.1016/j.renene.2015.07.083}, number={(part 2)}, journal={Renewable Energy}, publisher={Elsevier}, author={Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}, year={2016}, pages={946–953} }","chicago":"Ma, Chenjie, Paul Kaufmann, J.-Christian Töbermann, and Martin Braun. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy 87, no. (part 2) (2016): 946–53. https://doi.org/10.1016/j.renene.2015.07.083.","ama":"Ma C, Kaufmann P, Töbermann J-C, Braun M. Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy. 2016;87((part 2)):946-953. doi:10.1016/j.renene.2015.07.083","apa":"Ma, C., Kaufmann, P., Töbermann, J.-C., & Braun, M. (2016). Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy, 87((part 2)), 946–953. https://doi.org/10.1016/j.renene.2015.07.083"},"type":"journal_article","page":"946-953"},{"title":"Operating System Support for Reconfigurable Cache","user_id":"3118","date_created":"2019-07-10T11:43:30Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Makeswaran","first_name":"Vignesh","full_name":"Makeswaran, Vignesh"}],"_id":"10706","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"V. Makeswaran, Operating System Support for Reconfigurable Cache, Paderborn University, 2016.","ieee":"V. Makeswaran, Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","chicago":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","apa":"Makeswaran, V. (2016). Operating System Support for Reconfigurable Cache. Paderborn University.","ama":"Makeswaran V. Operating System Support for Reconfigurable Cache. Paderborn University; 2016.","bibtex":"@book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }","mla":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016."},"year":"2016","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}]},{"type":"mastersthesis","citation":{"bibtex":"@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }","mla":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","apa":"Ibne Ashraf, I. (2016). Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University.","ama":"Ibne Ashraf I. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University; 2016.","chicago":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","ieee":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","short":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform, Paderborn University, 2016."},"year":"2016","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"_id":"10707","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T11:43:31Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Ibne Ashraf","first_name":"Ishraq","full_name":"Ibne Ashraf, Ishraq"}],"title":"Private/Shared Data Classification and Implementation for a Multi-Softcore Platform","user_id":"3118"},{"doi":"10.1109/ReConFig.2016.7857193","date_updated":"2022-01-06T06:50:50Z","_id":"10712","language":[{"iso":"eng"}],"page":"1-8","year":"2016","type":"conference","citation":{"short":"S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on, 2016, pp. 1–8.","apa":"Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193","ama":"Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 1–8. ReConFig, 2016. https://doi.org/10.1109/ReConFig.2016.7857193.","bibtex":"@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={10.1109/ReConFig.2016.7857193}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193."},"series_title":"ReConFig","user_id":"3118","title":"Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level","date_created":"2019-07-10T11:47:25Z","status":"public","publication":"Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on","department":[{"_id":"78"}],"author":[{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"status":"public","date_created":"2019-07-10T12:05:20Z","author":[{"first_name":"Marco","full_name":"Schmidt, Marco","last_name":"Schmidt"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"user_id":"3118","title":"Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung","language":[{"iso":"eng"}],"citation":{"ieee":"M. Schmidt, Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University, 2016.","short":"M. Schmidt, Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung, Paderborn University, 2016.","bibtex":"@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }","mla":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","chicago":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","apa":"Schmidt, M. (2016). Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University.","ama":"Schmidt M. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University; 2016."},"year":"2016","type":"bachelorsthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10755"},{"series_title":"Lecture Notes in Computer Science","year":"2016","citation":{"ieee":"G. Squillero et al., Applications of Evolutionary Computation - 19th European Conference, EvoApplications, vol. 9597. Springer, 2016.","short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 19th European Conference, EvoApplications, Springer, 2016.","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597, Springer, 2016.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2016, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 19th European Conference, EvoApplications}, volume={9597}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2016}, collection={Lecture Notes in Computer Science} }","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597. Lecture Notes in Computer Science. Springer, 2016.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2016). Applications of Evolutionary Computation - 19th European Conference, EvoApplications (Vol. 9597). Springer.","ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol 9597. Springer; 2016."},"type":"book","_id":"10758","intvolume":" 9597","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"Squillero, Giovanni","first_name":"Giovanni","last_name":"Squillero"},{"full_name":"Burelli, Paolo","first_name":"Paolo","last_name":"Burelli"},{"last_name":"M. Mora","first_name":"Antonio","full_name":"M. Mora, Antonio"},{"last_name":"Agapitos","full_name":"Agapitos, Alexandros","first_name":"Alexandros"},{"full_name":"S. Bush, William","first_name":"William","last_name":"S. Bush"},{"full_name":"Cagnoni, Stefano","first_name":"Stefano","last_name":"Cagnoni"},{"last_name":"Cotta","full_name":"Cotta, Carlos","first_name":"Carlos"},{"last_name":"De Falco","full_name":"De Falco, Ivanoe","first_name":"Ivanoe"},{"last_name":"Della Cioppa","first_name":"Antonio","full_name":"Della Cioppa, Antonio"},{"full_name":"Divina, Federico","first_name":"Federico","last_name":"Divina"},{"full_name":"Eiben, A.E.","first_name":"A.E.","last_name":"Eiben"},{"first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"last_name":"Fern{\\'a}ndez de Vega","full_name":"Fern{\\'a}ndez de Vega, Francisco","first_name":"Francisco"},{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"last_name":"Haasdijk","first_name":"Evert","full_name":"Haasdijk, Evert"},{"first_name":"J.","full_name":"Ignacio Hidalgo, J.","last_name":"Ignacio Hidalgo"},{"last_name":"Kampouridis","full_name":"Kampouridis, Michael","first_name":"Michael"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Mavrovouniotis","first_name":"Michalis","full_name":"Mavrovouniotis, Michalis"},{"first_name":"Trung","full_name":"Thanh Nguyen, Trung","last_name":"Thanh Nguyen"},{"full_name":"Schaefer, Robert","first_name":"Robert","last_name":"Schaefer"},{"first_name":"Kevin","full_name":"Sim, Kevin","last_name":"Sim"},{"last_name":"Tarantino","first_name":"Ernesto","full_name":"Tarantino, Ernesto"},{"full_name":"Urquhart, Neil","first_name":"Neil","last_name":"Urquhart"},{"last_name":"Zhang (editors)","first_name":"Mengjie","full_name":"Zhang (editors), Mengjie"}],"volume":9597,"date_created":"2019-07-10T12:06:36Z","status":"public","title":"Applications of Evolutionary Computation - 19th European Conference, EvoApplications","user_id":"3118"},{"_id":"10766","date_updated":"2022-01-06T06:50:50Z","citation":{"bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }","mla":"Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In Proceedings of the 30th European Simulation and Modelling Conference (ESM).","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016."},"type":"conference","year":"2016","language":[{"iso":"eng"}],"title":"RCo-Design: New Visual Environment for Reconfigurable Embedded Systems","user_id":"3118","status":"public","date_created":"2019-07-10T12:07:54Z","author":[{"full_name":"Ghribi, Ines","first_name":"Ines","last_name":"Ghribi"},{"last_name":"Ben Abdallah","full_name":"Ben Abdallah, Riadh","first_name":"Riadh"},{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 30th European Simulation and Modelling Conference (ESM)"},{"user_id":"3118","title":"New Co-design Methodology for Real-time Embedded Systems","publication":"Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)","department":[{"_id":"78"}],"author":[{"first_name":"Ines","full_name":"Ghribi, Ines","last_name":"Ghribi"},{"first_name":"Riadh","full_name":"Ben Abdallah, Riadh","last_name":"Ben Abdallah"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T12:07:56Z","status":"public","_id":"10768","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"page":"185-195","type":"conference","citation":{"short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 185–95, 2016.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195).","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.","mla":"Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }"},"year":"2016"},{"volume":"PP","status":"public","date_created":"2019-07-10T12:08:14Z","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel","last_name":"Gaillardon"},{"first_name":"Giovanni","full_name":"De Micheli, Giovanni","last_name":"De Micheli"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","title":"Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation","user_id":"3118","extern":"1","type":"journal_article","year":"2016","citation":{"short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908."},"page":"1-1","language":[{"iso":"eng"}],"doi":"10.1109/TCAD.2016.2547908","issue":"99","_id":"10769","date_updated":"2022-01-06T06:50:50Z"},{"_id":"10781","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016.","ieee":"S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016.","apa":"Hermansen, S. (2016). Custom Memory Controller for ReconOS. Paderborn University.","ama":"Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016.","chicago":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.","bibtex":"@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }","mla":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016."},"year":"2016","type":"bachelorsthesis","language":[{"iso":"eng"}],"title":"Custom Memory Controller for ReconOS","user_id":"3118","status":"public","date_created":"2019-07-10T12:13:16Z","publisher":"Paderborn University","author":[{"last_name":"Hermansen","full_name":"Hermansen, Sven","first_name":"Sven"}],"department":[{"_id":"78"}]},{"year":"2016","type":"book_editor","citation":{"bibtex":"@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={10.1007/978-3-319-39675-0}, publisher={Springer}, year={2016} }","mla":"Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.","chicago":"Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer, 2016. https://doi.org/10.1007/978-3-319-39675-0.","apa":"Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., & Yao, X. (Eds.). (2016). Self-aware Computing Systems: An Engineering Approach. Cham: Springer. https://doi.org/10.1007/978-3-319-39675-0","ama":"Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0","ieee":"P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.","short":"P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016."},"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:27Z","_id":"12972","doi":"10.1007/978-3-319-39675-0","publisher":"Springer","department":[{"_id":"78"}],"editor":[{"first_name":"Peter R.","full_name":"Lewis, Peter R.","last_name":"Lewis"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"},{"first_name":"Jim","full_name":"Tørresen, Jim","last_name":"Tørresen"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"publication_status":"published","publication_identifier":{"isbn":["9783319396743","9783319396750"],"issn":["1619-7127"]},"status":"public","date_created":"2019-08-27T13:39:43Z","place":"Cham","abstract":[{"text":"Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering.","lang":"eng"}],"title":"Self-aware Computing Systems: An Engineering Approach","user_id":"398"},{"doi":"10.1109/reconfig.2015.7393312","conference":{"location":"Mexiko City, Mexiko","name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"},"_id":"15873","date_updated":"2022-01-06T06:52:38Z","language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"chicago":"Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","ama":"Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","apa":"Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","short":"A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ieee":"A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016."},"user_id":"49051","title":"FPGA-based acceleration of high density myoelectric signal processing","date_created":"2020-02-11T07:48:56Z","status":"public","publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","keyword":["Electromyography","Feature extraction","Delays","Hardware Pattern recognition","Prosthetics","High definition video"],"department":[{"_id":"78"}],"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"last_name":"Thombansen","first_name":"Georg","full_name":"Thombansen, Georg"},{"last_name":"Kraus","first_name":"Florian","full_name":"Kraus, Florian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE"},{"status":"public","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2019-09-09T09:01:09Z","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Computer and Games","title":"Using Deep Convolutional Neural Networks in Monte Carlo Tree Search","user_id":"398","type":"conference","year":"2016","citation":{"apa":"Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games.","ama":"Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In Computer and Games, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","mla":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.","short":"T. Graf, M. Platzner, in: Computer and Games, 2016.","ieee":"T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016."},"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:29Z","_id":"13151"},{"author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"IEEE Computational Intelligence and Games","department":[{"_id":"78"}],"status":"public","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2019-09-09T09:06:39Z","user_id":"398","title":"Monte-Carlo Simulation Balancing Revisited","language":[{"iso":"eng"}],"citation":{"mla":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","chicago":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In IEEE Computational Intelligence and Games, 2016.","ama":"Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.","apa":"Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games.","ieee":"T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016.","short":"T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016."},"year":"2016","type":"conference","_id":"13152","date_updated":"2022-01-06T06:51:29Z"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:30Z","doi":"10.1109/ReCoSoC.2016.7533910","department":[{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"}],"title":"Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware","page":"1--8","type":"conference","year":"2016","citation":{"short":"T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","ieee":"T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","chicago":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910.","ama":"Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910","apa":"Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910","bibtex":"@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }","mla":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910."},"_id":"132","file":[{"file_id":"1562","creator":"florida","file_size":911171,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-21T13:02:30Z","file_name":"132-07533910.pdf","date_created":"2018-03-21T13:02:30Z","access_level":"closed"}],"publication":"Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)","file_date_updated":"2018-03-21T13:02:30Z","author":[{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2017-10-17T12:41:17Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module."}],"user_id":"477","ddc":["040"]},{"_id":"29","year":"2016","type":"book_chapter","citation":{"apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244."},"page":"227-244","user_id":"15278","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}],"status":"public","date_created":"2017-07-26T15:07:06Z","quality_controlled":"1","publisher":"Springer International Publishing","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"}],"publication":"FPGAs for Software Programmers","doi":"10.1007/978-3-319-26408-0_13","date_updated":"2023-09-26T13:25:38Z","language":[{"iso":"eng"}],"title":"ReconOS","place":"Cham","project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"editor":[{"full_name":"Koch, Dirk","first_name":"Dirk","last_name":"Koch"},{"last_name":"Hannig","full_name":"Hannig, Frank","first_name":"Frank"},{"full_name":"Ziener, Daniel","first_name":"Daniel","last_name":"Ziener"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:22Z","file":[{"access_level":"closed","date_created":"2018-11-14T13:20:32Z","file_name":"chapter8.pdf","relation":"main_file","success":1,"date_updated":"2018-11-14T13:20:32Z","content_type":"application/pdf","creator":"aloesch","file_id":"5613","file_size":833054}],"publisher":"Springer International Publishing","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","file_date_updated":"2018-11-14T13:20:32Z","publication":"Self-aware Computing Systems","user_id":"15278","ddc":["040"],"abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"type":"book_chapter","year":"2016","citation":{"bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165."},"page":"145-165","_id":"156","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"title":"Self-aware Compute Nodes","place":"Cham","language":[{"iso":"eng"}],"series_title":"Natural Computing Series (NCS)","doi":"10.1007/978-3-319-39675-0_8","date_updated":"2023-09-26T13:27:44Z"},{"_id":"168","type":"conference","citation":{"ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917."},"year":"2016","page":"912-917","abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T12:41:55Z","file_id":"1541","creator":"florida","file_size":261356,"access_level":"closed","date_created":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf"}],"publisher":"EDA Consortium / IEEE","author":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2018-03-21T12:41:55Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}]},{"page":"365--372","year":"2015","type":"conference","citation":{"ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.","apa":"Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32","ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32","chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32."},"_id":"269","file":[{"file_size":344309,"file_id":"1477","creator":"florida","date_updated":"2018-03-21T09:32:42Z","content_type":"application/pdf","relation":"main_file","success":1,"file_name":"269-paper_53.pdf","date_created":"2018-03-21T09:32:42Z","access_level":"closed"}],"file_date_updated":"2018-03-21T09:32:42Z","publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","author":[{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"full_name":"Wu, Sen","first_name":"Sen","last_name":"Wu"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2017-10-17T12:41:44Z","has_accepted_license":"1","status":"public","abstract":[{"text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.","lang":"eng"}],"user_id":"477","ddc":["040"],"series_title":"LNCS","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:57:30Z","doi":"10.1007/978-3-319-16214-0_32","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"}],"title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach"},{"department":[{"_id":"78"}],"author":[{"full_name":"Knorr, Christoph","first_name":"Christoph","last_name":"Knorr"}],"publisher":"Universität Paderborn","date_created":"2018-06-26T14:06:07Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"}],"status":"public","title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","user_id":"477","citation":{"apa":"Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn.","ama":"Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.","chicago":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","mla":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","ieee":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015."},"type":"bachelorsthesis","year":"2015","supervisor":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"ger"}],"_id":"3364","date_updated":"2022-01-06T06:59:13Z"},{"project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","language":[{"iso":"eng"}],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","date_created":"2018-03-23T14:06:12Z","status":"public","has_accepted_license":"1","volume":48,"file":[{"file_size":5605009,"creator":"ups","file_id":"5313","content_type":"application/pdf","date_updated":"2018-11-02T15:47:45Z","relation":"main_file","success":1,"date_created":"2018-11-02T15:47:45Z","file_name":"07163237.pdf","access_level":"closed"}],"publication":"IEEE Computer","file_date_updated":"2018-11-02T15:47:45Z","keyword":["self-awareness","self-expression"],"publisher":"IEEE Computer Society","author":[{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"user_id":"16153","ddc":["000"],"page":"18-20","year":"2015","citation":{"ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205"},"type":"journal_article","issue":"7","intvolume":" 48","_id":"1772"},{"user_id":"3118","title":"Self-Optimizing Organic Cache","author":[{"last_name":"Ahmed","first_name":"Abdullah Fathi","full_name":"Ahmed, Abdullah Fathi"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:25:13Z","date_updated":"2022-01-06T06:50:47Z","_id":"10615","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"year":"2015","citation":{"short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.","ieee":"A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015.","chicago":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","ama":"Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.","apa":"Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University.","mla":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }"},"type":"mastersthesis"},{"citation":{"ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015."},"type":"dissertation","year":"2015","page":"183","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"date_updated":"2022-01-06T06:50:48Z","_id":"10624","publication_identifier":{"isbn":["978-3-8325-4155-2"]},"status":"public","date_created":"2019-07-10T09:36:58Z","project":[{"_id":"30","grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","user_id":"3118","place":"Berlin","abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies."}]},{"date_updated":"2022-01-06T06:50:49Z","_id":"10668","citation":{"ieee":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015.","mla":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","apa":"Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University.","ama":"Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.","chicago":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015."},"year":"2015","type":"mastersthesis","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}],"title":"Evolution of Heat Flow Prediction Models for FPGA Devices","user_id":"3118","author":[{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:15:13Z"},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"}],"type":"mastersthesis","year":"2015","citation":{"bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }","mla":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","chicago":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","ama":"Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.","apa":"Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University.","ieee":"C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015."},"_id":"10671","date_updated":"2022-01-06T06:50:49Z","author":[{"last_name":"Haupt","full_name":"Haupt, Christian","first_name":"Christian"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:17:57Z","user_id":"3118","title":"Computer Vision basierte Klassifikation von HD EMG Signalen"},{"author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi","first_name":"Abdullah Fathi"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"department":[{"_id":"78"}],"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","status":"public","date_created":"2019-07-10T11:18:00Z","project":[{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","user_id":"3118","type":"conference","year":"2015","citation":{"short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178."},"page":"1-7","language":[{"iso":"eng"}],"_id":"10673","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/AHS.2015.7231178"},{"_id":"10693","date_updated":"2022-01-06T06:50:49Z","type":"conference","citation":{"short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.","ieee":"P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416.","chicago":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic and Evolutionary Computation (GECCO), 409–16. ACM, 2015.","apa":"Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM.","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.","mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.","bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }"},"year":"2015","page":"409-416","user_id":"3118","title":"Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Shen, Cong","first_name":"Cong","last_name":"Shen"}],"publisher":"ACM","publication":"Genetic and Evolutionary Computation (GECCO)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:30:00Z"},{"series_title":"FPT","language":[{"iso":"eng"}],"year":"2015","type":"conference","citation":{"mla":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.","bibtex":"@inproceedings{Meisner_Platzner_2015, series={FPT}, title={Comparison of thread signatures for error detection in hybrid multi-cores}, DOI={10.1109/FPT.2015.7393153}, booktitle={Field Programmable Technology (FPT), 2015 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2015}, pages={212–215}, collection={FPT} }","ama":"Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153","apa":"Meisner, S., & Platzner, M. (2015). Comparison of thread signatures for error detection in hybrid multi-cores. In Field Programmable Technology (FPT), 2015 International Conference on (pp. 212–215). https://doi.org/10.1109/FPT.2015.7393153","chicago":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” In Field Programmable Technology (FPT), 2015 International Conference On, 212–15. FPT, 2015. https://doi.org/10.1109/FPT.2015.7393153.","ieee":"S. Meisner and M. Platzner, “Comparison of thread signatures for error detection in hybrid multi-cores,” in Field Programmable Technology (FPT), 2015 International Conference on, 2015, pp. 212–215.","short":"S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215."},"page":"212-215","_id":"10711","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/FPT.2015.7393153","author":[{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Field Programmable Technology (FPT), 2015 International Conference on","status":"public","date_created":"2019-07-10T11:47:24Z","user_id":"3118","title":"Comparison of thread signatures for error detection in hybrid multi-cores"},{"user_id":"477","title":"Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs","author":[{"full_name":"Meißner, Roland","first_name":"Roland","last_name":"Meißner"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"status":"public","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"date_created":"2019-07-10T11:48:25Z","date_updated":"2022-01-06T06:50:50Z","_id":"10714","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"}],"type":"bachelorsthesis","year":"2015","citation":{"apa":"Meißner, R. (2015). Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn.","ama":"Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015.","chicago":"Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.","bibtex":"@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }","mla":"Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.","short":"R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs, Universität Paderborn, 2015.","ieee":"R. Meißner, Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn, 2015."}},{"status":"public","date_created":"2019-07-10T11:54:44Z","publisher":"Paderborn University","author":[{"last_name":"Posewsky","full_name":"Posewsky, Thorbjörn","first_name":"Thorbjörn"}],"department":[{"_id":"78"}],"title":"Acceleration of Artificial Neural Networks on a Zynq Platform","user_id":"3118","type":"mastersthesis","year":"2015","citation":{"ieee":"T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","short":"T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform, Paderborn University, 2015.","bibtex":"@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }","mla":"Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","chicago":"Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","ama":"Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015.","apa":"Posewsky, T. (2015). Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University."},"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"_id":"10726","date_updated":"2022-01-06T06:50:50Z"},{"date_created":"2019-07-10T12:06:35Z","status":"public","volume":9028,"department":[{"_id":"78"}],"publisher":"Springer","author":[{"first_name":"Antonio","full_name":"M. Mora, Antonio","last_name":"M. Mora"},{"full_name":"Squillero, Giovanni","first_name":"Giovanni","last_name":"Squillero"},{"last_name":"Agapitos","first_name":"Alexandros","full_name":"Agapitos, Alexandros"},{"full_name":"Burelli, Paolo","first_name":"Paolo","last_name":"Burelli"},{"first_name":"William","full_name":"S. Bush, William","last_name":"S. Bush"},{"full_name":"Cagnoni, Stefano","first_name":"Stefano","last_name":"Cagnoni"},{"last_name":"Cotta","full_name":"Cotta, Carlos","first_name":"Carlos"},{"first_name":"Ivanoe","full_name":"De Falco, Ivanoe","last_name":"De Falco"},{"first_name":"Antonio","full_name":"Della Cioppa, Antonio","last_name":"Della Cioppa"},{"last_name":"Divina","full_name":"Divina, Federico","first_name":"Federico"},{"first_name":"A.E.","full_name":"Eiben, A.E.","last_name":"Eiben"},{"last_name":"I. Esparcia-Alc{\\'a}zar","first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna"},{"full_name":"Fern{\\'a}ndez de Vega, Francisco","first_name":"Francisco","last_name":"Fern{\\'a}ndez de Vega"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"full_name":"Haasdijk, Evert","first_name":"Evert","last_name":"Haasdijk"},{"last_name":"Ignacio Hidalgo","first_name":"J.","full_name":"Ignacio Hidalgo, J."},{"first_name":"Michael","full_name":"Kampouridis, Michael","last_name":"Kampouridis"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Michalis","full_name":"Mavrovouniotis, Michalis","last_name":"Mavrovouniotis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"first_name":"Robert","full_name":"Schaefer, Robert","last_name":"Schaefer"},{"last_name":"Sim","first_name":"Kevin","full_name":"Sim, Kevin"},{"last_name":"Tarantino","full_name":"Tarantino, Ernesto","first_name":"Ernesto"},{"first_name":"Neil","full_name":"Urquhart, Neil","last_name":"Urquhart"},{"first_name":"Mengjie","full_name":"Zhang (editors), Mengjie","last_name":"Zhang (editors)"}],"user_id":"3118","title":"Applications of Evolutionary Computation - 18th European Conference, EvoApplications","place":"Copenhagen, Denmark","year":"2015","citation":{"bibtex":"@book{M. Mora_Squillero_Agapitos_Burelli_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2015, place={Copenhagen, Denmark}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 18th European Conference, EvoApplications}, volume={9028}, publisher={Springer}, author={M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2015}, collection={Lecture Notes in Computer Science} }","mla":"M. Mora, Antonio, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028, Springer, 2015.","ama":"M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.","apa":"M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2015). Applications of Evolutionary Computation - 18th European Conference, EvoApplications (Vol. 9028). Copenhagen, Denmark: Springer.","chicago":"M. Mora, Antonio, Giovanni Squillero, Alexandros Agapitos, Paolo Burelli, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028. Lecture Notes in Computer Science. Copenhagen, Denmark: Springer, 2015.","ieee":"A. M. Mora et al., Applications of Evolutionary Computation - 18th European Conference, EvoApplications, vol. 9028. Copenhagen, Denmark: Springer, 2015.","short":"A. M. Mora, G. Squillero, A. Agapitos, P. Burelli, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 18th European Conference, EvoApplications, Springer, Copenhagen, Denmark, 2015."},"type":"book","series_title":"Lecture Notes in Computer Science","_id":"10757","date_updated":"2022-01-06T06:50:50Z","intvolume":" 9028"},{"language":[{"iso":"eng"}],"citation":{"mla":"H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.” Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3, doi:10.1109/FPL.2015.7293747.","bibtex":"@inproceedings{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2015, title={Significant papers from the first 25 years of the FPL conference}, DOI={10.1109/FPL.2015.7293747}, booktitle={Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2015}, pages={1–3} }","ama":"H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1–3). Imperial College. https://doi.org/10.1109/FPL.2015.7293747","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~ao M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “Significant Papers from the First 25 Years of the FPL Conference.” In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 1–3. Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293747.","ieee":"P. H.W. Leong et al., “Significant papers from the first 25 years of the FPL conference,” in Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–3.","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3."},"type":"conference","year":"2015","page":"1-3","doi":"10.1109/FPL.2015.7293747","date_updated":"2022-01-06T06:50:50Z","_id":"10765","status":"public","date_created":"2019-07-10T12:07:53Z","author":[{"full_name":"H.W. Leong, Philip","first_name":"Philip","last_name":"H.W. Leong"},{"last_name":"Amano","full_name":"Amano, Hideharu","first_name":"Hideharu"},{"full_name":"Anderson, Jason","first_name":"Jason","last_name":"Anderson"},{"full_name":"Bertels, Koen","first_name":"Koen","last_name":"Bertels"},{"last_name":"M.P. Cardoso","full_name":"M.P. Cardoso, Jo\\~ao","first_name":"Jo\\~ao"},{"first_name":"Oliver","full_name":"Diessel, Oliver","last_name":"Diessel"},{"full_name":"Gogniat, Guy","first_name":"Guy","last_name":"Gogniat"},{"last_name":"Hutton","first_name":"Mike","full_name":"Hutton, Mike"},{"full_name":"Lee, JunKyu","first_name":"JunKyu","last_name":"Lee"},{"last_name":"Luk","full_name":"Luk, Wayne","first_name":"Wayne"},{"last_name":"Lysaght","full_name":"Lysaght, Patrick","first_name":"Patrick"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"K. Prasanna","first_name":"Viktor","full_name":"K. Prasanna, Viktor"},{"full_name":"Rissa, Tero","first_name":"Tero","last_name":"Rissa"},{"first_name":"Cristina","full_name":"Silvano, Cristina","last_name":"Silvano"},{"last_name":"So","full_name":"So, Hayden","first_name":"Hayden"},{"last_name":"Wang","full_name":"Wang, Yu","first_name":"Yu"}],"publisher":"Imperial College","department":[{"_id":"78"}],"publication":"Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)","user_id":"3118","title":"Significant papers from the first 25 years of the FPL conference"},{"date_created":"2019-07-10T12:07:55Z","status":"public","publication":"Proceedings of the 29th European Simulation and Modelling Conference (ESM)","department":[{"_id":"78"}],"author":[{"first_name":"Ines","full_name":"Ghribi, Ines","last_name":"Ghribi"},{"last_name":"Ben Abdallah","full_name":"Ben Abdallah, Riadh","first_name":"Riadh"},{"first_name":"Mohamed","full_name":"Khalgui, Mohamed","last_name":"Khalgui"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"3118","title":"New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software","language":[{"iso":"eng"}],"year":"2015","type":"conference","citation":{"chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” In Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In Proceedings of the 29th European Simulation and Modelling Conference (ESM).","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2015, title={New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}, booktitle={Proceedings of the 29th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2015} }","mla":"Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,” in Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015."},"date_updated":"2022-01-06T06:50:50Z","_id":"10767"},{"doi":"10.1109/TNANO.2015.2482359","issue":"6","date_updated":"2022-01-06T06:50:50Z","_id":"10770","intvolume":" 14","page":"1117-1126","citation":{"short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126. https://doi.org/10.1109/TNANO.2015.2482359","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology 14, no. 6 (2015): 1117–26. https://doi.org/10.1109/TNANO.2015.2482359.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }"},"year":"2015","type":"journal_article","language":[{"iso":"eng"}],"title":"From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires","user_id":"3118","extern":"1","volume":14,"date_created":"2019-07-10T12:08:15Z","status":"public","publication":"IEEE Transactions on Nanotechnology","department":[{"_id":"78"}],"author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"Gaillardon","first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel"},{"last_name":"De Micheli","full_name":"De Micheli, Giovanni","first_name":"Giovanni"}],"publisher":"IEEE"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” In 2015 IEEE Computer Society Annual Symposium on VLSI, 491–96. IEEE, 2015. https://doi.org/10.1109/ISVLSI.2015.13.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015, title={On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}, DOI={10.1109/ISVLSI.2015.13}, booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}, year={2015}, pages={491–496} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 491–496."},"year":"2015","page":"491-496","_id":"10771","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/ISVLSI.2015.13","author":[{"last_name":"Ghasemzadeh Mohammadi","id":"61186","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"first_name":"Jian","full_name":"Zhang, Jian","last_name":"Zhang"},{"full_name":"De Micheli, Giovanni","first_name":"Giovanni","last_name":"De Micheli"},{"first_name":"Eduardo","full_name":"Sanchez, Eduardo","last_name":"Sanchez"},{"last_name":"Reorda","full_name":"Reorda, Matteo Sonza","first_name":"Matteo Sonza"}],"publisher":"IEEE","publication":"2015 IEEE Computer Society Annual Symposium on VLSI","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:08:16Z","extern":"1","user_id":"3118","title":"On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors"},{"date_created":"2019-07-10T12:08:17Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition","publisher":"EDA Consortium","author":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"last_name":"De Micheli","full_name":"De Micheli, Giovanni","first_name":"Giovanni"}],"user_id":"3118","title":"Fault modeling in controllable polarity silicon nanowire circuits","extern":"1","language":[{"iso":"eng"}],"page":"453-458","type":"conference","citation":{"ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling in controllable polarity silicon nanowire circuits,” in Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, 2015, pp. 453–458.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, EDA Consortium, 2015, pp. 453–458.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault modeling in controllable polarity silicon nanowire circuits}, DOI={10.7873/DATE.2015.0428}, booktitle={Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={453–458} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, EDA Consortium, 2015, pp. 453–58, doi:10.7873/DATE.2015.0428.","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” In Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, 453–58. EDA Consortium, 2015. https://doi.org/10.7873/DATE.2015.0428.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition (pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428"},"year":"2015","doi":"10.7873/DATE.2015.0428","_id":"10772","date_updated":"2022-01-06T06:50:50Z"},{"doi":"10.1109/FPL.2015.7293994","date_updated":"2022-01-06T06:50:50Z","_id":"10779","language":[{"iso":"eng"}],"citation":{"short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.","chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293994.","apa":"Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }"},"type":"conference","year":"2015","user_id":"398","title":"Over effective hard real-time hardware tasks scheduling and allocation","extern":"1","status":"public","date_created":"2019-07-10T12:11:36Z","publication_identifier":{"issn":["1946-147X"]},"author":[{"last_name":"Guettatfi","first_name":"Zakarya","full_name":"Guettatfi, Zakarya"},{"last_name":"Kermia","full_name":"Kermia, Omar","first_name":"Omar"},{"full_name":"Khouas, Abdelhakim","first_name":"Abdelhakim","last_name":"Khouas"}],"publisher":"Imperial College","keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"department":[{"_id":"78"}],"publication":"25th International Conference on Field Programmable Logic and Applications (FPL)"}]