[{"supervisor":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","citation":{"apa":"Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn.","ama":"Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn; 2018.","chicago":"Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.","bibtex":"@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }","mla":"Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.","short":"J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes, Universität Paderborn, 2018.","ieee":"J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018."},"year":"2018","date_updated":"2022-01-06T06:59:13Z","_id":"3365","status":"public","project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_created":"2018-06-26T14:10:18Z","author":[{"last_name":"Schnuer","full_name":"Schnuer, Jan-Philip","first_name":"Jan-Philip"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"user_id":"477","title":"Static Scheduling Algorithms for Heterogeneous Compute Nodes"},{"type":"bachelorsthesis","year":"2018","citation":{"short":"M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn, 2018.","ieee":"M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn, 2018.","apa":"Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn.","ama":"Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn; 2018.","chicago":"Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018.","bibtex":"@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }","mla":"Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018."},"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"_id":"3366","date_updated":"2022-01-06T06:59:13Z","status":"public","date_created":"2018-06-26T14:12:00Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"publisher":"Universität Paderborn","author":[{"full_name":"Croce, Marcel","first_name":"Marcel","last_name":"Croce"}],"department":[{"_id":"78"}],"title":"Evaluation of OpenCL-based Compilation for FPGAs","user_id":"477"},{"status":"public","has_accepted_license":"1","date_created":"2018-06-27T09:30:24Z","volume":10824,"file":[{"access_level":"closed","file_name":"AnFPGAHMC-BasedAcceleratorForR.pdf","date_created":"2018-11-02T13:55:07Z","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-02T13:55:07Z","file_id":"5257","creator":"ups","file_size":612367}],"publisher":"Springer International Publishing","author":[{"first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","last_name":"Hansmeier","id":"49992"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Andrews","first_name":"David","full_name":"Andrews, David"}],"file_date_updated":"2018-11-02T13:55:07Z","publication":"ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications","user_id":"3118","ddc":["000"],"abstract":[{"lang":"eng","text":"Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory."}],"type":"conference","year":"2018","citation":{"ieee":"T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824, pp. 153–165.","short":"T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2018, pp. 153–165.","mla":"Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, vol. 10824, Springer International Publishing, 2018, pp. 153–65, doi:10.1007/978-3-319-78890-6_13.","bibtex":"@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking}, volume={10824}, DOI={10.1007/978-3-319-78890-6_13}, booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture Notes in Computer Science} }","chicago":"Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.","ama":"Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13","apa":"Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini, Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13"},"page":"153-165","intvolume":" 10824","_id":"3373","conference":{"location":"Santorini, Greece","name":"ARC: International Symposium on Applied Reconfigurable Computing","start_date":"2018-05-02","end_date":"2018-05-04"},"project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783319788890","9783319788906"]},"publication_status":"published","department":[{"_id":"78"}],"title":"An FPGA/HMC-Based Accelerator for Resolution Proof Checking","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-78890-6_13","date_updated":"2022-01-06T06:59:13Z"},{"publication_status":"accepted","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"78"}],"title":"CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:59:26Z","date_created":"2018-07-20T14:10:46Z","status":"public","has_accepted_license":"1","file_date_updated":"2018-07-20T14:13:31Z","keyword":["Approximate Computing","Framework","Pareto Front","Accuracy"],"publication":"Third Workshop on Approximate Computing (AxC 2018)","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"id":"64665","last_name":"Awais","orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","first_name":"Muhammad"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-07-20T14:13:31Z","creator":"tobias82","file_id":"3587","file_size":285348,"access_level":"closed","date_created":"2018-07-20T14:13:31Z","file_name":"WitschenWMAP2018.pdf"}],"ddc":["000"],"user_id":"49051","abstract":[{"text":"Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.","lang":"eng"}],"page":"6","year":"2018","citation":{"apa":"Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).","ama":"Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018), n.d.","mla":"Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).","bibtex":"@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco} }","short":"L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Third Workshop on Approximate Computing (AxC 2018) (n.d.).","ieee":"L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). ."},"type":"preprint","_id":"3586"},{"_id":"3720","date_updated":"2022-01-06T06:59:31Z","doi":"10.17619/UNIPB/1-376","page":"139","year":"2018","citation":{"ieee":"N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018.","short":"N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization, Universität Paderborn, 2018.","mla":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.","bibtex":"@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }","ama":"Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376","apa":"Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376","chicago":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376."},"type":"dissertation","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches."},{"lang":"ger","text":"Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion. Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen, kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware. Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen, wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz im Vergleich zu konventionellen Caches erhöhen können."}],"title":"FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization","user_id":"477","department":[{"_id":"78"}],"publisher":"Universität Paderborn","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"}],"publication_status":"published","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"}],"date_created":"2018-07-27T06:41:13Z","status":"public"},{"user_id":"49051","ddc":["000"],"title":"Making the Case for Proof-carrying Approximate Circuits","file":[{"file_id":"5821","creator":"tobias82","file_size":287224,"relation":"main_file","success":1,"date_updated":"2018-11-26T08:00:53Z","content_type":"application/pdf","file_name":"WitschenWP2018[1].pdf","date_created":"2018-11-26T08:00:53Z","access_level":"closed"}],"file_date_updated":"2018-11-26T08:00:53Z","department":[{"_id":"7"},{"_id":"34"},{"_id":"78"}],"publication":"4th Workshop On Approximate Computing (WAPCO 2018)","author":[{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","id":"49051","last_name":"Witschen"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2018-02-01T14:24:54Z","status":"public","has_accepted_license":"1","_id":"1165","date_updated":"2022-01-06T06:51:06Z","language":[{"iso":"eng"}],"year":"2018","type":"preprint","citation":{"ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018.","short":"L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018).","bibtex":"@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018} }","mla":"Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018).","ama":"Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018."}},{"user_id":"43646","ddc":["040"],"file":[{"date_created":"2018-11-14T09:40:42Z","file_name":"loesch_asap2018.pdf","access_level":"closed","creator":"aloesch","file_id":"5552","file_size":2464949,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-14T09:40:42Z"}],"author":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","publication":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file_date_updated":"2018-11-14T09:40:42Z","status":"public","has_accepted_license":"1","date_created":"2018-11-14T09:26:53Z","_id":"5547","conference":{"name":"The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors","start_date":"2018-07-10","location":"Milan, Italy","end_date":"2018-07-12"},"year":"2018","type":"conference","citation":{"mla":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018, doi:10.1109/asap.2018.8445098.","bibtex":"@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }","chicago":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.","ama":"Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018. doi:10.1109/asap.2018.8445098","apa":"Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098","ieee":"A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 2018.","short":"A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018."},"title":"A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes","department":[{"_id":"78"}],"project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}],"publication_identifier":{"isbn":["9781538674796"]},"publication_status":"published","date_updated":"2022-01-06T07:01:59Z","doi":"10.1109/asap.2018.8445098","language":[{"iso":"eng"}]},{"type":"conference","citation":{"ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026}, booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2018}, pages={219–224} }","mla":"Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 219–24, 2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026","apa":"Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026"},"year":"2018","page":"219-224","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:46Z","_id":"10598","doi":"10.1109/VLSI-SoC.2018.8645026","author":[{"first_name":"Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","last_name":"Awais","id":"64665"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"keyword":["Approximate computing","High-level synthesis","Accuracy","Monte-Carlo tree search","Circuit simulation"],"department":[{"_id":"78"}],"publication":"26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","status":"public","date_created":"2019-07-10T09:21:38Z","abstract":[{"lang":"eng","text":"Approximate computing has become a very popular design\r\nstrategy that exploits error resilient computations to achieve higher\r\nperformance and energy efficiency. Automated synthesis of approximate\r\ncircuits is performed via functional approximation, in which various\r\nparts of the target circuit are extensively examined with a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy and computational budget (i.e., power). However, as the number\r\nof possible approximate transformations increases, traditional search\r\ntechniques suffer from a combinatorial explosion due to the large\r\nbranching factor. In this work, we present a comprehensive framework\r\nfor automated synthesis of approximate circuits from either structural\r\nor behavioral descriptions. We adapt the Monte Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the large design\r\nspace exploration, which enables a broader range of potential possible\r\napproximations through lightweight random simulations. The proposed\r\nframework is able to recognize the design Pareto set even with low\r\ncomputational budgets. Experimental results highlight the capabilities of\r\nthe proposed synthesis framework by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined quality constraints."}],"title":"An MCTS-based Framework for Synthesis of Approximate Circuits","user_id":"64665"},{"date_created":"2019-07-10T12:13:18Z","status":"public","department":[{"_id":"78"}],"publisher":"Ruhr-University Bochum","author":[{"id":"74287","last_name":"Clausing","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart"}],"title":"Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data","user_id":"3118","extern":"1","type":"mastersthesis","citation":{"chicago":"Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.","ama":"Clausing L. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.","apa":"Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum.","bibtex":"@book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }","mla":"Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.","short":"L. Clausing, Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.","ieee":"L. Clausing, Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum, 2018."},"year":"2018","language":[{"iso":"eng"}],"_id":"10782","date_updated":"2022-01-06T06:50:50Z"},{"user_id":"477","title":"Enforcing IP Core Connection Properties with Verifiable Security Monitors","status":"public","date_created":"2018-01-15T16:48:05Z","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"author":[{"full_name":"Jentzsch, Felix Paul","first_name":"Felix Paul","last_name":"Jentzsch"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"keyword":["Approximate Computing","Proof-Carrying Hardware","Formal Verification"],"_id":"1097","date_updated":"2022-01-06T06:50:54Z","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"citation":{"chicago":"Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.","apa":"Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn.","ama":"Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018.","bibtex":"@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }","mla":"Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.","short":"F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.","ieee":"F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018."},"type":"bachelorsthesis","year":"2018"},{"date_created":"2019-08-26T13:33:00Z","status":"public","publication_status":"published","publication_identifier":{"issn":["2169-3536"]},"publication":"IEEE Access","department":[{"_id":"78"}],"author":[{"first_name":"Ines","full_name":"Ghribi, Ines","last_name":"Ghribi"},{"first_name":"Riadh Ben","full_name":"Abdallah, Riadh Ben","last_name":"Abdallah"},{"first_name":"Mohamed","full_name":"Khalgui, Mohamed","last_name":"Khalgui"},{"full_name":"Li, Zhiwu","first_name":"Zhiwu","last_name":"Li"},{"first_name":"Khalid","full_name":"Alnowibet, Khalid","last_name":"Alnowibet"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"398","title":"R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints","language":[{"iso":"eng"}],"page":"14078-14092","type":"journal_article","citation":{"apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner, M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852","ama":"Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet, and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92. https://doi.org/10.1109/access.2018.2799852.","bibtex":"@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={10.1109/access.2018.2799852}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }","mla":"Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92, doi:10.1109/access.2018.2799852.","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018) 14078–14092.","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018."},"year":"2018","doi":"10.1109/access.2018.2799852","_id":"12965","date_updated":"2022-01-06T06:51:27Z"},{"date_updated":"2022-01-06T06:59:25Z","_id":"3580","supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","citation":{"ieee":"T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.","short":"T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität Paderborn, 2017.","mla":"Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.","bibtex":"@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }","chicago":"Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.","ama":"Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn; 2017.","apa":"Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn."},"year":"2017","user_id":"3118","title":"An FPGA Accelerator for Checking Resolution Proofs","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"author":[{"id":"49992","last_name":"Hansmeier","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","first_name":"Tim"}],"publisher":"Universität Paderborn","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - Subproject B4","_id":"12"}],"date_created":"2018-07-20T13:44:34Z","status":"public"},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2018-02-01T14:21:19Z","status":"public","department":[{"_id":"78"},{"_id":"7"}],"publisher":"Universität Paderborn","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"}],"user_id":"477","title":"A Framework for the Synthesis of Approximate Circuits","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"}],"year":"2017","type":"mastersthesis","citation":{"ieee":"L. M. Witschen, A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.","short":"L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität Paderborn, 2017.","bibtex":"@book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }","mla":"Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.","apa":"Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits. Universität Paderborn.","ama":"Witschen LM. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn; 2017.","chicago":"Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017."},"date_updated":"2022-01-06T06:51:03Z","_id":"1157"},{"status":"public","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"date_created":"2017-10-17T12:41:05Z","author":[{"last_name":"Knorr","full_name":"Knorr, Christoph","first_name":"Christoph"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"title":"OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten","user_id":"477","type":"mastersthesis","year":"2017","citation":{"ama":"Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn; 2017.","apa":"Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn.","chicago":"Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.","bibtex":"@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }","mla":"Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.","short":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten, Universität Paderborn, 2017.","ieee":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017."},"supervisor":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"language":[{"iso":"ger"}],"date_updated":"2022-01-06T07:03:36Z","_id":"74"},{"date_updated":"2019-10-06T21:56:18Z","_id":"9919","intvolume":" 94","doi":"10.1016/j.ijepes.2017.07.007","language":[{"iso":"eng"}],"citation":{"ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017.","short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017) 287–299.","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={287–299} }","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017): 287–99. https://doi.org/10.1016/j.ijepes.2017.07.007.","ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017;94:287-299. doi:10.1016/j.ijepes.2017.07.007","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 94, 287–299. https://doi.org/10.1016/j.ijepes.2017.07.007"},"year":"2017","type":"journal_article","page":"287-299","abstract":[{"text":"This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.","lang":"eng"}],"user_id":"3118","title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)","department":[{"_id":"78"}],"keyword":["Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations"],"status":"public","date_created":"2019-05-22T13:14:20Z","volume":94,"publication_status":"published"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:04Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"author":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"file_date_updated":"2018-11-14T09:37:55Z","department":[{"_id":"78"}],"publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file":[{"access_level":"closed","file_name":"loesch_asap2017.pdf","date_created":"2018-11-14T09:37:55Z","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-14T09:37:55Z","file_id":"5550","creator":"aloesch","file_size":467545}],"title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements","ddc":["040"],"user_id":"477","abstract":[{"lang":"eng","text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules."}],"type":"conference","citation":{"chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272","apa":"Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272","mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.","bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017."},"year":"2017","language":[{"iso":"eng"}],"doi":"10.1109/ASAP.2017.7995272","date_updated":"2022-01-06T07:03:08Z","_id":"65"},{"title":"Proof-Carrying Hardware via Inductive Invariants","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"77"},{"_id":"78"}],"doi":"10.1145/3054743","date_updated":"2022-01-06T07:03:20Z","language":[{"iso":"eng"}],"user_id":"3118","ddc":["000"],"abstract":[{"text":"Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:04Z","file":[{"file_size":806356,"file_id":"5324","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T16:08:17Z","relation":"main_file","success":1,"date_created":"2018-11-02T16:08:17Z","file_name":"a61-isenberg.pdf","access_level":"closed"}],"author":[{"full_name":"Isenberg, Tobias","first_name":"Tobias","last_name":"Isenberg"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Wehrheim, Heike","first_name":"Heike","id":"573","last_name":"Wehrheim"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"publisher":"ACM","file_date_updated":"2018-11-02T16:08:17Z","publication":"ACM Transactions on Design Automation of Electronic Systems","issue":"4","_id":"68","year":"2017","type":"journal_article","citation":{"short":"T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23.","ieee":"T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017.","chicago":"Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.","ama":"Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems. 2017;(4):61:1--61:23. doi:10.1145/3054743","apa":"Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743","mla":"Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743.","bibtex":"@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={10.1145/3054743}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }"},"page":"61:1--61:23"},{"year":"2017","citation":{"short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017).","ieee":"P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468","ama":"H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. 2017. doi:10.1145/2996468","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017. https://doi.org/10.1145/2996468.","bibtex":"@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={10.1145/2996468}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }","mla":"H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017, doi:10.1145/2996468."},"type":"journal_article","language":[{"iso":"eng"}],"_id":"10600","date_updated":"2022-01-06T06:50:47Z","doi":"10.1145/2996468","author":[{"full_name":"H.W. Leong, Philip","first_name":"Philip","last_name":"H.W. Leong"},{"first_name":"Hideharu","full_name":"Amano, Hideharu","last_name":"Amano"},{"full_name":"Anderson, Jason","first_name":"Jason","last_name":"Anderson"},{"first_name":"Koen","full_name":"Bertels, Koen","last_name":"Bertels"},{"full_name":"M.P. Cardoso, Jo\\~{a}o","first_name":"Jo\\~{a}o","last_name":"M.P. Cardoso"},{"first_name":"Oliver","full_name":"Diessel, Oliver","last_name":"Diessel"},{"first_name":"Guy","full_name":"Gogniat, Guy","last_name":"Gogniat"},{"full_name":"Hutton, Mike","first_name":"Mike","last_name":"Hutton"},{"first_name":"JunKyu","full_name":"Lee, JunKyu","last_name":"Lee"},{"full_name":"Luk, Wayne","first_name":"Wayne","last_name":"Luk"},{"first_name":"Patrick","full_name":"Lysaght, Patrick","last_name":"Lysaght"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"K. Prasanna","first_name":"Viktor","full_name":"K. Prasanna, Viktor"},{"first_name":"Tero","full_name":"Rissa, Tero","last_name":"Rissa"},{"first_name":"Cristina","full_name":"Silvano, Cristina","last_name":"Silvano"},{"first_name":"Hayden","full_name":"So, Hayden","last_name":"So"},{"full_name":"Wang, Yu","first_name":"Yu","last_name":"Wang"}],"department":[{"_id":"78"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems","status":"public","date_created":"2019-07-10T09:22:27Z","title":"The First 25 Years of the FPL Conference – Significant Papers","user_id":"398"},{"author":[{"first_name":"Ronald","full_name":"F. DeMara, Ronald","last_name":"F. DeMara"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Ottavi","first_name":"Marco","full_name":"Ottavi, Marco"}],"publication":"IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:22:28Z","user_id":"398","title":"Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)","language":[{"iso":"eng"}],"type":"journal_article","citation":{"short":"R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017).","ieee":"R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.","apa":"F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599","ama":"F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. 2017. doi:10.1109/TETC.2016.2641599","chicago":"F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017. https://doi.org/10.1109/TETC.2016.2641599.","bibtex":"@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }","mla":"F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599."},"year":"2017","_id":"10601","date_updated":"2022-01-06T06:50:47Z","doi":"10.1109/TETC.2016.2641599"},{"doi":"10.1016/j.micpro.2017.06.002","_id":"10611","date_updated":"2022-01-06T06:50:47Z","page":"160-172","year":"2017","type":"journal_article","citation":{"mla":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.","bibtex":"@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }","apa":"Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems, 160–172. https://doi.org/10.1016/j.micpro.2017.06.002","ama":"Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172. doi:10.1016/j.micpro.2017.06.002","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, 2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.","ieee":"J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” Microprocessors and Microsystems, pp. 160–172, 2017.","short":"J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172."},"language":[{"iso":"eng"}],"title":"Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus","user_id":"3118","date_created":"2019-07-10T09:23:11Z","status":"public","department":[{"_id":"78"}],"publication":"Microprocessors and Microsystems","publisher":"Elsevier","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}]},{"status":"public","date_created":"2019-07-10T09:25:11Z","publisher":"Paderborn University","author":[{"full_name":"Kaltschmidt, Christian","first_name":"Christian","last_name":"Kaltschmidt"}],"department":[{"_id":"78"}],"user_id":"3118","title":"An AR-based Training and Assessment System for Myoelectrical Prosthetic Control","language":[{"iso":"eng"}],"type":"bachelorsthesis","year":"2017","citation":{"ieee":"C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","short":"C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control, Paderborn University, 2017.","mla":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","bibtex":"@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }","apa":"Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University.","ama":"Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University; 2017.","chicago":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017."},"_id":"10613","date_updated":"2022-01-06T06:50:47Z"},{"language":[{"iso":"eng"}],"citation":{"chicago":"Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens, and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” In Design, Automation and Test in Europe (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927137.","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={10.23919/DATE.2017.7927137}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” Design, Automation and Test in Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.","short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017.","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in Design, Automation and Test in Europe (DATE), 2017."},"year":"2017","type":"conference","doi":"10.23919/DATE.2017.7927137","date_updated":"2022-01-06T06:50:49Z","_id":"10630","date_created":"2019-07-10T11:02:56Z","status":"public","publication":"Design, Automation and Test in Europe (DATE)","department":[{"_id":"78"}],"author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"last_name":"Thombansen","first_name":"Georg","full_name":"Thombansen, Georg"},{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"full_name":"Wiens, Alex","first_name":"Alex","last_name":"Wiens"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"3118","title":"A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller"},{"title":"Acceleration of Industrial Analytics Functions on a Platform FPGA","user_id":"3118","publisher":"Paderborn University","author":[{"first_name":"Umair","full_name":"Riaz, Umair","last_name":"Riaz"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:15:10Z","_id":"10666","date_updated":"2022-01-06T06:50:49Z","citation":{"ieee":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","short":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA, Paderborn University, 2017.","bibtex":"@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017} }","mla":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","ama":"Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University; 2017.","apa":"Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University.","chicago":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017."},"type":"mastersthesis","year":"2017","supervisor":[{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"}],"language":[{"iso":"eng"}]},{"user_id":"3118","title":"Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor","status":"public","date_created":"2019-07-10T11:17:58Z","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"first_name":"Ishraq Ibne","full_name":"Ashraf, Ishraq Ibne","last_name":"Ashraf"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Proc. Design, Automation and Test in Europe Conf. (DATE)","doi":"10.23919/DATE.2017.7927096","_id":"10672","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"mla":"Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design, Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.","bibtex":"@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}, DOI={10.23919/DATE.2017.7927096}, booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017} }","apa":"Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE). https://doi.org/10.23919/DATE.2017.7927096","ama":"Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096","chicago":"Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.","ieee":"N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.","short":"N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation and Test in Europe Conf. (DATE), 2017."},"year":"2017","type":"conference"},{"user_id":"398","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","status":"public","date_created":"2019-07-10T11:22:59Z","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"department":[{"_id":"78"}],"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","doi":"10.1109/FPT.2017.8280144","date_updated":"2022-01-06T06:50:49Z","_id":"10676","language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218."},"year":"2017","page":"215-218"},{"year":"2017","type":"journal_article","citation":{"bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017} }","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017.","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES).","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) (2017)."},"_id":"10692","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:29:58Z","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"department":[{"_id":"78"}],"publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)","user_id":"3118","title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies"},{"_id":"10708","date_updated":"2022-01-06T06:50:50Z","type":"mastersthesis","year":"2017","citation":{"ieee":"A. Dietrich, Reconfigurable Cryptographic Services. Paderborn University, 2017.","short":"A. Dietrich, Reconfigurable Cryptographic Services, Paderborn University, 2017.","mla":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.","bibtex":"@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn University}, author={Dietrich, Andreas}, year={2017} }","apa":"Dietrich, A. (2017). Reconfigurable Cryptographic Services. Paderborn University.","ama":"Dietrich A. Reconfigurable Cryptographic Services. Paderborn University; 2017.","chicago":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017."},"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"title":"Reconfigurable Cryptographic Services","user_id":"3118","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Dietrich","full_name":"Dietrich, Andreas","first_name":"Andreas"}],"date_created":"2019-07-10T11:43:32Z","status":"public"},{"page":"19pp","citation":{"short":"C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017) 19pp.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, 19pp. https://doi.org/10.1049/joe.2017.0032.","ama":"Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering, 19pp. https://doi.org/10.1049/joe.2017.0032","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032}, journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={19pp} }","mla":"Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032."},"type":"journal_article","year":"2017","_id":"10740","date_updated":"2022-01-06T06:50:50Z","doi":"10.1049/joe.2017.0032","publication":"The Journal of Engineering","department":[{"_id":"78"}],"author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"date_created":"2019-07-10T11:59:38Z","status":"public","title":"Fast Network Restoration by Partitioning of Parallel Black Start Zones","user_id":"3118"},{"series_title":"Lecture Notes in Computer Science","type":"book","citation":{"ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer; 2017.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2017). Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer.","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Lecture Notes in Computer Science. Springer, 2017.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2017, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 20th European Conference, EvoApplications}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2017}, collection={Lecture Notes in Computer Science} }","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017.","short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 20th European Conference, EvoApplications, Springer, 2017.","ieee":"G. Squillero et al., Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017."},"year":"2017","date_updated":"2022-01-06T06:50:50Z","_id":"10759","department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"Squillero, Giovanni","first_name":"Giovanni","last_name":"Squillero"},{"first_name":"Paolo","full_name":"Burelli, Paolo","last_name":"Burelli"},{"full_name":"M. Mora, Antonio","first_name":"Antonio","last_name":"M. Mora"},{"full_name":"Agapitos, Alexandros","first_name":"Alexandros","last_name":"Agapitos"},{"first_name":"William","full_name":"S. Bush, William","last_name":"S. Bush"},{"last_name":"Cagnoni","full_name":"Cagnoni, Stefano","first_name":"Stefano"},{"last_name":"Cotta","first_name":"Carlos","full_name":"Cotta, Carlos"},{"first_name":"Ivanoe","full_name":"De Falco, Ivanoe","last_name":"De Falco"},{"full_name":"Della Cioppa, Antonio","first_name":"Antonio","last_name":"Della Cioppa"},{"last_name":"Divina","first_name":"Federico","full_name":"Divina, Federico"},{"last_name":"Eiben","first_name":"A.E.","full_name":"Eiben, A.E."},{"last_name":"I. Esparcia-Alc{\\'a}zar","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","first_name":"Anna"},{"full_name":"Fern{\\'a}ndez de Vega, Francisco","first_name":"Francisco","last_name":"Fern{\\'a}ndez de Vega"},{"first_name":"Kyrre","full_name":"Glette, Kyrre","last_name":"Glette"},{"first_name":"Evert","full_name":"Haasdijk, Evert","last_name":"Haasdijk"},{"first_name":"J.","full_name":"Ignacio Hidalgo, J.","last_name":"Ignacio Hidalgo"},{"last_name":"Kampouridis","first_name":"Michael","full_name":"Kampouridis, Michael"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"first_name":"Michalis","full_name":"Mavrovouniotis, Michalis","last_name":"Mavrovouniotis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"first_name":"Robert","full_name":"Schaefer, Robert","last_name":"Schaefer"},{"first_name":"Kevin","full_name":"Sim, Kevin","last_name":"Sim"},{"last_name":"Tarantino","first_name":"Ernesto","full_name":"Tarantino, Ernesto"},{"first_name":"Neil","full_name":"Urquhart, Neil","last_name":"Urquhart"},{"full_name":"Zhang (editors), Mengjie","first_name":"Mengjie","last_name":"Zhang (editors)"}],"date_created":"2019-07-10T12:06:37Z","status":"public","title":"Applications of Evolutionary Computation - 20th European Conference, EvoApplications","user_id":"3118"},{"user_id":"3118","title":"Parametrizing Cartesian Genetic Programming: An Empirical Study","date_created":"2019-07-10T12:06:38Z","status":"public","department":[{"_id":"78"}],"publication":"KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI","publisher":"Springer International Publishing","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Kalkreuth","first_name":"Roman","full_name":"Kalkreuth, Roman"}],"doi":"10.1007/978-3-319-67190-1_26","date_updated":"2022-01-06T06:50:50Z","_id":"10760","language":[{"iso":"eng"}],"citation":{"chicago":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing, 2017. https://doi.org/10.1007/978-3-319-67190-1_26.","ama":"Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26","apa":"Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26","mla":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.","bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={Parametrizing Cartesian Genetic Programming: An Empirical Study}, DOI={10.1007/978-3-319-67190-1_26}, booktitle={KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}, publisher={Springer International Publishing}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","short":"P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017.","ieee":"P. Kaufmann and R. Kalkreuth, “Parametrizing Cartesian Genetic Programming: An Empirical Study,” in KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, 2017."},"year":"2017","type":"conference"},{"user_id":"3118","title":"Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches","department":[{"_id":"78"}],"publication":"Adaptive Hardware and Systems (AHS)","publisher":"IEEE","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T12:07:01Z","status":"public","_id":"10761","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/AHS.2017.8046380","language":[{"iso":"eng"}],"year":"2017","type":"conference","citation":{"bibtex":"@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}, DOI={10.1109/AHS.2017.8046380}, booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann, Paul and Ho, Nam and Platzner, Marco}, year={2017} }","mla":"Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” Adaptive Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.","ama":"Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380","apa":"Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380","chicago":"Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” In Adaptive Hardware and Systems (AHS). IEEE, 2017. https://doi.org/10.1109/AHS.2017.8046380.","ieee":"P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,” in Adaptive Hardware and Systems (AHS), 2017.","short":"P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017."}},{"department":[{"_id":"78"}],"publication":"Genetic and Evolutionary Computation (GECCO), Compendium","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Kalkreuth","first_name":"Roman","full_name":"Kalkreuth, Roman"}],"publisher":"ACM","date_created":"2019-07-10T12:07:03Z","status":"public","user_id":"3118","title":"An Empirical Study on the Parametrization of Cartesian Genetic Programming","type":"conference","citation":{"ieee":"P. Kaufmann and R. Kalkreuth, “An Empirical Study on the Parametrization of Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), Compendium, 2017.","short":"P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017.","bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={An Empirical Study on the Parametrization of Cartesian Genetic Programming}, DOI={10.1145/3067695.3075980}, booktitle={Genetic and Evolutionary Computation (GECCO), Compendium}, publisher={ACM}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","mla":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017, doi:10.1145/3067695.3075980.","chicago":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), Compendium. ACM, 2017. https://doi.org/10.1145/3067695.3075980.","ama":"Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium. ACM; 2017. doi:10.1145/3067695.3075980","apa":"Kaufmann, P., & Kalkreuth, R. (2017). An Empirical Study on the Parametrization of Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO), Compendium. ACM. https://doi.org/10.1145/3067695.3075980"},"year":"2017","date_updated":"2022-01-06T06:50:50Z","_id":"10762","doi":"10.1145/3067695.3075980"},{"author":[{"first_name":"Zakarya","full_name":"Guettatfi, Zakarya","last_name":"Guettatfi"},{"last_name":"Hübner","first_name":"Philipp","full_name":"Hübner, Philipp"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Bernhard","full_name":"Rinner, Bernhard","last_name":"Rinner"}],"department":[{"_id":"78"}],"keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","status":"public","date_created":"2019-07-10T12:13:15Z","title":"Computational self-awareness as design approach for visual sensor nodes","user_id":"3118","type":"conference","citation":{"chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.","apa":"Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8."},"year":"2017","page":"1-8","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10780","doi":"10.1109/ReCoSoC.2017.8016147"},{"_id":"14893","date_updated":"2022-01-06T06:52:10Z","doi":"10.1007/978-3-319-62569-0_8","type":"conference","citation":{"short":"I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017.","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems,” in Communications in Computer and Information Science, 2017.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In Communications in Computer and Information Science. Cham: Springer , 2017. https://doi.org/10.1007/978-3-319-62569-0_8.","ama":"Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: Communications in Computer and Information Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In Communications in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8","mla":"Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” Communications in Computer and Information Science, Springer , 2017, doi:10.1007/978-3-319-62569-0_8.","bibtex":"@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={10.1007/978-3-319-62569-0_8}, booktitle={Communications in Computer and Information Science}, publisher={Springer }, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}, year={2017} }"},"year":"2017","language":[{"iso":"eng"}],"place":"Cham","title":"I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems","user_id":"398","publisher":"Springer ","author":[{"last_name":"Ghribi","full_name":"Ghribi, Ines","first_name":"Ines"},{"last_name":"Abdallah","first_name":"Riadh Ben","full_name":"Abdallah, Riadh Ben"},{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Communications in Computer and Information Science","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"issn":["1865-0929","1865-0937"],"isbn":["9783319625683","9783319625690"]},"status":"public","date_created":"2019-11-12T08:33:13Z"},{"user_id":"477","ddc":["040"],"abstract":[{"text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.","lang":"eng"}],"date_created":"2017-10-17T12:41:35Z","has_accepted_license":"1","status":"public","file":[{"access_level":"closed","file_name":"222-1-s2.0-S0045790616300684-main.pdf","date_created":"2018-03-21T10:36:08Z","date_updated":"2018-03-21T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":931048,"file_id":"1511","creator":"florida"}],"publication":"Computers & Electrical Engineering","file_date_updated":"2018-03-21T10:36:08Z","author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Bockhorn","first_name":"Arne","full_name":"Bockhorn, Arne"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Elsevier","_id":"222","page":"112--122","type":"journal_article","citation":{"ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers & Electrical Engineering, pp. 112--122, 2016.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering (2016) 112--122.","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={10.1016/j.compeleceng.2016.04.005}, journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005","apa":"Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005."},"year":"2016","title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"doi":"10.1016/j.compeleceng.2016.04.005","date_updated":"2022-01-06T06:55:29Z","language":[{"iso":"eng"}]},{"user_id":"14053","title":"FPGA-based acceleration of high density myoelectric signal processing","extern":"1","date_created":"2018-11-23T15:00:28Z","status":"public","publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Linus","full_name":"Witschen, Linus","last_name":"Witschen"},{"last_name":"Thombansen","full_name":"Thombansen, Georg","first_name":"Georg"},{"first_name":"Florian","full_name":"Kraus, Florian","last_name":"Kraus","id":"14053"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","doi":"10.1109/reconfig.2015.7393312","date_updated":"2022-01-06T07:02:42Z","_id":"5812","language":[{"iso":"eng"}],"year":"2016","citation":{"ama":"Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","apa":"Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. https://doi.org/10.1109/reconfig.2015.7393312","chicago":"Boschmann, Alexander, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","short":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ieee":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2016."},"type":"conference"},{"_id":"10612","date_updated":"2022-01-06T06:50:47Z","language":[{"iso":"eng"}],"year":"2016","type":"mastersthesis","citation":{"ama":"Cedric Mertens J. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University; 2016.","apa":"Cedric Mertens, J. (2016). Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University.","chicago":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","bibtex":"@book{Cedric Mertens_2016, title={Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion}, publisher={Paderborn University}, author={Cedric Mertens, Jan}, year={2016} }","mla":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","short":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion, Paderborn University, 2016.","ieee":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016."},"user_id":"3118","title":"Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion","status":"public","date_created":"2019-07-10T09:23:26Z","publisher":"Paderborn University","author":[{"last_name":"Cedric Mertens","first_name":"Jan","full_name":"Cedric Mertens, Jan"}],"department":[{"_id":"78"}]},{"title":"Implementation of Bilinear Pairings on Reconfigurable Hardware","user_id":"3118","author":[{"last_name":"Nassery","first_name":"Abdul Sami","full_name":"Nassery, Abdul Sami"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:25:14Z","_id":"10616","date_updated":"2022-01-06T06:50:47Z","citation":{"chicago":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","apa":"Nassery, A. S. (2016). Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University.","ama":"Nassery AS. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University; 2016.","bibtex":"@book{Nassery_2016, title={Implementation of Bilinear Pairings on Reconfigurable Hardware}, publisher={Paderborn University}, author={Nassery, Abdul Sami}, year={2016} }","mla":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","short":"A.S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware, Paderborn University, 2016.","ieee":"A. S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016."},"year":"2016","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}]},{"title":"Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method","user_id":"3118","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Omair","full_name":"Amin, Omair","last_name":"Amin"}],"date_created":"2019-07-10T09:25:15Z","status":"public","_id":"10617","date_updated":"2022-01-06T06:50:47Z","citation":{"ieee":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University, 2016.","short":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method, Paderborn University, 2016.","mla":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.","bibtex":"@book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }","apa":"Amin, O. (2016). Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University.","ama":"Amin O. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University; 2016.","chicago":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016."},"year":"2016","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}]},{"_id":"10622","date_updated":"2022-01-06T06:50:48Z","doi":"10.1109/DSD.2016.35","language":[{"iso":"eng"}],"type":"conference","citation":{"short":"J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.","ieee":"J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs,” in Euromicro Conference on Digital System Design (DSD), 2016.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” In Euromicro Conference on Digital System Design (DSD), 2016. https://doi.org/10.1109/DSD.2016.35.","ama":"Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System Design (DSD). ; 2016. doi:10.1109/DSD.2016.35","apa":"Anwer, J., & Platzner, M. (2016). Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In Euromicro Conference on Digital System Design (DSD). https://doi.org/10.1109/DSD.2016.35","mla":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” Euromicro Conference on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.","bibtex":"@inproceedings{Anwer_Platzner_2016, title={Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}, DOI={10.1109/DSD.2016.35}, booktitle={Euromicro Conference on Digital System Design (DSD)}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2016} }"},"year":"2016","user_id":"3118","title":"Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Euromicro Conference on Digital System Design (DSD)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:33:00Z"},{"title":"A novel immersive augmented reality system for prosthesis training and assessment","user_id":"3118","date_created":"2019-07-10T11:02:57Z","status":"public","publication":"Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)","department":[{"_id":"78"}],"author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"last_name":"Dosen","full_name":"Dosen, Strahinja","first_name":"Strahinja"},{"last_name":"Werner","first_name":"Andreas","full_name":"Werner, Andreas"},{"full_name":"Raies, Ali","first_name":"Ali","last_name":"Raies"},{"last_name":"Farina","first_name":"Dario","full_name":"Farina, Dario"}],"_id":"10631","date_updated":"2022-01-06T06:50:49Z","citation":{"ieee":"A. Boschmann, S. Dosen, A. Werner, A. Raies, and D. Farina, “A novel immersive augmented reality system for prosthesis training and assessment,” in Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","short":"A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","bibtex":"@inproceedings{Boschmann_Dosen_Werner_Raies_Farina_2016, title={A novel immersive augmented reality system for prosthesis training and assessment}, booktitle={Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)}, author={Boschmann, Alexander and Dosen, Strahinja and Werner, Andreas and Raies, Ali and Farina, Dario}, year={2016} }","mla":"Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","ama":"Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016.","apa":"Boschmann, A., Dosen, S., Werner, A., Raies, A., & Farina, D. (2016). A novel immersive augmented reality system for prosthesis training and assessment. In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI).","chicago":"Boschmann, Alexander, Strahinja Dosen, Andreas Werner, Ali Raies, and Dario Farina. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016."},"type":"conference","year":"2016"},{"intvolume":" 644","_id":"10661","date_updated":"2022-01-06T06:50:49Z","doi":"10.1016/j.tcs.2016.06.029","page":"53-62","year":"2016","type":"journal_article","citation":{"short":"T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62.","ieee":"T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science 644 (2016): 53–62. https://doi.org/10.1016/j.tcs.2016.06.029.","apa":"Graf, T., & Platzner, M. (2016). Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science, 644, 53–62. https://doi.org/10.1016/j.tcs.2016.06.029","ama":"Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62. doi:10.1016/j.tcs.2016.06.029","bibtex":"@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029."},"language":[{"iso":"eng"}],"title":"Adaptive playouts for online learning of policies during Monte Carlo Tree Search","user_id":"3118","publication":"Journal Theoretical Computer Science","department":[{"_id":"78"}],"publisher":"Elsevier","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"volume":644,"date_created":"2019-07-10T11:14:43Z","status":"public"},{"date_created":"2019-07-10T11:30:20Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Jens","full_name":"Horstmann, Jens","last_name":"Horstmann"}],"title":"Beschleunigte Simulation elektrischer Stromnetze mit GPUs","user_id":"3118","type":"bachelorsthesis","citation":{"bibtex":"@book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }","mla":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","apa":"Horstmann, J. (2016). Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University.","ama":"Horstmann J. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University; 2016.","chicago":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","ieee":"J. Horstmann, Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University, 2016.","short":"J. Horstmann, Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs, Paderborn University, 2016."},"year":"2016","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10695"},{"title":"Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control","user_id":"3118","author":[{"last_name":"Ma","full_name":"Ma, Chenjie","first_name":"Chenjie"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"J.-Christian","full_name":"Töbermann, J.-Christian","last_name":"Töbermann"},{"first_name":"Martin","full_name":"Braun, Martin","last_name":"Braun"}],"publisher":"Elsevier","department":[{"_id":"78"}],"publication":"Renewable Energy","volume":87,"status":"public","date_created":"2019-07-10T11:42:59Z","date_updated":"2022-01-06T06:50:50Z","_id":"10705","intvolume":" 87","doi":"10.1016/j.renene.2015.07.083","issue":"(part 2)","year":"2016","citation":{"chicago":"Ma, Chenjie, Paul Kaufmann, J.-Christian Töbermann, and Martin Braun. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy 87, no. (part 2) (2016): 946–53. https://doi.org/10.1016/j.renene.2015.07.083.","apa":"Ma, C., Kaufmann, P., Töbermann, J.-C., & Braun, M. (2016). Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy, 87((part 2)), 946–953. https://doi.org/10.1016/j.renene.2015.07.083","ama":"Ma C, Kaufmann P, Töbermann J-C, Braun M. Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy. 2016;87((part 2)):946-953. doi:10.1016/j.renene.2015.07.083","mla":"Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083.","bibtex":"@article{Ma_Kaufmann_Töbermann_Braun_2016, title={Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}, volume={87}, DOI={10.1016/j.renene.2015.07.083}, number={(part 2)}, journal={Renewable Energy}, publisher={Elsevier}, author={Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}, year={2016}, pages={946–953} }","short":"C. Ma, P. Kaufmann, J.-C. Töbermann, M. Braun, Renewable Energy 87 (2016) 946–953.","ieee":"C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016."},"type":"journal_article","page":"946-953","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"type":"mastersthesis","year":"2016","citation":{"chicago":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","ama":"Makeswaran V. Operating System Support for Reconfigurable Cache. Paderborn University; 2016.","apa":"Makeswaran, V. (2016). Operating System Support for Reconfigurable Cache. Paderborn University.","mla":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","bibtex":"@book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }","short":"V. Makeswaran, Operating System Support for Reconfigurable Cache, Paderborn University, 2016.","ieee":"V. Makeswaran, Operating System Support for Reconfigurable Cache. Paderborn University, 2016."},"_id":"10706","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"author":[{"last_name":"Makeswaran","full_name":"Makeswaran, Vignesh","first_name":"Vignesh"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:43:30Z","status":"public","user_id":"3118","title":"Operating System Support for Reconfigurable Cache"},{"user_id":"3118","title":"Private/Shared Data Classification and Implementation for a Multi-Softcore Platform","department":[{"_id":"78"}],"author":[{"full_name":"Ibne Ashraf, Ishraq","first_name":"Ishraq","last_name":"Ibne Ashraf"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:43:31Z","status":"public","date_updated":"2022-01-06T06:50:50Z","_id":"10707","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"type":"mastersthesis","year":"2016","citation":{"ama":"Ibne Ashraf I. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University; 2016.","apa":"Ibne Ashraf, I. (2016). Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University.","chicago":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","bibtex":"@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }","mla":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","short":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform, Paderborn University, 2016.","ieee":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016."}},{"_id":"10712","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/ReConFig.2016.7857193","series_title":"ReConFig","language":[{"iso":"eng"}],"page":"1-8","year":"2016","type":"conference","citation":{"ieee":"S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on, 2016, pp. 1–8.","short":"S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.","bibtex":"@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={10.1109/ReConFig.2016.7857193}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 1–8. ReConFig, 2016. https://doi.org/10.1109/ReConFig.2016.7857193.","ama":"Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193","apa":"Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193"},"user_id":"3118","title":"Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level","department":[{"_id":"78"}],"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on","author":[{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:47:25Z","status":"public"},{"citation":{"short":"M. Schmidt, Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung, Paderborn University, 2016.","ieee":"M. Schmidt, Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University, 2016.","apa":"Schmidt, M. (2016). Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University.","ama":"Schmidt M. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University; 2016.","chicago":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","mla":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","bibtex":"@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }"},"year":"2016","type":"bachelorsthesis","language":[{"iso":"eng"}],"_id":"10755","date_updated":"2022-01-06T06:50:50Z","publisher":"Paderborn University","author":[{"last_name":"Schmidt","full_name":"Schmidt, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:05:20Z","title":"Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung","user_id":"3118"},{"title":"Applications of Evolutionary Computation - 19th European Conference, EvoApplications","user_id":"3118","department":[{"_id":"78"}],"publisher":"Springer","author":[{"last_name":"Squillero","full_name":"Squillero, Giovanni","first_name":"Giovanni"},{"full_name":"Burelli, Paolo","first_name":"Paolo","last_name":"Burelli"},{"full_name":"M. Mora, Antonio","first_name":"Antonio","last_name":"M. Mora"},{"full_name":"Agapitos, Alexandros","first_name":"Alexandros","last_name":"Agapitos"},{"last_name":"S. Bush","first_name":"William","full_name":"S. Bush, William"},{"first_name":"Stefano","full_name":"Cagnoni, Stefano","last_name":"Cagnoni"},{"full_name":"Cotta, Carlos","first_name":"Carlos","last_name":"Cotta"},{"last_name":"De Falco","full_name":"De Falco, Ivanoe","first_name":"Ivanoe"},{"full_name":"Della Cioppa, Antonio","first_name":"Antonio","last_name":"Della Cioppa"},{"full_name":"Divina, Federico","first_name":"Federico","last_name":"Divina"},{"last_name":"Eiben","full_name":"Eiben, A.E.","first_name":"A.E."},{"first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco","last_name":"Fern{\\'a}ndez de Vega"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"full_name":"Haasdijk, Evert","first_name":"Evert","last_name":"Haasdijk"},{"full_name":"Ignacio Hidalgo, J.","first_name":"J.","last_name":"Ignacio Hidalgo"},{"last_name":"Kampouridis","full_name":"Kampouridis, Michael","first_name":"Michael"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Mavrovouniotis","full_name":"Mavrovouniotis, Michalis","first_name":"Michalis"},{"first_name":"Trung","full_name":"Thanh Nguyen, Trung","last_name":"Thanh Nguyen"},{"full_name":"Schaefer, Robert","first_name":"Robert","last_name":"Schaefer"},{"first_name":"Kevin","full_name":"Sim, Kevin","last_name":"Sim"},{"full_name":"Tarantino, Ernesto","first_name":"Ernesto","last_name":"Tarantino"},{"full_name":"Urquhart, Neil","first_name":"Neil","last_name":"Urquhart"},{"full_name":"Zhang (editors), Mengjie","first_name":"Mengjie","last_name":"Zhang (editors)"}],"volume":9597,"date_created":"2019-07-10T12:06:36Z","status":"public","intvolume":" 9597","_id":"10758","date_updated":"2022-01-06T06:50:50Z","series_title":"Lecture Notes in Computer Science","citation":{"short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 19th European Conference, EvoApplications, Springer, 2016.","ieee":"G. Squillero et al., Applications of Evolutionary Computation - 19th European Conference, EvoApplications, vol. 9597. Springer, 2016.","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597. Lecture Notes in Computer Science. Springer, 2016.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2016). Applications of Evolutionary Computation - 19th European Conference, EvoApplications (Vol. 9597). Springer.","ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol 9597. Springer; 2016.","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597, Springer, 2016.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2016, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 19th European Conference, EvoApplications}, volume={9597}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2016}, collection={Lecture Notes in Computer Science} }"},"year":"2016","type":"book"},{"user_id":"3118","title":"RCo-Design: New Visual Environment for Reconfigurable Embedded Systems","status":"public","date_created":"2019-07-10T12:07:54Z","author":[{"last_name":"Ghribi","full_name":"Ghribi, Ines","first_name":"Ines"},{"full_name":"Ben Abdallah, Riadh","first_name":"Riadh","last_name":"Ben Abdallah"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings of the 30th European Simulation and Modelling Conference (ESM)","department":[{"_id":"78"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10766","language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }","mla":"Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In Proceedings of the 30th European Simulation and Modelling Conference (ESM).","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016."},"year":"2016"},{"language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }","mla":"Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 185–95, 2016.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195).","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195."},"page":"185-195","_id":"10768","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Ghribi","full_name":"Ghribi, Ines","first_name":"Ines"},{"first_name":"Riadh","full_name":"Ben Abdallah, Riadh","last_name":"Ben Abdallah"},{"last_name":"Khalgui","first_name":"Mohamed","full_name":"Khalgui, Mohamed"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:07:56Z","user_id":"3118","title":"New Co-design Methodology for Real-time Embedded Systems"},{"author":[{"last_name":"Ghasemzadeh Mohammadi","id":"61186","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"last_name":"Gaillardon","first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel"},{"first_name":"Giovanni","full_name":"De Micheli, Giovanni","last_name":"De Micheli"}],"publisher":"IEEE","publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:08:14Z","volume":"PP","extern":"1","user_id":"3118","title":"Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation","language":[{"iso":"eng"}],"year":"2016","type":"journal_article","citation":{"bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1."},"page":"1-1","_id":"10769","date_updated":"2022-01-06T06:50:50Z","issue":"99","doi":"10.1109/TCAD.2016.2547908"},{"language":[{"iso":"eng"}],"citation":{"apa":"Hermansen, S. (2016). Custom Memory Controller for ReconOS. Paderborn University.","ama":"Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016.","chicago":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.","mla":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.","bibtex":"@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }","short":"S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016.","ieee":"S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016."},"year":"2016","type":"bachelorsthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10781","date_created":"2019-07-10T12:13:16Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Sven","full_name":"Hermansen, Sven","last_name":"Hermansen"}],"user_id":"3118","title":"Custom Memory Controller for ReconOS"},{"department":[{"_id":"78"}],"publisher":"Springer","date_created":"2019-08-27T13:39:43Z","status":"public","publication_identifier":{"issn":["1619-7127"],"isbn":["9783319396743","9783319396750"]},"publication_status":"published","editor":[{"first_name":"Peter R.","full_name":"Lewis, Peter R.","last_name":"Lewis"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"},{"last_name":"Tørresen","full_name":"Tørresen, Jim","first_name":"Jim"},{"full_name":"Yao, Xin","first_name":"Xin","last_name":"Yao"}],"abstract":[{"lang":"eng","text":"Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering."}],"place":"Cham","user_id":"398","title":"Self-aware Computing Systems: An Engineering Approach","language":[{"iso":"eng"}],"year":"2016","type":"book_editor","citation":{"mla":"Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.","bibtex":"@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={10.1007/978-3-319-39675-0}, publisher={Springer}, year={2016} }","ama":"Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0","apa":"Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., & Yao, X. (Eds.). (2016). Self-aware Computing Systems: An Engineering Approach. Cham: Springer. https://doi.org/10.1007/978-3-319-39675-0","chicago":"Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer, 2016. https://doi.org/10.1007/978-3-319-39675-0.","ieee":"P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.","short":"P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016."},"date_updated":"2022-01-06T06:51:27Z","_id":"12972","doi":"10.1007/978-3-319-39675-0"},{"title":"FPGA-based acceleration of high density myoelectric signal processing","user_id":"49051","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"last_name":"Thombansen","full_name":"Thombansen, Georg","first_name":"Georg"},{"last_name":"Kraus","full_name":"Kraus, Florian","first_name":"Florian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","keyword":["Electromyography","Feature extraction","Delays","Hardware Pattern recognition","Prosthetics","High definition video"],"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["9781467394062"]},"status":"public","date_created":"2020-02-11T07:48:56Z","date_updated":"2022-01-06T06:52:38Z","_id":"15873","conference":{"location":"Mexiko City, Mexiko","name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"},"doi":"10.1109/reconfig.2015.7393312","type":"conference","citation":{"apa":"Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312","ama":"Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","chicago":"Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","short":"A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ieee":"A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016."},"year":"2016","language":[{"iso":"eng"}]},{"user_id":"398","title":"Using Deep Convolutional Neural Networks in Monte Carlo Tree Search","department":[{"_id":"78"}],"publication":"Computer and Games","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2019-09-09T09:01:09Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","_id":"13151","date_updated":"2022-01-06T06:51:29Z","language":[{"iso":"eng"}],"year":"2016","type":"conference","citation":{"ieee":"T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016.","short":"T. Graf, M. Platzner, in: Computer and Games, 2016.","mla":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","chicago":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In Computer and Games, 2016.","apa":"Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games.","ama":"Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016."}},{"title":"Monte-Carlo Simulation Balancing Revisited","user_id":"398","status":"public","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2019-09-09T09:06:39Z","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"IEEE Computational Intelligence and Games","_id":"13152","date_updated":"2022-01-06T06:51:29Z","type":"conference","citation":{"bibtex":"@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","mla":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In IEEE Computational Intelligence and Games, 2016.","apa":"Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games.","ama":"Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.","ieee":"T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016.","short":"T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016."},"year":"2016","language":[{"iso":"eng"}]},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"title":"Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware","language":[{"iso":"eng"}],"doi":"10.1109/ReCoSoC.2016.7533910","date_updated":"2022-01-06T06:51:30Z","date_created":"2017-10-17T12:41:17Z","has_accepted_license":"1","status":"public","file":[{"file_name":"132-07533910.pdf","date_created":"2018-03-21T13:02:30Z","access_level":"closed","file_size":911171,"creator":"florida","file_id":"1562","date_updated":"2018-03-21T13:02:30Z","content_type":"application/pdf","relation":"main_file","success":1}],"publication":"Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)","file_date_updated":"2018-03-21T13:02:30Z","author":[{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"user_id":"477","ddc":["040"],"abstract":[{"lang":"eng","text":"Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module."}],"page":"1--8","citation":{"chicago":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910.","apa":"Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910","ama":"Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910","bibtex":"@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }","mla":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910.","short":"T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","ieee":"T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8."},"type":"conference","year":"2016","_id":"132"},{"abstract":[{"lang":"eng","text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems."}],"user_id":"15278","publication":"FPGAs for Software Programmers","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"}],"publisher":"Springer International Publishing","quality_controlled":"1","date_created":"2017-07-26T15:07:06Z","status":"public","_id":"29","page":"227-244","type":"book_chapter","citation":{"bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244."},"year":"2016","place":"Cham","title":"ReconOS","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"publication_status":"published","editor":[{"first_name":"Dirk","full_name":"Koch, Dirk","last_name":"Koch"},{"first_name":"Frank","full_name":"Hannig, Frank","last_name":"Hannig"},{"last_name":"Ziener","first_name":"Daniel","full_name":"Ziener, Daniel"}],"date_updated":"2023-09-26T13:25:38Z","doi":"10.1007/978-3-319-26408-0_13","language":[{"iso":"eng"}]},{"date_updated":"2023-09-26T13:27:44Z","doi":"10.1007/978-3-319-39675-0_8","series_title":"Natural Computing Series (NCS)","language":[{"iso":"eng"}],"place":"Cham","title":"Self-aware Compute Nodes","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"_id":"156","citation":{"chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165."},"year":"2016","type":"book_chapter","page":"145-165","abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"content_type":"application/pdf","date_updated":"2018-11-14T13:20:32Z","success":1,"relation":"main_file","file_size":833054,"file_id":"5613","creator":"aloesch","access_level":"closed","date_created":"2018-11-14T13:20:32Z","file_name":"chapter8.pdf"}],"publisher":"Springer International Publishing","quality_controlled":"1","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Self-aware Computing Systems","file_date_updated":"2018-11-14T13:20:32Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:22Z"},{"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"date_created":"2017-10-17T12:41:24Z","has_accepted_license":"1","status":"public","file":[{"access_level":"closed","date_created":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf","creator":"florida","file_id":"1541","file_size":261356}],"publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2018-03-21T12:41:55Z","quality_controlled":"1","publisher":"EDA Consortium / IEEE","author":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"_id":"168","page":"912-917","type":"conference","citation":{"ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016."},"year":"2016"},{"_id":"269","type":"conference","year":"2015","citation":{"chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32.","apa":"Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32","ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.","bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }","short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372."},"page":"365--372","abstract":[{"lang":"eng","text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level."}],"user_id":"477","ddc":["040"],"file":[{"file_name":"269-paper_53.pdf","date_created":"2018-03-21T09:32:42Z","access_level":"closed","file_id":"1477","creator":"florida","file_size":344309,"success":1,"relation":"main_file","date_updated":"2018-03-21T09:32:42Z","content_type":"application/pdf"}],"author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Wu","full_name":"Wu, Sen","first_name":"Sen"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","file_date_updated":"2018-03-21T09:32:42Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:44Z","date_updated":"2022-01-06T06:57:30Z","doi":"10.1007/978-3-319-16214-0_32","series_title":"LNCS","language":[{"iso":"eng"}],"title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"}]},{"publisher":"Universität Paderborn","author":[{"first_name":"Christoph","full_name":"Knorr, Christoph","last_name":"Knorr"}],"department":[{"_id":"78"}],"status":"public","date_created":"2018-06-26T14:06:07Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"}],"title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","user_id":"477","citation":{"ieee":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","mla":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","ama":"Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.","apa":"Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn.","chicago":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015."},"type":"bachelorsthesis","year":"2015","supervisor":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"language":[{"iso":"ger"}],"_id":"3364","date_updated":"2022-01-06T06:59:13Z"},{"ddc":["000"],"user_id":"16153","volume":48,"has_accepted_license":"1","status":"public","date_created":"2018-03-23T14:06:12Z","author":[{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Yao","first_name":"Xin","full_name":"Yao, Xin"}],"publisher":"IEEE Computer Society","publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"file_date_updated":"2018-11-02T15:47:45Z","file":[{"date_created":"2018-11-02T15:47:45Z","file_name":"07163237.pdf","access_level":"closed","file_size":5605009,"creator":"ups","file_id":"5313","date_updated":"2018-11-02T15:47:45Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"issue":"7","intvolume":" 48","_id":"1772","type":"journal_article","year":"2015","citation":{"bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20."},"page":"18-20","title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}]},{"citation":{"apa":"Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University.","ama":"Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.","chicago":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","mla":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }","short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.","ieee":"A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015."},"year":"2015","type":"mastersthesis","supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"_id":"10615","date_updated":"2022-01-06T06:50:47Z","date_created":"2019-07-10T09:25:13Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi","first_name":"Abdullah Fathi"}],"publisher":"Paderborn University","title":"Self-Optimizing Organic Cache","user_id":"3118"},{"_id":"10624","date_updated":"2022-01-06T06:50:48Z","supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"type":"dissertation","year":"2015","citation":{"chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015."},"page":"183","place":"Berlin","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"status":"public","project":[{"grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_created":"2019-07-10T09:36:58Z","publication_identifier":{"isbn":["978-3-8325-4155-2"]}},{"status":"public","date_created":"2019-07-10T11:15:13Z","author":[{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"user_id":"3118","title":"Evolution of Heat Flow Prediction Models for FPGA Devices","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"year":"2015","type":"mastersthesis","citation":{"ieee":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015.","bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","mla":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","chicago":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","ama":"Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.","apa":"Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University."},"date_updated":"2022-01-06T06:50:49Z","_id":"10668"},{"user_id":"3118","title":"Computer Vision basierte Klassifikation von HD EMG Signalen","department":[{"_id":"78"}],"author":[{"last_name":"Haupt","first_name":"Christian","full_name":"Haupt, Christian"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:17:57Z","status":"public","_id":"10671","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"}],"year":"2015","citation":{"short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015.","ieee":"C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","ama":"Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.","apa":"Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University.","chicago":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","mla":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }"},"type":"mastersthesis"},{"title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","user_id":"3118","status":"public","date_created":"2019-07-10T11:18:00Z","project":[{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"full_name":"Ahmed, Abdullah Fathi","first_name":"Abdullah Fathi","last_name":"Ahmed"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"department":[{"_id":"78"}],"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","doi":"10.1109/AHS.2015.7231178","_id":"10673","date_updated":"2022-01-06T06:50:49Z","year":"2015","citation":{"short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178."},"type":"conference","page":"1-7","language":[{"iso":"eng"}]},{"page":"409-416","citation":{"bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }","mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.","apa":"Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM.","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.","chicago":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic and Evolutionary Computation (GECCO), 409–16. ACM, 2015.","ieee":"P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416.","short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416."},"year":"2015","type":"conference","_id":"10693","date_updated":"2022-01-06T06:50:49Z","publication":"Genetic and Evolutionary Computation (GECCO)","department":[{"_id":"78"}],"publisher":"ACM","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"}],"date_created":"2019-07-10T11:30:00Z","status":"public","user_id":"3118","title":"Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing"},{"doi":"10.1109/FPT.2015.7393153","date_updated":"2022-01-06T06:50:50Z","_id":"10711","language":[{"iso":"eng"}],"page":"212-215","citation":{"ieee":"S. Meisner and M. Platzner, “Comparison of thread signatures for error detection in hybrid multi-cores,” in Field Programmable Technology (FPT), 2015 International Conference on, 2015, pp. 212–215.","short":"S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215.","mla":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.","bibtex":"@inproceedings{Meisner_Platzner_2015, series={FPT}, title={Comparison of thread signatures for error detection in hybrid multi-cores}, DOI={10.1109/FPT.2015.7393153}, booktitle={Field Programmable Technology (FPT), 2015 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2015}, pages={212–215}, collection={FPT} }","apa":"Meisner, S., & Platzner, M. (2015). Comparison of thread signatures for error detection in hybrid multi-cores. In Field Programmable Technology (FPT), 2015 International Conference on (pp. 212–215). https://doi.org/10.1109/FPT.2015.7393153","ama":"Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153","chicago":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” In Field Programmable Technology (FPT), 2015 International Conference On, 212–15. FPT, 2015. https://doi.org/10.1109/FPT.2015.7393153."},"year":"2015","type":"conference","series_title":"FPT","user_id":"3118","title":"Comparison of thread signatures for error detection in hybrid multi-cores","date_created":"2019-07-10T11:47:24Z","status":"public","department":[{"_id":"78"}],"publication":"Field Programmable Technology (FPT), 2015 International Conference on","author":[{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}]},{"user_id":"477","title":"Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs","status":"public","date_created":"2019-07-10T11:48:25Z","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"}],"author":[{"last_name":"Meißner","first_name":"Roland","full_name":"Meißner, Roland"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10714","supervisor":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"language":[{"iso":"eng"}],"citation":{"bibtex":"@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }","mla":"Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.","apa":"Meißner, R. (2015). Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn.","ama":"Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015.","chicago":"Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.","ieee":"R. Meißner, Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn, 2015.","short":"R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs, Universität Paderborn, 2015."},"type":"bachelorsthesis","year":"2015"},{"date_created":"2019-07-10T11:54:44Z","status":"public","department":[{"_id":"78"}],"author":[{"first_name":"Thorbjörn","full_name":"Posewsky, Thorbjörn","last_name":"Posewsky"}],"publisher":"Paderborn University","title":"Acceleration of Artificial Neural Networks on a Zynq Platform","user_id":"3118","year":"2015","citation":{"ieee":"T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","short":"T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform, Paderborn University, 2015.","mla":"Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","bibtex":"@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }","chicago":"Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.","apa":"Posewsky, T. (2015). Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University.","ama":"Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015."},"type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10726"},{"date_created":"2019-07-10T12:06:35Z","status":"public","volume":9028,"department":[{"_id":"78"}],"author":[{"first_name":"Antonio","full_name":"M. Mora, Antonio","last_name":"M. Mora"},{"first_name":"Giovanni","full_name":"Squillero, Giovanni","last_name":"Squillero"},{"first_name":"Alexandros","full_name":"Agapitos, Alexandros","last_name":"Agapitos"},{"full_name":"Burelli, Paolo","first_name":"Paolo","last_name":"Burelli"},{"last_name":"S. Bush","full_name":"S. Bush, William","first_name":"William"},{"full_name":"Cagnoni, Stefano","first_name":"Stefano","last_name":"Cagnoni"},{"full_name":"Cotta, Carlos","first_name":"Carlos","last_name":"Cotta"},{"first_name":"Ivanoe","full_name":"De Falco, Ivanoe","last_name":"De Falco"},{"full_name":"Della Cioppa, Antonio","first_name":"Antonio","last_name":"Della Cioppa"},{"last_name":"Divina","first_name":"Federico","full_name":"Divina, Federico"},{"full_name":"Eiben, A.E.","first_name":"A.E.","last_name":"Eiben"},{"last_name":"I. Esparcia-Alc{\\'a}zar","first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna"},{"first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco","last_name":"Fern{\\'a}ndez de Vega"},{"first_name":"Kyrre","full_name":"Glette, Kyrre","last_name":"Glette"},{"last_name":"Haasdijk","first_name":"Evert","full_name":"Haasdijk, Evert"},{"last_name":"Ignacio Hidalgo","full_name":"Ignacio Hidalgo, J.","first_name":"J."},{"full_name":"Kampouridis, Michael","first_name":"Michael","last_name":"Kampouridis"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Mavrovouniotis, Michalis","first_name":"Michalis","last_name":"Mavrovouniotis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"full_name":"Schaefer, Robert","first_name":"Robert","last_name":"Schaefer"},{"last_name":"Sim","first_name":"Kevin","full_name":"Sim, Kevin"},{"last_name":"Tarantino","full_name":"Tarantino, Ernesto","first_name":"Ernesto"},{"last_name":"Urquhart","first_name":"Neil","full_name":"Urquhart, Neil"},{"full_name":"Zhang (editors), Mengjie","first_name":"Mengjie","last_name":"Zhang (editors)"}],"publisher":"Springer","user_id":"3118","title":"Applications of Evolutionary Computation - 18th European Conference, EvoApplications","place":"Copenhagen, Denmark","type":"book","year":"2015","citation":{"chicago":"M. Mora, Antonio, Giovanni Squillero, Alexandros Agapitos, Paolo Burelli, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028. Lecture Notes in Computer Science. Copenhagen, Denmark: Springer, 2015.","ama":"M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.","apa":"M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2015). Applications of Evolutionary Computation - 18th European Conference, EvoApplications (Vol. 9028). Copenhagen, Denmark: Springer.","mla":"M. Mora, Antonio, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028, Springer, 2015.","bibtex":"@book{M. Mora_Squillero_Agapitos_Burelli_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2015, place={Copenhagen, Denmark}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 18th European Conference, EvoApplications}, volume={9028}, publisher={Springer}, author={M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2015}, collection={Lecture Notes in Computer Science} }","short":"A. M. Mora, G. Squillero, A. Agapitos, P. Burelli, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 18th European Conference, EvoApplications, Springer, Copenhagen, Denmark, 2015.","ieee":"A. M. Mora et al., Applications of Evolutionary Computation - 18th European Conference, EvoApplications, vol. 9028. Copenhagen, Denmark: Springer, 2015."},"series_title":"Lecture Notes in Computer Science","intvolume":" 9028","_id":"10757","date_updated":"2022-01-06T06:50:50Z"},{"user_id":"3118","title":"Significant papers from the first 25 years of the FPL conference","date_created":"2019-07-10T12:07:53Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)","author":[{"last_name":"H.W. Leong","first_name":"Philip","full_name":"H.W. Leong, Philip"},{"last_name":"Amano","first_name":"Hideharu","full_name":"Amano, Hideharu"},{"full_name":"Anderson, Jason","first_name":"Jason","last_name":"Anderson"},{"last_name":"Bertels","full_name":"Bertels, Koen","first_name":"Koen"},{"last_name":"M.P. Cardoso","first_name":"Jo\\~ao","full_name":"M.P. Cardoso, Jo\\~ao"},{"first_name":"Oliver","full_name":"Diessel, Oliver","last_name":"Diessel"},{"full_name":"Gogniat, Guy","first_name":"Guy","last_name":"Gogniat"},{"full_name":"Hutton, Mike","first_name":"Mike","last_name":"Hutton"},{"full_name":"Lee, JunKyu","first_name":"JunKyu","last_name":"Lee"},{"last_name":"Luk","first_name":"Wayne","full_name":"Luk, Wayne"},{"first_name":"Patrick","full_name":"Lysaght, Patrick","last_name":"Lysaght"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Viktor","full_name":"K. Prasanna, Viktor","last_name":"K. Prasanna"},{"first_name":"Tero","full_name":"Rissa, Tero","last_name":"Rissa"},{"first_name":"Cristina","full_name":"Silvano, Cristina","last_name":"Silvano"},{"first_name":"Hayden","full_name":"So, Hayden","last_name":"So"},{"first_name":"Yu","full_name":"Wang, Yu","last_name":"Wang"}],"publisher":"Imperial College","doi":"10.1109/FPL.2015.7293747","date_updated":"2022-01-06T06:50:50Z","_id":"10765","language":[{"iso":"eng"}],"page":"1-3","type":"conference","year":"2015","citation":{"mla":"H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.” Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3, doi:10.1109/FPL.2015.7293747.","bibtex":"@inproceedings{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2015, title={Significant papers from the first 25 years of the FPL conference}, DOI={10.1109/FPL.2015.7293747}, booktitle={Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2015}, pages={1–3} }","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1–3). Imperial College. https://doi.org/10.1109/FPL.2015.7293747","ama":"H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~ao M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “Significant Papers from the First 25 Years of the FPL Conference.” In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 1–3. Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293747.","ieee":"P. H.W. Leong et al., “Significant papers from the first 25 years of the FPL conference,” in Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–3.","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3."}},{"status":"public","date_created":"2019-07-10T12:07:55Z","author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"last_name":"Ben Abdallah","full_name":"Ben Abdallah, Riadh","first_name":"Riadh"},{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 29th European Simulation and Modelling Conference (ESM)","title":"New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software","user_id":"3118","type":"conference","year":"2015","citation":{"bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2015, title={New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}, booktitle={Proceedings of the 29th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2015} }","mla":"Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In Proceedings of the 29th European Simulation and Modelling Conference (ESM).","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” In Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,” in Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015."},"language":[{"iso":"eng"}],"_id":"10767","date_updated":"2022-01-06T06:50:50Z"},{"volume":14,"status":"public","date_created":"2019-07-10T12:08:15Z","author":[{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"last_name":"Gaillardon","full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"IEEE Transactions on Nanotechnology","title":"From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires","user_id":"3118","extern":"1","year":"2015","citation":{"ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126. https://doi.org/10.1109/TNANO.2015.2482359","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology 14, no. 6 (2015): 1117–26. https://doi.org/10.1109/TNANO.2015.2482359."},"type":"journal_article","page":"1117-1126","language":[{"iso":"eng"}],"doi":"10.1109/TNANO.2015.2482359","issue":"6","_id":"10770","intvolume":" 14","date_updated":"2022-01-06T06:50:50Z"},{"user_id":"3118","title":"On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors","extern":"1","date_created":"2019-07-10T12:08:16Z","status":"public","department":[{"_id":"78"}],"publication":"2015 IEEE Computer Society Annual Symposium on VLSI","publisher":"IEEE","author":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"last_name":"Zhang","full_name":"Zhang, Jian","first_name":"Jian"},{"last_name":"De Micheli","full_name":"De Micheli, Giovanni","first_name":"Giovanni"},{"last_name":"Sanchez","full_name":"Sanchez, Eduardo","first_name":"Eduardo"},{"last_name":"Reorda","first_name":"Matteo Sonza","full_name":"Reorda, Matteo Sonza"}],"doi":"10.1109/ISVLSI.2015.13","_id":"10771","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"page":"491-496","year":"2015","type":"conference","citation":{"chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” In 2015 IEEE Computer Society Annual Symposium on VLSI, 491–96. IEEE, 2015. https://doi.org/10.1109/ISVLSI.2015.13.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015, title={On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}, DOI={10.1109/ISVLSI.2015.13}, booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}, year={2015}, pages={491–496} }","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 491–496."}},{"language":[{"iso":"eng"}],"citation":{"apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition (pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” In Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, 453–58. EDA Consortium, 2015. https://doi.org/10.7873/DATE.2015.0428.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault modeling in controllable polarity silicon nanowire circuits}, DOI={10.7873/DATE.2015.0428}, booktitle={Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={453–458} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, EDA Consortium, 2015, pp. 453–58, doi:10.7873/DATE.2015.0428.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, EDA Consortium, 2015, pp. 453–458.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling in controllable polarity silicon nanowire circuits,” in Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition, 2015, pp. 453–458."},"type":"conference","year":"2015","page":"453-458","_id":"10772","date_updated":"2022-01-06T06:50:50Z","doi":"10.7873/DATE.2015.0428","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"Gaillardon","full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel"},{"last_name":"De Micheli","full_name":"De Micheli, Giovanni","first_name":"Giovanni"}],"publisher":"EDA Consortium","publication":"Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:08:17Z","extern":"1","user_id":"3118","title":"Fault modeling in controllable polarity silicon nanowire circuits"},{"doi":"10.1109/FPL.2015.7293994","date_updated":"2022-01-06T06:50:50Z","_id":"10779","year":"2015","type":"conference","citation":{"chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293994.","apa":"Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015."},"language":[{"iso":"eng"}],"title":"Over effective hard real-time hardware tasks scheduling and allocation","user_id":"398","extern":"1","publication_identifier":{"issn":["1946-147X"]},"status":"public","date_created":"2019-07-10T12:11:36Z","publisher":"Imperial College","author":[{"last_name":"Guettatfi","first_name":"Zakarya","full_name":"Guettatfi, Zakarya"},{"last_name":"Kermia","first_name":"Omar","full_name":"Kermia, Omar"},{"first_name":"Abdelhakim","full_name":"Khouas, Abdelhakim","last_name":"Khouas"}],"department":[{"_id":"78"}],"keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"publication":"25th International Conference on Field Programmable Logic and Applications (FPL)"},{"_id":"13153","date_updated":"2022-01-06T06:51:29Z","doi":"10.1007/978-3-319-27992-3_1","page":"1-11","year":"2015","type":"conference","citation":{"short":"T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11.","ieee":"T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 2015, pp. 1–11.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 1–11. Springer International Publishing, 2015. https://doi.org/10.1007/978-3-319-27992-3_1.","ama":"Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1","apa":"Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing. https://doi.org/10.1007/978-3-319-27992-3_1","bibtex":"@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}, DOI={10.1007/978-3-319-27992-3_1}, booktitle={Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015}, pages={1–11} }","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1."},"language":[{"iso":"eng"}],"title":"Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning","user_id":"40778","publication":"Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers","department":[{"_id":"78"}],"author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer International Publishing","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2019-09-09T09:07:46Z","status":"public"},{"abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-20T07:47:56Z","publication":"International Journal of Reconfigurable Computing (IJRC)","publisher":"Hindawi","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","file":[{"access_level":"closed","file_name":"296-859425.pdf","date_created":"2018-03-20T07:47:56Z","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:47:56Z","creator":"florida","file_id":"1444","file_size":2993898}],"volume":2015,"date_created":"2017-10-17T12:41:49Z","has_accepted_license":"1","status":"public","_id":"296","intvolume":" 2015","article_number":"859425","year":"2015","type":"journal_article","citation":{"chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425."},"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_updated":"2023-09-26T13:29:08Z","doi":"10.1155/2015/859425","language":[{"iso":"eng"}]},{"_id":"303","type":"conference","year":"2015","citation":{"mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"ddc":["040"],"user_id":"15278","file_date_updated":"2019-08-01T09:10:44Z","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","author":[{"first_name":"Marvin","full_name":"Damschen, Marvin","last_name":"Damschen"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file":[{"date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","access_level":"open_access","file_size":1176620,"file_id":"1442","creator":"florida","content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file"}],"date_created":"2017-10-17T12:41:51Z","has_accepted_license":"1","status":"public","date_updated":"2023-09-26T13:29:59Z","oa":"1","language":[{"iso":"eng"}],"external_id":{"arxiv":["1412.3906"]},"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}]},{"year":"2015","type":"conference","citation":{"apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824."},"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:01Z","_id":"1773","doi":"10.1145/2675743.2771824","author":[{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"last_name":"T. Anderson","full_name":"T. Anderson, J.","first_name":"J."},{"full_name":"Borga, A.","first_name":"A.","last_name":"Borga"},{"last_name":"Boterenbrood","first_name":"H.","full_name":"Boterenbrood, H."},{"first_name":"H.","full_name":"Chen, H.","last_name":"Chen"},{"last_name":"Chen","first_name":"K.","full_name":"Chen, K."},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"last_name":"Francis","first_name":"D.","full_name":"Francis, D."},{"last_name":"Gorini","first_name":"B.","full_name":"Gorini, B."},{"full_name":"Lanni, F.","first_name":"F.","last_name":"Lanni"},{"full_name":"Lehmann-Miotto, Giovanna","first_name":"Giovanna","last_name":"Lehmann-Miotto"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"full_name":"Narevicius, J.","first_name":"J.","last_name":"Narevicius"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"A.","full_name":"Roich, A.","last_name":"Roich"},{"full_name":"Ryu, S.","first_name":"S.","last_name":"Ryu"},{"last_name":"P. Schreuder","first_name":"F.","full_name":"P. Schreuder, F."},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"first_name":"J.","full_name":"Vermeulen, J.","last_name":"Vermeulen"},{"last_name":"Zhang","full_name":"Zhang, J.","first_name":"J."}],"publisher":"ACM","quality_controlled":"1","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-03-23T14:09:33Z","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","user_id":"15278"},{"type":"journal_article","year":"2015","citation":{"ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z"},"page":"396-399","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:30:22Z","_id":"1768","doi":"10.1007/s00287-015-0911-z","issue":"5","quality_controlled":"1","publisher":"Springer","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Peter J.","full_name":"Schreier, Peter J.","last_name":"Schreier"}],"keyword":["approximate computing","survey"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"publication":"Informatik Spektrum","status":"public","date_created":"2018-03-23T13:58:34Z","title":"Aktuelles Schlagwort: Approximate Computing","user_id":"15278"},{"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:38Z","file":[{"date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":380552,"file_id":"1500","creator":"florida","access_level":"closed","file_name":"238-plessl15_date.pdf","date_created":"2018-03-21T10:29:49Z"}],"author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"EDA Consortium / IEEE","quality_controlled":"1","file_date_updated":"2018-03-21T10:29:49Z","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","user_id":"15278","ddc":["040"],"abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"type":"conference","year":"2015","citation":{"short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }"},"page":"1078-1083","_id":"238","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","language":[{"iso":"eng"}],"doi":"10.7873/DATE.2015.1124","date_updated":"2023-09-26T13:31:44Z"},{"_id":"347","type":"conference","citation":{"bibtex":"@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}, DOI={10.1007/978-3-319-05960-0_30}, booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner, Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture Notes in Computer Science} }","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels, 283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.","ama":"Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30","apa":"Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio, J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer. https://doi.org/10.1007/978-3-319-05960-0_30","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.","short":"S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290."},"year":"2014","page":"283-290","user_id":"398","ddc":["040"],"abstract":[{"lang":"eng","text":"Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:59Z","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:26:16Z","file_id":"1417","creator":"florida","file_size":1168877,"access_level":"closed","date_created":"2018-03-20T07:26:16Z","file_name":"347-meisner13_xx_SFB1__1_.pdf"}],"author":[{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer","publication":"Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)","file_date_updated":"2018-03-20T07:26:16Z","doi":"10.1007/978-3-319-05960-0_30","date_updated":"2022-01-06T06:59:18Z","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","title":"Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"editor":[{"first_name":"Diana","full_name":"Goehringer, Diana","last_name":"Goehringer"},{"last_name":"Santambrogio","first_name":"MarcoDomenico","full_name":"Santambrogio, MarcoDomenico"},{"first_name":"JoãoM.P.","full_name":"Cardoso, JoãoM.P.","last_name":"Cardoso"},{"first_name":"Koen","full_name":"Bertels, Koen","last_name":"Bertels"}],"department":[{"_id":"78"}]},{"doi":"10.1007/978-3-319-09165-5_2","issue":"8427","date_updated":"2022-01-06T06:53:20Z","_id":"1782","page":"14-25","year":"2014","citation":{"chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25."},"type":"conference","series_title":"Lecture Notes in Computer Science","title":"On Semeai Detection in Monte-Carlo Go","user_id":"24135","place":"Switzerland","date_created":"2018-03-26T13:50:37Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Conf. on Computers and Games (CG)","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"last_name":"Schaefers","full_name":"Schaefers, Lars","first_name":"Lars"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:09Z","file":[{"success":1,"relation":"main_file","date_updated":"2018-03-20T06:57:44Z","content_type":"application/pdf","file_id":"1380","creator":"florida","file_size":404328,"access_level":"closed","file_name":"399-wiersema14_fpt_IEEE_approved.pdf","date_created":"2018-03-20T06:57:44Z"}],"author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie","first_name":"Stephanie"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"file_date_updated":"2018-03-20T06:57:44Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","user_id":"477","ddc":["040"],"abstract":[{"text":"Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.","lang":"eng"}],"year":"2014","type":"conference","citation":{"ieee":"T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.","short":"T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.","bibtex":"@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}, year={2014}, pages={167–174} }","mla":"Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.","ama":"Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771","apa":"Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174). https://doi.org/10.1109/FPT.2014.7082771","chicago":"Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771."},"page":"167-174","_id":"399","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"department":[{"_id":"78"}],"title":"Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2014.7082771","date_updated":"2022-01-06T07:00:05Z"},{"title":"Integrating Software and Hardware Verification","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"}],"editor":[{"last_name":"Albert","first_name":"Elvira","full_name":"Albert, Elvira"},{"full_name":"Sekerinski, Emil","first_name":"Emil","last_name":"Sekerinski"}],"department":[{"_id":"77"},{"_id":"78"}],"doi":"10.1007/978-3-319-10181-1_19","date_updated":"2022-01-06T07:00:14Z","language":[{"iso":"eng"}],"series_title":"LNCS","user_id":"477","ddc":["040"],"abstract":[{"lang":"eng","text":"Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques."}],"date_created":"2017-10-17T12:42:11Z","status":"public","has_accepted_license":"1","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-16T11:35:28Z","creator":"florida","file_id":"1364","file_size":561325,"access_level":"closed","date_created":"2018-03-16T11:35:28Z","file_name":"408-jakobs14_ifm.pdf"}],"file_date_updated":"2018-03-16T11:35:28Z","publication":"Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)","author":[{"last_name":"Jakobs","full_name":"Jakobs, Marie-Christine","first_name":"Marie-Christine"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Wehrheim","id":"573","first_name":"Heike","full_name":"Wehrheim, Heike"}],"_id":"408","page":"307-322","type":"conference","citation":{"bibtex":"@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19}, booktitle={Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors}, year={2014}, pages={307–322}, collection={LNCS} }","mla":"Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.” Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.","apa":"Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322). https://doi.org/10.1007/978-3-319-10181-1_19","ama":"Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19","chicago":"Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim. “Integrating Software and Hardware Verification.” In Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19.","ieee":"M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in Proceedings of the 11th International Conference on Integrated Formal Methods (iFM), 2014, pp. 307–322.","short":"M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322."},"year":"2014"},{"_id":"433","year":"2014","type":"conference","citation":{"short":"T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","ama":"Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514","apa":"Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–6, 2014. https://doi.org/10.1109/ReConFig.2014.7032514.","bibtex":"@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={10.1109/ReConFig.2014.7032514}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2014}, pages={1–6} }","mla":"Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514."},"page":"1-6 ","abstract":[{"text":"Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.","lang":"eng"}],"user_id":"477","ddc":["040"],"file":[{"file_name":"433-wiersema14_reconfig_IEEE_approved.pdf","date_created":"2018-03-16T11:30:58Z","access_level":"closed","file_size":369333,"file_id":"1355","creator":"florida","date_updated":"2018-03-16T11:30:58Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Bockhorn","first_name":"Arne","full_name":"Bockhorn, Arne"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"file_date_updated":"2018-03-16T11:30:58Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:16Z","date_updated":"2022-01-06T07:00:56Z","doi":"10.1109/ReConFig.2014.7032514","language":[{"iso":"eng"}],"title":"Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}]},{"title":"A Novel Technique and its Application to Computer Go","user_id":"3118","publication":"IEEE Transactions on Computational Intelligence and AI in Games","department":[{"_id":"78"}],"author":[{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"volume":6,"date_created":"2019-07-10T09:22:43Z","status":"public","date_updated":"2022-01-06T06:50:47Z","_id":"10602","intvolume":" 6","doi":"10.1109/TCIAIG.2014.2346997","issue":"3","page":"361-374","citation":{"mla":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.","bibtex":"@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={10.1109/TCIAIG.2014.2346997}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }","ama":"Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374. doi:10.1109/TCIAIG.2014.2346997","apa":"Schaefers, L., & Platzner, M. (2014). A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games, 6(3), 361–374. https://doi.org/10.1109/TCIAIG.2014.2346997","chicago":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” IEEE Transactions on Computational Intelligence and AI in Games 6, no. 3 (2014): 361–74. https://doi.org/10.1109/TCIAIG.2014.2346997.","ieee":"L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, pp. 361–374, 2014.","short":"L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374."},"type":"journal_article","year":"2014","language":[{"iso":"eng"}]},{"_id":"10603","intvolume":" 63","date_updated":"2022-01-06T06:50:47Z","issue":"12","doi":"10.1109/TC.2013.174","language":[{"iso":"eng"}],"page":"2919 - 2932","year":"2014","type":"journal_article","citation":{"bibtex":"@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={10.1109/TC.2013.174}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }","mla":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.","chicago":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” IEEE Transactions on Computers 63, no. 12 (2014): 2919–32. https://doi.org/10.1109/TC.2013.174.","ama":"Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174","apa":"Giefers, H., & Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers, 63(12), 2919–2932. https://doi.org/10.1109/TC.2013.174","ieee":"H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.","short":"H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932."},"user_id":"398","title":"An FPGA-based Reconfigurable Mesh Many-Core","publication":"IEEE Transactions on Computers","department":[{"_id":"78"}],"author":[{"last_name":"Giefers","full_name":"Giefers, Heiner","first_name":"Heiner"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T09:22:44Z","status":"public","volume":63},{"language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy Configurations: An Automated Design Space Exploration}, DOI={10.1109/IPDPSW.2014.37}, booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }","mla":"Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” Reconfigurable Architectures Workshop (RAW), 2014, doi:10.1109/IPDPSW.2014.37.","chicago":"Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” In Reconfigurable Architectures Workshop (RAW). RAW, 2014. https://doi.org/10.1109/IPDPSW.2014.37.","ama":"Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW). RAW. ; 2014. doi:10.1109/IPDPSW.2014.37","apa":"Anwer, J., Platzner, M., & Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In Reconfigurable Architectures Workshop (RAW). https://doi.org/10.1109/IPDPSW.2014.37","ieee":"J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in Reconfigurable Architectures Workshop (RAW), 2014.","short":"J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014."},"year":"2014","type":"conference","series_title":"RAW","doi":"10.1109/IPDPSW.2014.37","_id":"10621","date_updated":"2022-01-06T06:50:48Z","date_created":"2019-07-10T09:32:58Z","status":"public","publication":"Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"}],"user_id":"3118","title":"FPGA Redundancy Configurations: An Automated Design Space Exploration"},{"status":"public","date_created":"2019-07-10T09:40:25Z","publisher":"Paderborn University","author":[{"last_name":"Bockhorn","full_name":"Bockhorn, Arne","first_name":"Arne"}],"department":[{"_id":"78"}],"user_id":"3118","title":"Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"}],"type":"bachelorsthesis","year":"2014","citation":{"ieee":"A. Bockhorn, Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board. Paderborn University, 2014.","short":"A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board, Paderborn University, 2014.","mla":"Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University, 2014.","bibtex":"@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn, Arne}, year={2014} }","chicago":"Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University, 2014.","apa":"Bockhorn, A. (2014). Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board. Paderborn University.","ama":"Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University; 2014."},"date_updated":"2022-01-06T06:50:48Z","_id":"10627"},{"title":"A computer vision-based approach to high density EMG pattern recognition using structural similarity","user_id":"3118","date_created":"2019-07-10T11:02:58Z","status":"public","department":[{"_id":"78"}],"publication":"Proc. MyoElectric Controls Symposium (MEC)","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10632","citation":{"short":"A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC), 2014.","ieee":"A. Boschmann and M. Platzner, “A computer vision-based approach to high density EMG pattern recognition using structural similarity,” in Proc. MyoElectric Controls Symposium (MEC), 2014.","chicago":"Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” In Proc. MyoElectric Controls Symposium (MEC), 2014.","ama":"Boschmann A, Platzner M. A computer vision-based approach to high density EMG pattern recognition using structural similarity. In: Proc. MyoElectric Controls Symposium (MEC). ; 2014.","apa":"Boschmann, A., & Platzner, M. (2014). A computer vision-based approach to high density EMG pattern recognition using structural similarity. In Proc. MyoElectric Controls Symposium (MEC).","bibtex":"@inproceedings{Boschmann_Platzner_2014, title={A computer vision-based approach to high density EMG pattern recognition using structural similarity}, booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2014} }","mla":"Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” Proc. MyoElectric Controls Symposium (MEC), 2014."},"type":"conference","year":"2014","language":[{"iso":"eng"}]},{"date_created":"2019-07-10T11:02:59Z","status":"public","publication":"Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)","department":[{"_id":"78"}],"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity","user_id":"3118","type":"conference","year":"2014","citation":{"mla":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.","bibtex":"@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2014} }","apa":"Boschmann, A., & Platzner, M. (2014). Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC).","ama":"Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2014.","chicago":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.","ieee":"A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.","short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014."},"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10633"},{"date_created":"2019-07-10T11:03:41Z","status":"public","department":[{"_id":"78"}],"author":[{"full_name":"Brand, Marcel","first_name":"Marcel","last_name":"Brand"}],"publisher":"Paderborn University","title":"A Generalized Loop Accelerator Implemented as a Coarse-Grained Array","user_id":"3118","type":"mastersthesis","year":"2014","citation":{"bibtex":"@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel}, year={2014} }","mla":"Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University, 2014.","chicago":"Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University, 2014.","ama":"Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University; 2014.","apa":"Brand, M. (2014). A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University.","ieee":"M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University, 2014.","short":"M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained Array, Paderborn University, 2014."},"language":[{"iso":"eng"}],"_id":"10640","date_updated":"2022-01-06T06:50:49Z"},{"language":[{"iso":"eng"}],"citation":{"bibtex":"@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014} }","mla":"Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University, 2014.","chicago":"Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University, 2014.","ama":"Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University; 2014.","apa":"Damschen, M. (2014). Easy-to-use-on-the-fly binary program acceleration on many-cores. Paderborn University.","ieee":"M. Damschen, Easy-to-use-on-the-fly binary program acceleration on many-cores. Paderborn University, 2014.","short":"M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores, Paderborn University, 2014."},"year":"2014","type":"mastersthesis","date_updated":"2022-01-06T06:50:49Z","_id":"10645","author":[{"first_name":"Marvin","full_name":"Damschen, Marvin","last_name":"Damschen"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:08:47Z","user_id":"3118","title":"Easy-to-use-on-the-fly binary program acceleration on many-cores"},{"author":[{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"publication":"IEEE Congress on Evolutionary Computation (CEC)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:13:14Z","user_id":"3118","title":"Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System","citation":{"short":"K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC), 2014.","ieee":"K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System,” in IEEE Congress on Evolutionary Computation (CEC), 2014.","ama":"Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC). ; 2014.","apa":"Glette, K., & Kaufmann, P. (2014). Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In IEEE Congress on Evolutionary Computation (CEC).","chicago":"Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” In IEEE Congress on Evolutionary Computation (CEC), 2014.","bibtex":"@inproceedings{Glette_Kaufmann_2014, title={Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System}, booktitle={IEEE Congress on Evolutionary Computation (CEC)}, author={Glette, Kyrre and Kaufmann, Paul}, year={2014} }","mla":"Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” IEEE Congress on Evolutionary Computation (CEC), 2014."},"type":"conference","year":"2014","_id":"10654","date_updated":"2022-01-06T06:50:49Z"}]