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Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. 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Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8."},"page":"145-165","_id":"156","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:22Z","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer International Publishing","quality_controlled":"1","file_date_updated":"2018-11-14T13:20:32Z","publication":"Self-aware Computing Systems","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-14T13:20:32Z","file_id":"5613","creator":"aloesch","file_size":833054,"access_level":"closed","file_name":"chapter8.pdf","date_created":"2018-11-14T13:20:32Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}]}]