[{"date_created":"2019-07-10T09:40:26Z","status":"public","alternative_title":["Effects of Pattern Matching Algorithms on Long-term Electromyography Signals"],"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"}],"user_id":"3118","title":"Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"citation":{"apa":"Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University.","ama":"Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University; 2008.","chicago":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","mla":"Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.","bibtex":"@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }","short":"A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen, Paderborn University, 2008.","ieee":"A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008."},"type":"bachelorsthesis","year":"2008","date_updated":"2022-01-06T06:50:48Z","_id":"10628"},{"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}],"citation":{"ieee":"D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.","short":"D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008.","bibtex":"@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }","mla":"Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.","apa":"Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn University.","ama":"Breitlauch D. Selbstoptimierender Cache-Kontroller. Paderborn University; 2008.","chicago":"Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008."},"year":"2008","type":"bachelorsthesis","date_updated":"2022-01-06T06:50:49Z","_id":"10641","department":[{"_id":"78"}],"author":[{"last_name":"Breitlauch","first_name":"Daniel","full_name":"Breitlauch, Daniel"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:03:42Z","status":"public","alternative_title":["Self-optimizing Cache Controller"],"user_id":"3118","title":"Selbstoptimierender Cache-Kontroller"},{"title":"Verteilte Simulation von mobilen Robotern mit EyeSim","user_id":"3118","publisher":"Paderborn University","author":[{"last_name":"Ceylan","full_name":"Ceylan, Toni","first_name":"Toni"},{"last_name":"Yalcin","full_name":"Yalcin, Coni","first_name":"Coni"}],"department":[{"_id":"78"}],"alternative_title":["Distributed Simulation of mobile Robots using EyeSim"],"status":"public","date_created":"2019-07-10T11:03:45Z","date_updated":"2022-01-06T06:50:49Z","_id":"10644","type":"bachelorsthesis","year":"2008","citation":{"chicago":"Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008.","ama":"Ceylan T, Yalcin C. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University; 2008.","apa":"Ceylan, T., & Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University.","mla":"Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008.","bibtex":"@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }","short":"T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008.","ieee":"T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University, 2008."},"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}]},{"date_updated":"2022-01-06T06:50:49Z","_id":"10653","language":[{"iso":"eng"}],"page":"32-39","citation":{"short":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.","ieee":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS), 2008, pp. 32–39.","apa":"Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., & Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp. 32–39). IEEE.","ama":"Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: IEEE Adaptive Hardware and Systems (AHS). IEEE; 2008:32-39.","chicago":"Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” In IEEE Adaptive Hardware and Systems (AHS), 32–39. IEEE, 2008.","mla":"Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.","bibtex":"@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }"},"type":"conference","year":"2008","user_id":"3118","title":"Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control","publication":"IEEE Adaptive Hardware and Systems (AHS)","department":[{"_id":"78"}],"author":[{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"last_name":"Gruber","full_name":"Gruber, Thiemo","first_name":"Thiemo"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"first_name":"Jim","full_name":"Torresen, Jim","last_name":"Torresen"},{"first_name":"Bernhard","full_name":"Sick, Bernhard","last_name":"Sick"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","date_created":"2019-07-10T11:13:13Z","status":"public"},{"status":"public","date_created":"2019-07-10T11:13:31Z","volume":5216,"author":[{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","department":[{"_id":"78"}],"publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","user_id":"3118","title":"A Comparison of Evolvable Hardware Architectures for Classification Tasks","language":[{"iso":"eng"}],"citation":{"apa":"Glette, K., Torresen, J., Kaufmann, P., & Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer.","ama":"Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 5216. LNCS. Springer; 2008:22-33.","chicago":"Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 5216:22–33. LNCS. Springer, 2008.","mla":"Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 5216, Springer, 2008, pp. 22–33.","bibtex":"@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={22–33}, collection={LNCS} }","short":"K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33.","ieee":"K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2008, vol. 5216, pp. 22–33."},"year":"2008","type":"conference","page":"22-33","series_title":"LNCS","_id":"10656","date_updated":"2022-01-06T06:50:49Z","intvolume":" 5216"},{"_id":"10669","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"short":"M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008.","ieee":"M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","ama":"Happe M. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University; 2008.","apa":"Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University.","chicago":"Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","mla":"Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.","bibtex":"@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }"},"year":"2008","type":"mastersthesis","user_id":"3118","title":"Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern","publisher":"Paderborn University","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:15:14Z"},{"status":"public","date_created":"2019-07-10T11:29:14Z","author":[{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"department":[{"_id":"78"}],"user_id":"398","title":"Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)","language":[{"iso":"eng"}],"type":"preprint","citation":{"chicago":"Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008.","ama":"Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","apa":"Torresen, J., Glette, K., Platzner, M., & Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).","mla":"Torresen, Jim, et al. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","bibtex":"@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }","short":"J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).","ieee":"J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008."},"year":"2008","_id":"10690","date_updated":"2022-01-06T06:50:49Z"},{"title":"Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming","user_id":"3118","status":"public","date_created":"2019-07-10T11:29:57Z","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"ACM Press","publication":"Genetic and Evolutionary Computation (GECCO)","department":[{"_id":"78"}],"_id":"10691","date_updated":"2022-01-06T06:50:49Z","type":"conference","year":"2008","citation":{"ieee":"P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), 2008, pp. 1219–1226.","short":"P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.","bibtex":"@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }","mla":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–26.","apa":"Kaufmann, P., & Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press.","ama":"Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO). ACM Press; 2008:1219-1226.","chicago":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), 1219–26. ACM Press, 2008."},"page":"1219 - 1226","language":[{"iso":"eng"}]},{"author":[{"first_name":"Tobias","full_name":"Knieper, Tobias","last_name":"Knieper"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:30:22Z","alternative_title":["Multi-objective Optimizer IBEA for Digital Logic Design"],"user_id":"3118","title":"Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","year":"2008","citation":{"ieee":"T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008.","short":"T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.","bibtex":"@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }","mla":"Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008.","ama":"Knieper T. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University; 2008.","apa":"Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University.","chicago":"Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008."},"_id":"10696","date_updated":"2022-01-06T06:50:49Z"},{"series_title":"IFIP International Federation for Information Processing","page":"2313-222","type":"conference","citation":{"ieee":"T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC), 2008, vol. 268, pp. 2313–222.","short":"T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.","bibtex":"@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={2313–222}, collection={IFIP International Federation for Information Processing} }","mla":"Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” Biologically Inspired Collaborative Computing (BICC), vol. 268, Springer, 2008, pp. 2313–222.","chicago":"Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In Biologically Inspired Collaborative Computing (BICC), 268:2313–222. IFIP International Federation for Information Processing. Springer, 2008.","apa":"Knieper, T., Defo, B., Kaufmann, P., & Platzner, M. (2008). On Robust Evolution of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC) (Vol. 268, pp. 2313–222). Springer.","ama":"Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: Biologically Inspired Collaborative Computing (BICC). Vol 268. IFIP International Federation for Information Processing. Springer; 2008:2313-222."},"year":"2008","language":[{"iso":"eng"}],"_id":"10698","date_updated":"2022-01-06T06:50:49Z","intvolume":" 268","department":[{"_id":"78"}],"publication":"Biologically Inspired Collaborative Computing (BICC)","author":[{"last_name":"Knieper","full_name":"Knieper, Tobias","first_name":"Tobias"},{"first_name":"Bertrand","full_name":"Defo, Bertrand","last_name":"Defo"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer","volume":268,"date_created":"2019-07-10T11:38:02Z","status":"public","title":"On Robust Evolution of Digital Hardware","user_id":"3118"},{"author":[{"full_name":"Niklas, Jörg","first_name":"Jörg","last_name":"Niklas"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:48:29Z","title":"Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme","user_id":"3118","year":"2008","type":"bachelorsthesis","citation":{"short":"J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008.","ieee":"J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008.","chicago":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","apa":"Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University.","ama":"Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University; 2008.","mla":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","bibtex":"@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }"},"language":[{"iso":"eng"}],"_id":"10718","date_updated":"2022-01-06T06:50:50Z"},{"_id":"10721","date_updated":"2022-01-06T06:50:50Z","citation":{"mla":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","bibtex":"@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }","chicago":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","ama":"Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University; 2008.","apa":"Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University.","ieee":"M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","short":"M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008."},"year":"2008","type":"bachelorsthesis","language":[{"iso":"eng"}],"title":"Raytracing on a Custom Instruction Set CPU","user_id":"3118","publisher":"Paderborn University","author":[{"full_name":"Östermann, Marco","first_name":"Marco","last_name":"Östermann"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:52:51Z"},{"language":[{"iso":"eng"}],"citation":{"apa":"Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University.","ama":"Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University; 2008.","chicago":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008.","bibtex":"@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }","mla":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008.","short":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008.","ieee":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008."},"type":"bachelorsthesis","year":"2008","_id":"10751","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"author":[{"first_name":"Nico","full_name":"Westerheide, Nico","last_name":"Westerheide"}],"publisher":"Paderborn University","date_created":"2019-07-10T12:03:01Z","status":"public","user_id":"3118","title":"Design and Evaluation of MicroBlaze Multi-core Architectures"},{"date_updated":"2022-01-06T06:50:50Z","_id":"10778","doi":"10.1109/ICM.2008.5393497","language":[{"iso":"eng"}],"year":"2008","type":"conference","citation":{"ieee":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447.","short":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={10.1109/ICM.2008.5393497}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }","ama":"Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497","apa":"Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497","chicago":"Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In 2008 International Conference on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497."},"page":"444-447","extern":"1","user_id":"3118","title":"A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic","publisher":"IEEE","author":[{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"first_name":"Hamed","full_name":"Tabkhi, Hamed","last_name":"Tabkhi"},{"first_name":"Seyed Ghassem","full_name":"Miremadi, Seyed Ghassem","last_name":"Miremadi"},{"last_name":"Ejlali","first_name":"Alireza","full_name":"Ejlali, Alireza"}],"department":[{"_id":"78"}],"publication":"2008 International Conference on Microelectronics","status":"public","date_created":"2019-07-10T12:11:35Z"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"mla":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.","bibtex":"@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }","chicago":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE, 2008.","ama":"Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE; 2008.","apa":"Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE.","ieee":"H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008.","short":"H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008."},"year":"2008","date_updated":"2022-01-06T06:51:40Z","_id":"13629","author":[{"last_name":"Giefers","full_name":"Giefers, Heiner","first_name":"Heiner"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","publication":"Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T22:05:22Z","user_id":"398","title":"Realizing Reconfigurable Mesh Algorithms on Softcore Arrays"},{"title":"Communication and Synchronization in Multithreaded Reconfigurable Computing Systems","user_id":"398","status":"public","date_created":"2019-10-04T22:07:14Z","author":[{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","publication":"Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"_id":"13630","date_updated":"2022-01-06T06:51:40Z","type":"conference","citation":{"ama":"Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008.","apa":"Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","chicago":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2008.","mla":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","short":"E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","ieee":"E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008."},"year":"2008","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"short":"E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.","ieee":"E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), 2008.","ama":"Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901","apa":"Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901","chicago":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={10.1109/fpl.2008.4629901}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","mla":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901."},"type":"conference","year":"2008","doi":"10.1109/fpl.2008.4629901","_id":"13631","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T22:07:43Z","status":"public","publication_status":"published","publication_identifier":{"isbn":["9781424419609"]},"publication":"Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","user_id":"398","title":"A portable abstraction layer for hardware threads"},{"date_created":"2018-04-17T11:33:32Z","status":"public","publication_identifier":{"isbn":["1-60132-064-7"]},"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"CSREA Press","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"15278","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning","language":[{"iso":"eng"}],"page":"245-251","year":"2008","citation":{"ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251.","ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251."},"type":"conference","_id":"2364","date_updated":"2023-09-26T13:54:24Z"},{"title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","user_id":"15278","date_created":"2018-04-17T12:05:28Z","status":"public","publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)","keyword":["IMORC","IP core","interconnect"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_updated":"2023-09-26T13:55:51Z","_id":"2372","year":"2008","type":"conference","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008."},"language":[{"iso":"eng"}]},{"title":"MOVES: A Modular Framework for Hardware Evolution","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["076952866X","9780769528663"]},"date_updated":"2022-01-06T07:03:08Z","doi":"10.1109/ahs.2007.73","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits."}],"user_id":"3118","publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"publisher":"IEEE","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-01-08T09:52:43Z","status":"public","conference":{"end_date":"2007-08-08","location":"Edinburgh, UK","start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)"},"_id":"6508","page":"447-454","citation":{"mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={10.1109/ahs.2007.73}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","apa":"Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK, 2007, pp. 447–454.","short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454."},"type":"conference","year":"2007"}]