[{"user_id":"49051","abstract":[{"text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.","lang":"eng"}],"article_type":"original","date_created":"2020-07-06T11:21:30Z","status":"public","volume":28,"publication":"IEEE Transactions On Very Large Scale Integration Systems","keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"issue":"9","intvolume":" 28","_id":"17358","page":"2084 - 2088","citation":{"short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020.","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems 28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }","mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061."},"type":"journal_article","year":"2020","funded_apc":"1","title":"Proof-carrying Approximate Circuits","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901","_id":"1"}],"publication_identifier":{"issn":["1063-8210"],"eissn":["1557-9999"]},"publication_status":"published","department":[{"_id":"78"}],"doi":"10.1109/TVLSI.2020.3008061","date_updated":"2022-01-06T06:53:09Z","language":[{"iso":"eng"}]},{"author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IOS Press","department":[{"_id":"78"}],"publication":"International Journal of Hybrid intelligent Systems","status":"public","date_created":"2020-07-10T18:55:30Z","title":"Evolution of Application-Specific Cache Mappings","user_id":"398","citation":{"short":"N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent Systems (2020).","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2020). Evolution of Application-Specific Cache Mappings. International Journal of Hybrid Intelligent Systems.","ama":"Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings. International Journal of Hybrid intelligent Systems. 2020.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific Cache Mappings.” International Journal of Hybrid Intelligent Systems, 2020.","mla":"Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” International Journal of Hybrid Intelligent Systems, IOS Press, 2020.","bibtex":"@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific Cache Mappings}, journal={International Journal of Hybrid intelligent Systems}, publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2020} }"},"year":"2020","type":"journal_article","language":[{"iso":"eng"}],"_id":"17369","date_updated":"2022-01-06T06:53:09Z"},{"department":[{"_id":"78"}],"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"publication_status":"accepted","title":"Search Space Characterization for AxC Synthesis","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:54:35Z","file":[{"file_name":"witschen20_axc.pdf","date_created":"2020-12-15T15:11:06Z","access_level":"closed","file_id":"20749","creator":"witschen","file_size":250870,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2020-12-15T15:11:06Z"}],"publication":"Fifth Workshop on Approximate Computing (AxC 2020)","file_date_updated":"2020-12-15T15:11:06Z","author":[{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","id":"49051","last_name":"Witschen"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2020-12-15T15:13:49Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies.\r\nIn the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. \r\nIn this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification.\r\nIn our experimental results, we present the runtimes of our approach."}],"user_id":"3118","ddc":["000"],"page":"2","year":"2020","type":"preprint","citation":{"bibtex":"@article{Witschen_Wiersema_Platzner, title={Search Space Characterization for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }","mla":"Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020).","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020), n.d.","ama":"Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).","apa":"Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .","short":"L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.)."},"_id":"20748"},{"_id":"20750","date_updated":"2022-01-06T06:54:35Z","conference":{"start_date":"2020-12-09","name":"International Conference on Field Programmable Technology (ICFPT)","end_date":"2020-12-11"},"citation":{"short":"C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","ieee":"C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for ROS2 Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","chicago":"Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” In Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","ama":"Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT). ; 2020.","apa":"Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT).","mla":"Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","bibtex":"@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian and Platzner, Marco and Rinner, Bernhard}, year={2020} }"},"type":"conference","year":"2020","language":[{"iso":"eng"}],"title":"ReconROS: Flexible Hardware Acceleration for ROS2 Applications","user_id":"398","status":"public","date_created":"2020-12-16T05:20:01Z","author":[{"full_name":"Lienen, Christian","first_name":"Christian","id":"60323","last_name":"Lienen"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"}],"publication":"Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"78"}]},{"supervisor":[{"full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"citation":{"mla":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","bibtex":"@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ FPGA Overlays}, author={Thiele, Simon}, year={2020} }","ama":"Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.; 2020.","apa":"Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA Overlays.","chicago":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","ieee":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","short":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020."},"year":"2020","type":"bachelorsthesis","date_updated":"2022-01-06T06:54:40Z","_id":"20820","author":[{"first_name":"Simon","full_name":"Thiele, Simon","last_name":"Thiele"}],"department":[{"_id":"78"}],"status":"public","date_created":"2020-12-21T13:59:55Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"82","name":"SFB 901 - Project Area T"},{"_id":"83","name":"SFB 901 -Subproject T1"}],"user_id":"74287","title":"Implementing Machine Learning Functions as PYNQ FPGA Overlays"},{"type":"mastersthesis","year":"2020","citation":{"bibtex":"@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }","mla":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows. 2020.","apa":"Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level Synthesis Tool Flows.","ama":"Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows.; 2020.","chicago":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.","ieee":"V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020.","short":"V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020."},"supervisor":[{"full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:54:40Z","_id":"20821","date_created":"2020-12-21T14:02:42Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"82","name":"SFB 901 - Project Area T"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"status":"public","department":[{"_id":"78"}],"author":[{"first_name":"Vivek","full_name":"Jaganath, Vivek","last_name":"Jaganath"}],"title":"Extension and Evaluation of Python-based High-Level Synthesis Tool Flows","user_id":"74287"},{"page":"1756-1764","citation":{"mla":"Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.” GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.","bibtex":"@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }","chicago":"Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “An Adaption Mechanism for the Error Threshold of XCSF.” In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1756–64. New York, NY, United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3398106.","apa":"Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106","ama":"Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764. doi:10.1145/3377929.3398106","ieee":"T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi: 10.1145/3377929.3398106.","short":"T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764."},"type":"conference","year":"2020","conference":{"end_date":"2020-07-12","location":"Cancún, Mexico","name":"International Workshop on Learning Classifier Systems (IWLCS 2020)","start_date":"2020-07-08"},"_id":"17063","date_created":"2020-05-27T14:14:58Z","status":"public","publication":"GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion","author":[{"first_name":"Tim","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","last_name":"Hansmeier","id":"49992"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Association for Computing Machinery (ACM)","user_id":"477","language":[{"iso":"eng"}],"doi":"10.1145/3377929.3398106","date_updated":"2022-01-06T06:53:03Z","publication_identifier":{"isbn":["978-1-4503-7127-8"]},"publication_status":"published","project":[{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"department":[{"_id":"78"}],"title":"An Adaption Mechanism for the Error Threshold of XCSF","place":"New York, NY, United States"},{"abstract":[{"lang":"eng","text":"Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application."}],"user_id":"398","title":"Dynamic Reliability Management for FPGA-Based Systems","department":[{"_id":"78"}],"publication":"International Journal of Reconfigurable Computing","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2020-06-15T11:25:07Z","status":"public","publication_status":"published","publication_identifier":{"issn":["1687-7195","1687-7209"]},"date_updated":"2022-01-06T06:53:04Z","_id":"17092","doi":"10.1155/2020/2808710","language":[{"iso":"eng"}],"page":"1-19","type":"journal_article","citation":{"short":"J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable Computing (2020) 1–19.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, pp. 1–19, 2020.","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management for FPGA-Based Systems.” International Journal of Reconfigurable Computing, 2020, 1–19. https://doi.org/10.1155/2020/2808710.","ama":"Anwer J, Meisner S, Platzner M. Dynamic Reliability Management for FPGA-Based Systems. International Journal of Reconfigurable Computing. 2020:1-19. doi:10.1155/2020/2808710","apa":"Anwer, J., Meisner, S., & Platzner, M. (2020). Dynamic Reliability Management for FPGA-Based Systems. International Journal of Reconfigurable Computing, 1–19. https://doi.org/10.1155/2020/2808710","bibtex":"@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management for FPGA-Based Systems}, DOI={10.1155/2020/2808710}, journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.” International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710."},"year":"2020"},{"status":"public","date_created":"2020-02-06T15:05:45Z","volume":"Accepted for Publication","author":[{"first_name":"K.","full_name":"Bellman, K.","last_name":"Bellman"},{"full_name":"Dutt, N.","first_name":"N.","last_name":"Dutt"},{"first_name":"L.","full_name":"Esterle, L.","last_name":"Esterle"},{"last_name":"Herkersdorf","full_name":"Herkersdorf, A.","first_name":"A."},{"last_name":"Jantsch","full_name":"Jantsch, A.","first_name":"A."},{"last_name":"Landauer","full_name":"Landauer, C.","first_name":"C."},{"first_name":"P.","full_name":"R. Lewis, P.","last_name":"R. Lewis"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"TaheriNejad","full_name":"TaheriNejad, N.","first_name":"N."},{"first_name":"K.","full_name":"Tammemäe, K.","last_name":"Tammemäe"}],"department":[{"_id":"78"}],"publication":"ACM Transactions on Cyber-Physical Systems","user_id":"398","title":"Self-aware Cyber-Physical Systems","language":[{"iso":"eng"}],"type":"journal_article","year":"2020","citation":{"short":"K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer, P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical Systems Accepted for Publication (2020) 1–24.","ieee":"K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.","chicago":"Bellman, K., N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer, P. R. Lewis, Marco Platzner, N. TaheriNejad, and K. Tammemäe. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems Accepted for Publication (2020): 1–24.","ama":"Bellman K, Dutt N, Esterle L, et al. Self-aware Cyber-Physical Systems. ACM Transactions on Cyber-Physical Systems. 2020;Accepted for Publication:1-24.","apa":"Bellman, K., Dutt, N., Esterle, L., Herkersdorf, A., Jantsch, A., Landauer, C., … Tammemäe, K. (2020). Self-aware Cyber-Physical Systems. ACM Transactions on Cyber-Physical Systems, Accepted for Publication, 1–24.","mla":"Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.","bibtex":"@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020, title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication}, journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C. and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020}, pages={1–24} }"},"page":"1-24","_id":"15836","date_updated":"2022-01-06T06:52:37Z"},{"publication_status":"published","status":"public","date_created":"2020-03-02T15:49:38Z","author":[{"orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","first_name":"Muhammad","id":"64665","last_name":"Awais"},{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"ACM","publication":"Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020","department":[{"_id":"78"}],"title":"A Hybrid Synthesis Methodology for Approximate Circuits","user_id":"64665","abstract":[{"lang":"eng","text":"Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \\textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. "}],"type":"conference","year":"2020","citation":{"bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952}, booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2020}, pages={421–426} }","mla":"Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.” Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.","apa":"Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China: ACM. https://doi.org/10.1145/3386263.3406952","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426."},"page":"421-426","language":[{"iso":"eng"}],"doi":"10.1145/3386263.3406952","_id":"16213","date_updated":"2022-01-06T06:52:45Z","conference":{"name":"ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020","location":"Beijing, China"}},{"title":"Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold","place":"New York, NY, United States","project":[{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"publication_status":"published","publication_identifier":{"isbn":["978-1-4503-7127-8"]},"department":[{"_id":"78"}],"doi":"10.1145/3377929.3389968","date_updated":"2022-01-06T06:52:49Z","language":[{"iso":"eng"}],"user_id":"477","date_created":"2020-04-02T10:07:10Z","status":"public","publication":"GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion","publisher":"Association for Computing Machinery (ACM)","author":[{"id":"49992","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","first_name":"Tim"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"conference":{"location":"Cancún, Mexico","start_date":"2020-07-08","name":"The Genetic and Evolutionary Computation Conference (GECCO 2020)","end_date":"2020-07-12"},"_id":"16363","page":"125-126","citation":{"short":"T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.","ieee":"T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.","chicago":"Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 125–26. New York, NY, United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3389968.","ama":"Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York, NY, United States: Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968","apa":"Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126). New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968","bibtex":"@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}, DOI={10.1145/3377929.3389968}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126} }","mla":"Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125–26, doi:10.1145/3377929.3389968."},"type":"conference","year":"2020"},{"doi":"10.1109/ipdpsw50202.2020.00012","_id":"20838","date_updated":"2023-01-03T22:07:12Z","type":"conference","year":"2020","citation":{"chicago":"Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.","apa":"Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012","ama":"Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012","mla":"Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.","bibtex":"@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012}, booktitle={2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }","short":"A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020.","ieee":"A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012."},"language":[{"iso":"eng"}],"title":"MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes","user_id":"398","publication_status":"published","publication_identifier":{"isbn":["9781728174457"]},"status":"public","date_created":"2020-12-23T09:07:11Z","author":[{"last_name":"Lösch","first_name":"Achim","full_name":"Lösch, Achim"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)"},{"department":[{"_id":"78"}],"author":[{"first_name":"Felix P.","full_name":"Jentzsch, Felix P.","last_name":"Jentzsch"}],"date_created":"2021-03-10T07:09:14Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"},{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"}],"status":"public","abstract":[{"text":"Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.","lang":"eng"}],"title":"Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture","user_id":"398","citation":{"ieee":"F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.","short":"F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020.","mla":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture. 2020.","bibtex":"@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020} }","chicago":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020.","apa":"Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture.","ama":"Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture.; 2020."},"type":"mastersthesis","year":"2020","supervisor":[{"full_name":"Lienen, Christian","first_name":"Christian","id":"60323","last_name":"Lienen"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"language":[{"iso":"eng"}],"_id":"21433","date_updated":"2023-07-09T17:12:52Z"},{"title":"CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation","department":[{"_id":"78"}],"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","publication_identifier":{"issn":["0026-2714"]},"date_updated":"2022-01-06T06:59:25Z","doi":"10.1016/j.microrel.2019.04.003","language":[{"iso":"eng"}],"abstract":[{"text":"Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.","lang":"eng"}],"user_id":"49051","publisher":"Elsevier","author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"last_name":"Awais","id":"64665","first_name":"Muhammad","orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["Approximate Computing","Framework","Pareto Front","Accuracy"],"publication":"Microelectronics Reliability","status":"public","date_created":"2018-07-20T14:08:49Z","volume":99,"intvolume":" 99","_id":"3585","citation":{"mla":"Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.","bibtex":"@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019): 277–90. https://doi.org/10.1016/j.microrel.2019.04.003.","ama":"Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003","apa":"Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003","ieee":"L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.","short":"L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability 99 (2019) 277–290."},"type":"journal_article","year":"2019","page":"277-290"},{"type":"preprint","citation":{"short":"L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.).","ieee":"L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .","ama":"Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).","apa":"Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).","chicago":"Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.","bibtex":"@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }","mla":"Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019)."},"year":"2019","page":"2","_id":"16853","status":"public","has_accepted_license":"1","date_created":"2020-04-25T08:02:07Z","file":[{"file_size":152806,"creator":"witschen","file_id":"16854","date_updated":"2020-04-25T08:00:35Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"AxC19_paper_3.pdf","date_created":"2020-04-25T08:00:35Z","access_level":"closed"}],"author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"last_name":"Artmann","first_name":"Matthias","full_name":"Artmann, Matthias"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Fourth Workshop on Approximate Computing (AxC 2019)","keyword":["Approximate computing","parameter selection","search space exploration","verification","circuit synthesis"],"file_date_updated":"2020-04-25T08:00:35Z","user_id":"49051","ddc":["006"],"abstract":[{"text":"State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.","lang":"eng"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:52:57Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"accepted","department":[{"_id":"78"}],"title":"Jump Search: A Fast Technique for the Synthesis of Approximate Circuits"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:45Z","doi":"10.1145/3299874.3317998","department":[{"_id":"78"}],"publication_identifier":{"isbn":["9781450362528"]},"publication_status":"published","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"place":"New York, NY, USA","title":"Jump Search: A Fast Technique for the Synthesis of Approximate Circuits","year":"2019","type":"conference","citation":{"chicago":"Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.","ama":"Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM; 2019. doi:10.1145/3299874.3317998","apa":"Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998","bibtex":"@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, DOI={10.1145/3299874.3317998}, booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }","mla":"Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.","short":"L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY, USA, 2019.","ieee":"L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner, VA, USA, 2019."},"_id":"10577","conference":{"name":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","start_date":"2019-05-09","location":"Tysons Corner, VA, USA","end_date":"2019-05-11"},"publisher":"ACM","author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"id":"61186","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"last_name":"Artmann","full_name":"Artmann, Matthias","first_name":"Matthias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["Approximate computing","design automation","parameter selection","circuit synthesis"],"publication":"Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19","status":"public","date_created":"2019-07-08T15:13:10Z","abstract":[{"text":"State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution.\r\n\r\nIn this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.","lang":"eng"}],"user_id":"49051"},{"publication_status":"published","publication_identifier":{"issn":["0743-7315"]},"department":[{"_id":"78"}],"title":"Zynq-based acceleration of robust high density myoelectric signal processing","language":[{"iso":"eng"}],"doi":"10.1016/j.jpdc.2018.07.004","date_updated":"2022-01-06T06:51:13Z","volume":123,"status":"public","date_created":"2019-07-12T13:13:55Z","publisher":"Elsevier","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Thombansen","first_name":"Georg","full_name":"Thombansen, Georg"},{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"last_name":"Kraus","first_name":"Florian","full_name":"Kraus, Florian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"keyword":["High density electromyography","FPGA acceleration","Medical signal processing","Pattern recognition","Prosthetics"],"publication":"Journal of Parallel and Distributed Computing","user_id":"398","abstract":[{"text":"Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels.","lang":"eng"}],"year":"2019","citation":{"apa":"Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., & Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing, 123, 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004","ama":"Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004","chicago":"Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen, Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing 123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.","bibtex":"@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based acceleration of robust high density myoelectric signal processing}, volume={123}, DOI={10.1016/j.jpdc.2018.07.004}, journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier}, author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen, Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89} }","mla":"Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing, vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.","short":"A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner, Journal of Parallel and Distributed Computing 123 (2019) 77–89.","ieee":"A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019."},"type":"journal_article","page":"77-89","intvolume":" 123","_id":"11950"},{"publication_status":"published","publication_identifier":{"issn":["1939-8018","1939-8115"]},"department":[{"_id":"78"}],"title":"An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology","language":[{"iso":"eng"}],"doi":"10.1007/s11265-018-1435-y","date_updated":"2022-01-06T06:51:27Z","volume":91,"status":"public","date_created":"2019-08-26T13:41:57Z","author":[{"last_name":"Hansmeier","id":"49992","first_name":"Tim","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Md Jubaer Hossain","full_name":"Pantho, Md Jubaer Hossain","last_name":"Pantho"},{"last_name":"Andrews","full_name":"Andrews, David","first_name":"David"}],"publication":"Journal of Signal Processing Systems","user_id":"49992","abstract":[{"text":"Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.","lang":"eng"}],"type":"journal_article","year":"2019","citation":{"short":"T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing Systems 91 (2019) 1259–1272.","ieee":"T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.","chicago":"Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019): 1259–72. https://doi.org/10.1007/s11265-018-1435-y.","apa":"Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems, 91(11), 1259–1272. https://doi.org/10.1007/s11265-018-1435-y","ama":"Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y","mla":"Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems, vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.","bibtex":"@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}, volume={91}, DOI={10.1007/s11265-018-1435-y}, number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019}, pages={1259–1272} }"},"page":"1259 - 1272","issue":"11","intvolume":" 91","_id":"12967"},{"_id":"15422","date_updated":"2022-01-06T06:52:25Z","series_title":"Advances in Nature and Biologically Inspired Computing","citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer, 2019.","ama":"Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In: World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer; 2019.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In World Congress on Nature and Biologically Inspired Computing (NaBIC). Springer.","mla":"Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and Biologically Inspired Computing}, title={Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances in Nature and Biologically Inspired Computing} }","short":"N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019."},"year":"2019","type":"conference","language":[{"iso":"eng"}],"title":"Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor","user_id":"398","publication":"World Congress on Nature and Biologically Inspired Computing (NaBIC)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-12-30T13:55:49Z","status":"public"},{"date_updated":"2022-01-06T06:52:39Z","_id":"15883","type":"mastersthesis","year":"2019","citation":{"short":"S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded Platforms, 2019.","ieee":"S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019.","apa":"Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine on embedded platforms.","ama":"Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded Platforms.; 2019.","chicago":"Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms, 2019.","bibtex":"@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019} }","mla":"Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms. 2019."},"supervisor":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"}],"language":[{"iso":"eng"}],"title":"Incremental learning with Support Vector Machine on embedded platforms","user_id":"61186","department":[{"_id":"78"}],"author":[{"first_name":"Shankar","full_name":"Kumar Jeyakumar, Shankar","last_name":"Kumar Jeyakumar"}],"date_created":"2020-02-11T16:43:38Z","status":"public"}]