[{"title":"An AR-based Training and Assessment System for Myoelectrical Prosthetic Control","user_id":"3118","status":"public","date_created":"2019-07-10T09:25:11Z","author":[{"full_name":"Kaltschmidt, Christian","first_name":"Christian","last_name":"Kaltschmidt"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"_id":"10613","date_updated":"2022-01-06T06:50:47Z","type":"bachelorsthesis","year":"2017","citation":{"short":"C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control, Paderborn University, 2017.","ieee":"C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","ama":"Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University; 2017.","apa":"Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University.","chicago":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.","bibtex":"@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }","mla":"Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017."},"language":[{"iso":"eng"}]},{"_id":"10630","date_updated":"2022-01-06T06:50:49Z","doi":"10.23919/DATE.2017.7927137","language":[{"iso":"eng"}],"year":"2017","citation":{"mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” Design, Automation and Test in Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={10.23919/DATE.2017.7927137}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137","chicago":"Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens, and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” In Design, Automation and Test in Europe (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927137.","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in Design, Automation and Test in Europe (DATE), 2017.","short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017."},"type":"conference","user_id":"3118","title":"A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller","department":[{"_id":"78"}],"publication":"Design, Automation and Test in Europe (DATE)","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"full_name":"Thombansen, Georg","first_name":"Georg","last_name":"Thombansen"},{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"},{"last_name":"Wiens","full_name":"Wiens, Alex","first_name":"Alex"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:02:56Z","status":"public"},{"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"}],"type":"mastersthesis","year":"2017","citation":{"short":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA, Paderborn University, 2017.","ieee":"U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","chicago":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","apa":"Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University.","ama":"Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University; 2017.","mla":"Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.","bibtex":"@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017} }"},"_id":"10666","date_updated":"2022-01-06T06:50:49Z","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Riaz","first_name":"Umair","full_name":"Riaz, Umair"}],"date_created":"2019-07-10T11:15:10Z","status":"public","user_id":"3118","title":"Acceleration of Industrial Analytics Functions on a Platform FPGA"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"bibtex":"@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}, DOI={10.23919/DATE.2017.7927096}, booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017} }","mla":"Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design, Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.","chicago":"Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.","apa":"Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE). https://doi.org/10.23919/DATE.2017.7927096","ama":"Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096","ieee":"N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.","short":"N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation and Test in Europe Conf. (DATE), 2017."},"year":"2017","doi":"10.23919/DATE.2017.7927096","_id":"10672","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:17:58Z","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"last_name":"Ashraf","full_name":"Ashraf, Ishraq Ibne","first_name":"Ishraq Ibne"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proc. Design, Automation and Test in Europe Conf. (DATE)","user_id":"3118","title":"Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor"},{"status":"public","date_created":"2019-07-10T11:22:59Z","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","user_id":"398","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","language":[{"iso":"eng"}],"citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144"},"year":"2017","type":"conference","page":"215-218","doi":"10.1109/FPT.2017.8280144","_id":"10676","date_updated":"2022-01-06T06:50:49Z"},{"type":"journal_article","citation":{"short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) (2017).","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES).","ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017} }","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017."},"year":"2017","date_updated":"2022-01-06T06:50:49Z","_id":"10692","department":[{"_id":"78"}],"publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)","author":[{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Martin","full_name":"Braun, Martin","last_name":"Braun"}],"date_created":"2019-07-10T11:29:58Z","status":"public","title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies","user_id":"3118"},{"department":[{"_id":"78"}],"author":[{"last_name":"Dietrich","full_name":"Dietrich, Andreas","first_name":"Andreas"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:43:32Z","status":"public","title":"Reconfigurable Cryptographic Services","user_id":"3118","citation":{"short":"A. Dietrich, Reconfigurable Cryptographic Services, Paderborn University, 2017.","ieee":"A. Dietrich, Reconfigurable Cryptographic Services. Paderborn University, 2017.","chicago":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.","apa":"Dietrich, A. (2017). Reconfigurable Cryptographic Services. Paderborn University.","ama":"Dietrich A. Reconfigurable Cryptographic Services. Paderborn University; 2017.","mla":"Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.","bibtex":"@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn University}, author={Dietrich, Andreas}, year={2017} }"},"year":"2017","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"_id":"10708","date_updated":"2022-01-06T06:50:50Z"},{"doi":"10.1049/joe.2017.0032","_id":"10740","date_updated":"2022-01-06T06:50:50Z","type":"journal_article","citation":{"short":"C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017) 19pp.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.","ama":"Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032","apa":"Shen, C., Kaufmann, P., & Braun, M. (2017). Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering, 19pp. https://doi.org/10.1049/joe.2017.0032","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, 19pp. https://doi.org/10.1049/joe.2017.0032.","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032}, journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={19pp} }","mla":"Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.” The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032."},"year":"2017","page":"19pp","title":"Fast Network Restoration by Partitioning of Parallel Black Start Zones","user_id":"3118","status":"public","date_created":"2019-07-10T11:59:38Z","author":[{"first_name":"Cong","full_name":"Shen, Cong","last_name":"Shen"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"department":[{"_id":"78"}],"publication":"The Journal of Engineering"},{"_id":"10759","date_updated":"2022-01-06T06:50:50Z","type":"book","citation":{"ieee":"G. Squillero et al., Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017.","short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 20th European Conference, EvoApplications, Springer, 2017.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2017, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 20th European Conference, EvoApplications}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2017}, collection={Lecture Notes in Computer Science} }","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2017). Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer.","ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer; 2017.","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Lecture Notes in Computer Science. Springer, 2017."},"year":"2017","series_title":"Lecture Notes in Computer Science","title":"Applications of Evolutionary Computation - 20th European Conference, EvoApplications","user_id":"3118","status":"public","date_created":"2019-07-10T12:06:37Z","author":[{"last_name":"Squillero","first_name":"Giovanni","full_name":"Squillero, Giovanni"},{"first_name":"Paolo","full_name":"Burelli, Paolo","last_name":"Burelli"},{"last_name":"M. Mora","first_name":"Antonio","full_name":"M. Mora, Antonio"},{"first_name":"Alexandros","full_name":"Agapitos, Alexandros","last_name":"Agapitos"},{"full_name":"S. Bush, William","first_name":"William","last_name":"S. Bush"},{"last_name":"Cagnoni","first_name":"Stefano","full_name":"Cagnoni, Stefano"},{"first_name":"Carlos","full_name":"Cotta, Carlos","last_name":"Cotta"},{"full_name":"De Falco, Ivanoe","first_name":"Ivanoe","last_name":"De Falco"},{"last_name":"Della Cioppa","full_name":"Della Cioppa, Antonio","first_name":"Antonio"},{"last_name":"Divina","full_name":"Divina, Federico","first_name":"Federico"},{"full_name":"Eiben, A.E.","first_name":"A.E.","last_name":"Eiben"},{"first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"last_name":"Fern{\\'a}ndez de Vega","first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"last_name":"Haasdijk","first_name":"Evert","full_name":"Haasdijk, Evert"},{"first_name":"J.","full_name":"Ignacio Hidalgo, J.","last_name":"Ignacio Hidalgo"},{"last_name":"Kampouridis","first_name":"Michael","full_name":"Kampouridis, Michael"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Mavrovouniotis, Michalis","first_name":"Michalis","last_name":"Mavrovouniotis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"first_name":"Robert","full_name":"Schaefer, Robert","last_name":"Schaefer"},{"first_name":"Kevin","full_name":"Sim, Kevin","last_name":"Sim"},{"last_name":"Tarantino","first_name":"Ernesto","full_name":"Tarantino, Ernesto"},{"last_name":"Urquhart","first_name":"Neil","full_name":"Urquhart, Neil"},{"first_name":"Mengjie","full_name":"Zhang (editors), Mengjie","last_name":"Zhang (editors)"}],"publisher":"Springer","department":[{"_id":"78"}]},{"language":[{"iso":"eng"}],"type":"conference","year":"2017","citation":{"ieee":"P. Kaufmann and R. Kalkreuth, “Parametrizing Cartesian Genetic Programming: An Empirical Study,” in KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, 2017.","short":"P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017.","bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={Parametrizing Cartesian Genetic Programming: An Empirical Study}, DOI={10.1007/978-3-319-67190-1_26}, booktitle={KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}, publisher={Springer International Publishing}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","mla":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.","chicago":"Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.” In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing, 2017. https://doi.org/10.1007/978-3-319-67190-1_26.","apa":"Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26","ama":"Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26"},"date_updated":"2022-01-06T06:50:50Z","_id":"10760","doi":"10.1007/978-3-319-67190-1_26","publisher":"Springer International Publishing","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Kalkreuth, Roman","first_name":"Roman","last_name":"Kalkreuth"}],"department":[{"_id":"78"}],"publication":"KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI","status":"public","date_created":"2019-07-10T12:06:38Z","user_id":"3118","title":"Parametrizing Cartesian Genetic Programming: An Empirical Study"},{"language":[{"iso":"eng"}],"year":"2017","type":"conference","citation":{"bibtex":"@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}, DOI={10.1109/AHS.2017.8046380}, booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann, Paul and Ho, Nam and Platzner, Marco}, year={2017} }","mla":"Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” Adaptive Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.","ama":"Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380","apa":"Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380","chicago":"Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” In Adaptive Hardware and Systems (AHS). IEEE, 2017. https://doi.org/10.1109/AHS.2017.8046380.","ieee":"P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,” in Adaptive Hardware and Systems (AHS), 2017.","short":"P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017."},"_id":"10761","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/AHS.2017.8046380","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"Adaptive Hardware and Systems (AHS)","status":"public","date_created":"2019-07-10T12:07:01Z","user_id":"3118","title":"Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches"},{"type":"conference","citation":{"bibtex":"@inproceedings{Kaufmann_Kalkreuth_2017, title={An Empirical Study on the Parametrization of Cartesian Genetic Programming}, DOI={10.1145/3067695.3075980}, booktitle={Genetic and Evolutionary Computation (GECCO), Compendium}, publisher={ACM}, author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }","mla":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017, doi:10.1145/3067695.3075980.","chicago":"Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), Compendium. ACM, 2017. https://doi.org/10.1145/3067695.3075980.","ama":"Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium. ACM; 2017. doi:10.1145/3067695.3075980","apa":"Kaufmann, P., & Kalkreuth, R. (2017). An Empirical Study on the Parametrization of Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO), Compendium. ACM. https://doi.org/10.1145/3067695.3075980","ieee":"P. Kaufmann and R. Kalkreuth, “An Empirical Study on the Parametrization of Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), Compendium, 2017.","short":"P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017."},"year":"2017","doi":"10.1145/3067695.3075980","date_updated":"2022-01-06T06:50:50Z","_id":"10762","date_created":"2019-07-10T12:07:03Z","status":"public","publication":"Genetic and Evolutionary Computation (GECCO), Compendium","department":[{"_id":"78"}],"publisher":"ACM","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Roman","full_name":"Kalkreuth, Roman","last_name":"Kalkreuth"}],"title":"An Empirical Study on the Parametrization of Cartesian Genetic Programming","user_id":"3118"},{"doi":"10.1109/ReCoSoC.2017.8016147","_id":"10780","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"page":"1-8","citation":{"ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147","apa":"Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8."},"year":"2017","type":"conference","user_id":"3118","title":"Computational self-awareness as design approach for visual sensor nodes","date_created":"2019-07-10T12:13:15Z","status":"public","publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"department":[{"_id":"78"}],"author":[{"last_name":"Guettatfi","first_name":"Zakarya","full_name":"Guettatfi, Zakarya"},{"last_name":"Hübner","first_name":"Philipp","full_name":"Hübner, Philipp"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"}]},{"title":"I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems","user_id":"398","place":"Cham","publication_identifier":{"isbn":["9783319625683","9783319625690"],"issn":["1865-0929","1865-0937"]},"publication_status":"published","status":"public","date_created":"2019-11-12T08:33:13Z","publisher":"Springer ","author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"last_name":"Abdallah","first_name":"Riadh Ben","full_name":"Abdallah, Riadh Ben"},{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Communications in Computer and Information Science","department":[{"_id":"78"}],"doi":"10.1007/978-3-319-62569-0_8","date_updated":"2022-01-06T06:52:10Z","_id":"14893","type":"conference","citation":{"bibtex":"@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={10.1007/978-3-319-62569-0_8}, booktitle={Communications in Computer and Information Science}, publisher={Springer }, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}, year={2017} }","mla":"Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” Communications in Computer and Information Science, Springer , 2017, doi:10.1007/978-3-319-62569-0_8.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In Communications in Computer and Information Science. Cham: Springer , 2017. https://doi.org/10.1007/978-3-319-62569-0_8.","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In Communications in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8","ama":"Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: Communications in Computer and Information Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems,” in Communications in Computer and Information Science, 2017.","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017."},"year":"2017","language":[{"iso":"eng"}]},{"_id":"222","page":"112--122","year":"2016","type":"journal_article","citation":{"apa":"Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005.","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={10.1016/j.compeleceng.2016.04.005}, journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering (2016) 112--122.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers & Electrical Engineering, pp. 112--122, 2016."},"abstract":[{"text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.","lang":"eng"}],"user_id":"477","ddc":["040"],"file":[{"date_created":"2018-03-21T10:36:08Z","file_name":"222-1-s2.0-S0045790616300684-main.pdf","access_level":"closed","file_size":931048,"creator":"florida","file_id":"1511","date_updated":"2018-03-21T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"Computers & Electrical Engineering","file_date_updated":"2018-03-21T10:36:08Z","author":[{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"last_name":"Bockhorn","full_name":"Bockhorn, Arne","first_name":"Arne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Elsevier","date_created":"2017-10-17T12:41:35Z","has_accepted_license":"1","status":"public","date_updated":"2022-01-06T06:55:29Z","doi":"10.1016/j.compeleceng.2016.04.005","language":[{"iso":"eng"}],"title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","department":[{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}]},{"date_updated":"2022-01-06T07:02:42Z","_id":"5812","doi":"10.1109/reconfig.2015.7393312","citation":{"mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","chicago":"Boschmann, Alexander, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","ama":"Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","apa":"Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. https://doi.org/10.1109/reconfig.2015.7393312","ieee":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2016.","short":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016."},"type":"conference","year":"2016","language":[{"iso":"eng"}],"extern":"1","title":"FPGA-based acceleration of high density myoelectric signal processing","user_id":"14053","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Linus","full_name":"Witschen, Linus","last_name":"Witschen"},{"first_name":"Georg","full_name":"Thombansen, Georg","last_name":"Thombansen"},{"id":"14053","last_name":"Kraus","full_name":"Kraus, Florian","first_name":"Florian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","status":"public","date_created":"2018-11-23T15:00:28Z"},{"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Cedric Mertens, Jan","first_name":"Jan","last_name":"Cedric Mertens"}],"date_created":"2019-07-10T09:23:26Z","status":"public","title":"Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion","user_id":"3118","year":"2016","type":"mastersthesis","citation":{"short":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion, Paderborn University, 2016.","ieee":"J. Cedric Mertens, Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","chicago":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016.","apa":"Cedric Mertens, J. (2016). Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University.","ama":"Cedric Mertens J. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University; 2016.","bibtex":"@book{Cedric Mertens_2016, title={Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion}, publisher={Paderborn University}, author={Cedric Mertens, Jan}, year={2016} }","mla":"Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \\& IMU Sensor Fusion. Paderborn University, 2016."},"language":[{"iso":"eng"}],"_id":"10612","date_updated":"2022-01-06T06:50:47Z"},{"date_updated":"2022-01-06T06:50:47Z","_id":"10616","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"citation":{"short":"A.S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware, Paderborn University, 2016.","ieee":"A. S. Nassery, Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","ama":"Nassery AS. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University; 2016.","apa":"Nassery, A. S. (2016). Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University.","chicago":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.","bibtex":"@book{Nassery_2016, title={Implementation of Bilinear Pairings on Reconfigurable Hardware}, publisher={Paderborn University}, author={Nassery, Abdul Sami}, year={2016} }","mla":"Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016."},"year":"2016","type":"mastersthesis","user_id":"3118","title":"Implementation of Bilinear Pairings on Reconfigurable Hardware","status":"public","date_created":"2019-07-10T09:25:14Z","publisher":"Paderborn University","author":[{"last_name":"Nassery","first_name":"Abdul Sami","full_name":"Nassery, Abdul Sami"}],"department":[{"_id":"78"}]},{"_id":"10617","date_updated":"2022-01-06T06:50:47Z","type":"mastersthesis","year":"2016","citation":{"mla":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.","bibtex":"@book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }","chicago":"Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.","ama":"Amin O. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University; 2016.","apa":"Amin, O. (2016). Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University.","ieee":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method. Paderborn University, 2016.","short":"O. Amin, Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method, Paderborn University, 2016."},"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"language":[{"iso":"eng"}],"title":"Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method","user_id":"3118","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Omair","full_name":"Amin, Omair","last_name":"Amin"}],"date_created":"2019-07-10T09:25:15Z","status":"public"},{"type":"conference","citation":{"short":"J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.","ieee":"J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs,” in Euromicro Conference on Digital System Design (DSD), 2016.","apa":"Anwer, J., & Platzner, M. (2016). Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In Euromicro Conference on Digital System Design (DSD). https://doi.org/10.1109/DSD.2016.35","ama":"Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System Design (DSD). ; 2016. doi:10.1109/DSD.2016.35","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” In Euromicro Conference on Digital System Design (DSD), 2016. https://doi.org/10.1109/DSD.2016.35.","mla":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” Euromicro Conference on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.","bibtex":"@inproceedings{Anwer_Platzner_2016, title={Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}, DOI={10.1109/DSD.2016.35}, booktitle={Euromicro Conference on Digital System Design (DSD)}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2016} }"},"year":"2016","language":[{"iso":"eng"}],"_id":"10622","date_updated":"2022-01-06T06:50:48Z","doi":"10.1109/DSD.2016.35","publication":"Euromicro Conference on Digital System Design (DSD)","department":[{"_id":"78"}],"author":[{"last_name":"Anwer","full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2019-07-10T09:33:00Z","status":"public","title":"Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs","user_id":"3118"},{"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Dosen","first_name":"Strahinja","full_name":"Dosen, Strahinja"},{"full_name":"Werner, Andreas","first_name":"Andreas","last_name":"Werner"},{"last_name":"Raies","first_name":"Ali","full_name":"Raies, Ali"},{"first_name":"Dario","full_name":"Farina, Dario","last_name":"Farina"}],"department":[{"_id":"78"}],"publication":"Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)","status":"public","date_created":"2019-07-10T11:02:57Z","user_id":"3118","title":"A novel immersive augmented reality system for prosthesis training and assessment","type":"conference","year":"2016","citation":{"ieee":"A. Boschmann, S. Dosen, A. Werner, A. Raies, and D. Farina, “A novel immersive augmented reality system for prosthesis training and assessment,” in Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","short":"A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","bibtex":"@inproceedings{Boschmann_Dosen_Werner_Raies_Farina_2016, title={A novel immersive augmented reality system for prosthesis training and assessment}, booktitle={Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)}, author={Boschmann, Alexander and Dosen, Strahinja and Werner, Andreas and Raies, Ali and Farina, Dario}, year={2016} }","mla":"Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","chicago":"Boschmann, Alexander, Strahinja Dosen, Andreas Werner, Ali Raies, and Dario Farina. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.","apa":"Boschmann, A., Dosen, S., Werner, A., Raies, A., & Farina, D. (2016). A novel immersive augmented reality system for prosthesis training and assessment. In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI).","ama":"Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016."},"_id":"10631","date_updated":"2022-01-06T06:50:49Z"},{"doi":"10.1016/j.tcs.2016.06.029","intvolume":" 644","_id":"10661","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"citation":{"bibtex":"@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science 644 (2016): 53–62. https://doi.org/10.1016/j.tcs.2016.06.029.","apa":"Graf, T., & Platzner, M. (2016). Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science, 644, 53–62. https://doi.org/10.1016/j.tcs.2016.06.029","ama":"Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62. doi:10.1016/j.tcs.2016.06.029","ieee":"T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016.","short":"T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62."},"year":"2016","type":"journal_article","page":"53-62","user_id":"3118","title":"Adaptive playouts for online learning of policies during Monte Carlo Tree Search","status":"public","date_created":"2019-07-10T11:14:43Z","volume":644,"publisher":"Elsevier","author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"Journal Theoretical Computer Science"},{"title":"Beschleunigte Simulation elektrischer Stromnetze mit GPUs","user_id":"3118","author":[{"last_name":"Horstmann","full_name":"Horstmann, Jens","first_name":"Jens"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:30:20Z","_id":"10695","date_updated":"2022-01-06T06:50:49Z","year":"2016","type":"bachelorsthesis","citation":{"ama":"Horstmann J. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University; 2016.","apa":"Horstmann, J. (2016). Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University.","chicago":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","mla":"Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.","bibtex":"@book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }","short":"J. Horstmann, Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs, Paderborn University, 2016.","ieee":"J. Horstmann, Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University, 2016."},"language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}]},{"title":"Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control","user_id":"3118","volume":87,"date_created":"2019-07-10T11:42:59Z","status":"public","publication":"Renewable Energy","department":[{"_id":"78"}],"author":[{"full_name":"Ma, Chenjie","first_name":"Chenjie","last_name":"Ma"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Töbermann","first_name":"J.-Christian","full_name":"Töbermann, J.-Christian"},{"last_name":"Braun","first_name":"Martin","full_name":"Braun, Martin"}],"publisher":"Elsevier","doi":"10.1016/j.renene.2015.07.083","issue":"(part 2)","_id":"10705","date_updated":"2022-01-06T06:50:50Z","intvolume":" 87","page":"946-953","citation":{"ieee":"C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016.","short":"C. Ma, P. Kaufmann, J.-C. Töbermann, M. Braun, Renewable Energy 87 (2016) 946–953.","bibtex":"@article{Ma_Kaufmann_Töbermann_Braun_2016, title={Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}, volume={87}, DOI={10.1016/j.renene.2015.07.083}, number={(part 2)}, journal={Renewable Energy}, publisher={Elsevier}, author={Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}, year={2016}, pages={946–953} }","mla":"Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083.","chicago":"Ma, Chenjie, Paul Kaufmann, J.-Christian Töbermann, and Martin Braun. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy 87, no. (part 2) (2016): 946–53. https://doi.org/10.1016/j.renene.2015.07.083.","ama":"Ma C, Kaufmann P, Töbermann J-C, Braun M. Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy. 2016;87((part 2)):946-953. doi:10.1016/j.renene.2015.07.083","apa":"Ma, C., Kaufmann, P., Töbermann, J.-C., & Braun, M. (2016). Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy, 87((part 2)), 946–953. https://doi.org/10.1016/j.renene.2015.07.083"},"year":"2016","type":"journal_article","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:50:50Z","_id":"10706","supervisor":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"year":"2016","citation":{"ieee":"V. Makeswaran, Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","short":"V. Makeswaran, Operating System Support for Reconfigurable Cache, Paderborn University, 2016.","mla":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","bibtex":"@book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }","chicago":"Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.","apa":"Makeswaran, V. (2016). Operating System Support for Reconfigurable Cache. Paderborn University.","ama":"Makeswaran V. Operating System Support for Reconfigurable Cache. Paderborn University; 2016."},"type":"mastersthesis","user_id":"3118","title":"Operating System Support for Reconfigurable Cache","publisher":"Paderborn University","author":[{"full_name":"Makeswaran, Vignesh","first_name":"Vignesh","last_name":"Makeswaran"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:43:30Z"},{"date_updated":"2022-01-06T06:50:50Z","_id":"10707","type":"mastersthesis","citation":{"ieee":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","short":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform, Paderborn University, 2016.","bibtex":"@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }","mla":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.","apa":"Ibne Ashraf, I. (2016). Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University.","ama":"Ibne Ashraf I. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University; 2016.","chicago":"Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016."},"year":"2016","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"title":"Private/Shared Data Classification and Implementation for a Multi-Softcore Platform","user_id":"3118","status":"public","date_created":"2019-07-10T11:43:31Z","author":[{"last_name":"Ibne Ashraf","first_name":"Ishraq","full_name":"Ibne Ashraf, Ishraq"}],"publisher":"Paderborn University","department":[{"_id":"78"}]},{"series_title":"ReConFig","page":"1-8","year":"2016","type":"conference","citation":{"chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 1–8. ReConFig, 2016. https://doi.org/10.1109/ReConFig.2016.7857193.","apa":"Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193","ama":"Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.","bibtex":"@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={10.1109/ReConFig.2016.7857193}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }","short":"S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on, 2016, pp. 1–8."},"language":[{"iso":"eng"}],"_id":"10712","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/ReConFig.2016.7857193","publication":"Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on","department":[{"_id":"78"}],"author":[{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:47:25Z","status":"public","title":"Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level","user_id":"3118"},{"_id":"10755","date_updated":"2022-01-06T06:50:50Z","citation":{"short":"M. Schmidt, Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung, Paderborn University, 2016.","ieee":"M. Schmidt, Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University, 2016.","ama":"Schmidt M. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University; 2016.","apa":"Schmidt, M. (2016). Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University.","chicago":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","mla":"Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.","bibtex":"@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }"},"year":"2016","type":"bachelorsthesis","language":[{"iso":"eng"}],"title":"Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung","user_id":"3118","author":[{"first_name":"Marco","full_name":"Schmidt, Marco","last_name":"Schmidt"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:05:20Z"},{"volume":9597,"date_created":"2019-07-10T12:06:36Z","status":"public","department":[{"_id":"78"}],"publisher":"Springer","author":[{"last_name":"Squillero","full_name":"Squillero, Giovanni","first_name":"Giovanni"},{"last_name":"Burelli","full_name":"Burelli, Paolo","first_name":"Paolo"},{"last_name":"M. Mora","full_name":"M. Mora, Antonio","first_name":"Antonio"},{"first_name":"Alexandros","full_name":"Agapitos, Alexandros","last_name":"Agapitos"},{"full_name":"S. Bush, William","first_name":"William","last_name":"S. Bush"},{"last_name":"Cagnoni","full_name":"Cagnoni, Stefano","first_name":"Stefano"},{"full_name":"Cotta, Carlos","first_name":"Carlos","last_name":"Cotta"},{"first_name":"Ivanoe","full_name":"De Falco, Ivanoe","last_name":"De Falco"},{"last_name":"Della Cioppa","first_name":"Antonio","full_name":"Della Cioppa, Antonio"},{"last_name":"Divina","full_name":"Divina, Federico","first_name":"Federico"},{"full_name":"Eiben, A.E.","first_name":"A.E.","last_name":"Eiben"},{"first_name":"Anna","full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco","last_name":"Fern{\\'a}ndez de Vega"},{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"first_name":"Evert","full_name":"Haasdijk, Evert","last_name":"Haasdijk"},{"last_name":"Ignacio Hidalgo","first_name":"J.","full_name":"Ignacio Hidalgo, J."},{"last_name":"Kampouridis","full_name":"Kampouridis, Michael","first_name":"Michael"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Mavrovouniotis","first_name":"Michalis","full_name":"Mavrovouniotis, Michalis"},{"first_name":"Trung","full_name":"Thanh Nguyen, Trung","last_name":"Thanh Nguyen"},{"full_name":"Schaefer, Robert","first_name":"Robert","last_name":"Schaefer"},{"last_name":"Sim","first_name":"Kevin","full_name":"Sim, Kevin"},{"full_name":"Tarantino, Ernesto","first_name":"Ernesto","last_name":"Tarantino"},{"first_name":"Neil","full_name":"Urquhart, Neil","last_name":"Urquhart"},{"full_name":"Zhang (editors), Mengjie","first_name":"Mengjie","last_name":"Zhang (editors)"}],"title":"Applications of Evolutionary Computation - 19th European Conference, EvoApplications","user_id":"3118","year":"2016","type":"book","citation":{"short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 19th European Conference, EvoApplications, Springer, 2016.","ieee":"G. Squillero et al., Applications of Evolutionary Computation - 19th European Conference, EvoApplications, vol. 9597. Springer, 2016.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2016). Applications of Evolutionary Computation - 19th European Conference, EvoApplications (Vol. 9597). Springer.","ama":"Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol 9597. Springer; 2016.","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597. Lecture Notes in Computer Science. Springer, 2016.","mla":"Squillero, Giovanni, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597, Springer, 2016.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2016, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 19th European Conference, EvoApplications}, volume={9597}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2016}, collection={Lecture Notes in Computer Science} }"},"series_title":"Lecture Notes in Computer Science","intvolume":" 9597","_id":"10758","date_updated":"2022-01-06T06:50:50Z"},{"_id":"10766","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"year":"2016","citation":{"short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In Proceedings of the 30th European Simulation and Modelling Conference (ESM).","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","mla":"Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }"},"type":"conference","user_id":"3118","title":"RCo-Design: New Visual Environment for Reconfigurable Embedded Systems","date_created":"2019-07-10T12:07:54Z","status":"public","publication":"Proceedings of the 30th European Simulation and Modelling Conference (ESM)","department":[{"_id":"78"}],"author":[{"full_name":"Ghribi, Ines","first_name":"Ines","last_name":"Ghribi"},{"full_name":"Ben Abdallah, Riadh","first_name":"Riadh","last_name":"Ben Abdallah"},{"last_name":"Khalgui","first_name":"Mohamed","full_name":"Khalgui, Mohamed"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}]},{"type":"conference","year":"2016","citation":{"short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195).","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 185–95, 2016.","mla":"Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }"},"page":"185-195","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10768","author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"last_name":"Ben Abdallah","full_name":"Ben Abdallah, Riadh","first_name":"Riadh"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T12:07:56Z","title":"New Co-design Methodology for Real-time Embedded Systems","user_id":"3118"},{"volume":"PP","status":"public","date_created":"2019-07-10T12:08:14Z","publisher":"IEEE","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"first_name":"Giovanni","full_name":"De Micheli, Giovanni","last_name":"De Micheli"}],"publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","department":[{"_id":"78"}],"title":"Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation","user_id":"3118","extern":"1","type":"journal_article","citation":{"apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908.","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016."},"year":"2016","page":"1-1","language":[{"iso":"eng"}],"doi":"10.1109/TCAD.2016.2547908","issue":"99","date_updated":"2022-01-06T06:50:50Z","_id":"10769"},{"language":[{"iso":"eng"}],"citation":{"short":"S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016.","ieee":"S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016.","chicago":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.","ama":"Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016.","apa":"Hermansen, S. (2016). Custom Memory Controller for ReconOS. Paderborn University.","bibtex":"@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }","mla":"Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016."},"year":"2016","type":"bachelorsthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10781","date_created":"2019-07-10T12:13:16Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Hermansen","first_name":"Sven","full_name":"Hermansen, Sven"}],"user_id":"3118","title":"Custom Memory Controller for ReconOS"},{"place":"Cham","abstract":[{"lang":"eng","text":"Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering."}],"user_id":"398","title":"Self-aware Computing Systems: An Engineering Approach","publisher":"Springer","department":[{"_id":"78"}],"status":"public","date_created":"2019-08-27T13:39:43Z","editor":[{"last_name":"Lewis","full_name":"Lewis, Peter R.","first_name":"Peter R."},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"},{"last_name":"Tørresen","first_name":"Jim","full_name":"Tørresen, Jim"},{"first_name":"Xin","full_name":"Yao, Xin","last_name":"Yao"}],"publication_identifier":{"issn":["1619-7127"],"isbn":["9783319396743","9783319396750"]},"publication_status":"published","date_updated":"2022-01-06T06:51:27Z","_id":"12972","doi":"10.1007/978-3-319-39675-0","language":[{"iso":"eng"}],"type":"book_editor","year":"2016","citation":{"short":"P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016.","ieee":"P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.","ama":"Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0","apa":"Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., & Yao, X. (Eds.). (2016). Self-aware Computing Systems: An Engineering Approach. Cham: Springer. https://doi.org/10.1007/978-3-319-39675-0","chicago":"Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer, 2016. https://doi.org/10.1007/978-3-319-39675-0.","bibtex":"@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={10.1007/978-3-319-39675-0}, publisher={Springer}, year={2016} }","mla":"Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0."}},{"year":"2016","citation":{"short":"A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ieee":"A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016.","ama":"Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312","apa":"Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312","chicago":"Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312."},"type":"conference","language":[{"iso":"eng"}],"conference":{"name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","location":"Mexiko City, Mexiko"},"_id":"15873","date_updated":"2022-01-06T06:52:38Z","doi":"10.1109/reconfig.2015.7393312","keyword":["Electromyography","Feature extraction","Delays","Hardware Pattern recognition","Prosthetics","High definition video"],"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Witschen","id":"49051","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"full_name":"Thombansen, Georg","first_name":"Georg","last_name":"Thombansen"},{"last_name":"Kraus","first_name":"Florian","full_name":"Kraus, Florian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","date_created":"2020-02-11T07:48:56Z","status":"public","title":"FPGA-based acceleration of high density myoelectric signal processing","user_id":"49051"},{"type":"conference","year":"2016","citation":{"chicago":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In Computer and Games, 2016.","ama":"Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.","apa":"Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games.","mla":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","short":"T. Graf, M. Platzner, in: Computer and Games, 2016.","ieee":"T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016."},"language":[{"iso":"eng"}],"_id":"13151","date_updated":"2022-01-06T06:51:29Z","department":[{"_id":"78"}],"publication":"Computer and Games","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-09-09T09:01:09Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","title":"Using Deep Convolutional Neural Networks in Monte Carlo Tree Search","user_id":"398"},{"year":"2016","citation":{"short":"T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016.","ieee":"T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016.","apa":"Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games.","ama":"Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In IEEE Computational Intelligence and Games, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","mla":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016."},"type":"conference","language":[{"iso":"eng"}],"_id":"13152","date_updated":"2022-01-06T06:51:29Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2019-09-09T09:06:39Z","status":"public","publication":"IEEE Computational Intelligence and Games","department":[{"_id":"78"}],"author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Monte-Carlo Simulation Balancing Revisited","user_id":"398"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:17Z","file":[{"date_created":"2018-03-21T13:02:30Z","file_name":"132-07533910.pdf","access_level":"closed","file_id":"1562","creator":"florida","file_size":911171,"relation":"main_file","success":1,"date_updated":"2018-03-21T13:02:30Z","content_type":"application/pdf"}],"author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"file_date_updated":"2018-03-21T13:02:30Z","publication":"Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)","user_id":"477","ddc":["040"],"abstract":[{"text":"Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.","lang":"eng"}],"type":"conference","citation":{"short":"T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","ieee":"T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","chicago":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910.","ama":"Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910","apa":"Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910","mla":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910.","bibtex":"@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }"},"year":"2016","page":"1--8","_id":"132","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"department":[{"_id":"78"}],"title":"Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware","language":[{"iso":"eng"}],"doi":"10.1109/ReCoSoC.2016.7533910","date_updated":"2022-01-06T06:51:30Z"},{"type":"book_chapter","year":"2016","citation":{"ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13"},"page":"227-244","_id":"29","quality_controlled":"1","publisher":"Springer International Publishing","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"}],"publication":"FPGAs for Software Programmers","status":"public","date_created":"2017-07-26T15:07:06Z","abstract":[{"lang":"eng","text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems."}],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:25:38Z","doi":"10.1007/978-3-319-26408-0_13","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"editor":[{"last_name":"Koch","first_name":"Dirk","full_name":"Koch, Dirk"},{"last_name":"Hannig","first_name":"Frank","full_name":"Hannig, Frank"},{"last_name":"Ziener","first_name":"Daniel","full_name":"Ziener, Daniel"}],"publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"publication_status":"published","project":[{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"place":"Cham","title":"ReconOS"},{"doi":"10.1007/978-3-319-39675-0_8","date_updated":"2023-09-26T13:27:44Z","language":[{"iso":"eng"}],"series_title":"Natural Computing Series (NCS)","title":"Self-aware Compute Nodes","place":"Cham","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"_id":"156","page":"145-165","type":"book_chapter","year":"2016","citation":{"bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165."},"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level."}],"date_created":"2017-10-17T12:41:22Z","status":"public","has_accepted_license":"1","file":[{"content_type":"application/pdf","date_updated":"2018-11-14T13:20:32Z","success":1,"relation":"main_file","file_size":833054,"creator":"aloesch","file_id":"5613","access_level":"closed","file_name":"chapter8.pdf","date_created":"2018-11-14T13:20:32Z"}],"publication":"Self-aware Computing Systems","file_date_updated":"2018-11-14T13:20:32Z","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publisher":"Springer International Publishing"},{"_id":"168","page":"912-917","citation":{"ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016."},"year":"2016","type":"conference","abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"ddc":["040"],"user_id":"15278","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2018-03-21T12:41:55Z","quality_controlled":"1","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"EDA Consortium / IEEE","file":[{"date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":261356,"file_id":"1541","creator":"florida","access_level":"closed","file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z"}],"date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}]},{"date_created":"2017-10-17T12:41:44Z","status":"public","has_accepted_license":"1","publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","file_date_updated":"2018-03-21T09:32:42Z","author":[{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Wu","full_name":"Wu, Sen","first_name":"Sen"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"file":[{"date_created":"2018-03-21T09:32:42Z","file_name":"269-paper_53.pdf","access_level":"closed","file_size":344309,"file_id":"1477","creator":"florida","date_updated":"2018-03-21T09:32:42Z","content_type":"application/pdf","relation":"main_file","success":1}],"ddc":["040"],"user_id":"477","abstract":[{"text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.","lang":"eng"}],"page":"365--372","type":"conference","citation":{"bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.","apa":"Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32","ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32","chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32.","ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372."},"year":"2015","_id":"269","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"department":[{"_id":"78"}],"title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach","language":[{"iso":"eng"}],"series_title":"LNCS","doi":"10.1007/978-3-319-16214-0_32","date_updated":"2022-01-06T06:57:30Z"},{"status":"public","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"date_created":"2018-06-26T14:06:07Z","publisher":"Universität Paderborn","author":[{"last_name":"Knorr","full_name":"Knorr, Christoph","first_name":"Christoph"}],"department":[{"_id":"78"}],"user_id":"477","title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","supervisor":[{"id":"43646","last_name":"Lösch","full_name":"Lösch, Achim","first_name":"Achim"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"language":[{"iso":"ger"}],"citation":{"ieee":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","mla":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.","apa":"Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn.","ama":"Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.","chicago":"Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015."},"year":"2015","type":"bachelorsthesis","date_updated":"2022-01-06T06:59:13Z","_id":"3364"},{"issue":"7","_id":"1772","intvolume":" 48","citation":{"bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20."},"type":"journal_article","year":"2015","page":"18-20","user_id":"16153","ddc":["000"],"status":"public","has_accepted_license":"1","date_created":"2018-03-23T14:06:12Z","volume":48,"file":[{"file_size":5605009,"file_id":"5313","creator":"ups","date_updated":"2018-11-02T15:47:45Z","content_type":"application/pdf","success":1,"relation":"main_file","date_created":"2018-11-02T15:47:45Z","file_name":"07163237.pdf","access_level":"closed"}],"author":[{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"publisher":"IEEE Computer Society","file_date_updated":"2018-11-02T15:47:45Z","publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"_id":"10615","date_updated":"2022-01-06T06:50:47Z","citation":{"short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.","ieee":"A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015.","chicago":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.","apa":"Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University.","ama":"Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }","mla":"Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015."},"year":"2015","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"title":"Self-Optimizing Organic Cache","user_id":"3118","status":"public","date_created":"2019-07-10T09:25:13Z","publisher":"Paderborn University","author":[{"first_name":"Abdullah Fathi","full_name":"Ahmed, Abdullah Fathi","last_name":"Ahmed"}],"department":[{"_id":"78"}]},{"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"}],"project":[{"grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_created":"2019-07-10T09:36:58Z","status":"public","publication_identifier":{"isbn":["978-3-8325-4155-2"]},"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies."}],"place":"Berlin","user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}],"page":"183","citation":{"short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }"},"type":"dissertation","year":"2015","date_updated":"2022-01-06T06:50:48Z","_id":"10624"},{"date_created":"2019-07-10T11:15:13Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"}],"publisher":"Paderborn University","title":"Evolution of Heat Flow Prediction Models for FPGA Devices","user_id":"3118","type":"mastersthesis","citation":{"chicago":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","ama":"Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.","apa":"Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University.","mla":"Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.","bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015.","ieee":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015."},"year":"2015","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}],"_id":"10668","date_updated":"2022-01-06T06:50:49Z"},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"}],"year":"2015","citation":{"ieee":"C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015.","mla":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.","bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }","apa":"Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University.","ama":"Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.","chicago":"Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015."},"type":"mastersthesis","_id":"10671","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:17:57Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Christian","full_name":"Haupt, Christian","last_name":"Haupt"}],"user_id":"3118","title":"Computer Vision basierte Klassifikation von HD EMG Signalen"},{"date_created":"2019-07-10T11:18:00Z","project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"status":"public","publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","department":[{"_id":"78"}],"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Ahmed","first_name":"Abdullah Fathi","full_name":"Ahmed, Abdullah Fathi"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"3118","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","language":[{"iso":"eng"}],"page":"1-7","year":"2015","type":"conference","citation":{"ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178."},"doi":"10.1109/AHS.2015.7231178","date_updated":"2022-01-06T06:50:49Z","_id":"10673"},{"user_id":"3118","title":"Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"}],"publisher":"ACM","department":[{"_id":"78"}],"publication":"Genetic and Evolutionary Computation (GECCO)","status":"public","date_created":"2019-07-10T11:30:00Z","date_updated":"2022-01-06T06:50:49Z","_id":"10693","year":"2015","type":"conference","citation":{"short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.","ieee":"P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416.","chicago":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic and Evolutionary Computation (GECCO), 409–16. ACM, 2015.","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.","apa":"Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM.","mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.","bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }"},"page":"409-416"}]