[{"date_updated":"2022-01-06T06:51:40Z","_id":"13637","year":"2009","type":"conference","citation":{"short":"H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","ieee":"H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009.","ama":"Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.","apa":"Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.","chicago":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009.","mla":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }"},"language":[{"iso":"eng"}],"title":"Program-driven Fine-grained Power Management for the Reconfigurable Mesh","user_id":"398","status":"public","date_created":"2019-10-04T22:22:02Z","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) "},{"user_id":"398","title":"An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning","date_created":"2019-10-04T22:22:52Z","status":"public","publication_status":"published","publication_identifier":{"isbn":["9781424443758"]},"publication":"Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"doi":"10.1109/fpt.2009.5377645","_id":"13638","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"2009","citation":{"mla":"Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645.","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645.","ama":"Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645","apa":"Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645","ieee":"M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), 2009.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009."},"type":"conference"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13639","type":"conference","citation":{"chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2009.","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.","apa":"Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.","bibtex":"@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.","short":"S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.","ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009."},"year":"2009","language":[{"iso":"eng"}],"title":"Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules","user_id":"398","status":"public","date_created":"2019-10-04T22:25:10Z","publisher":"IEEE","author":[{"first_name":"Stephanie","full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky"},{"full_name":"Kastens, Uwe","first_name":"Uwe","last_name":"Kastens"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)"},{"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2009.25","date_updated":"2023-09-26T13:51:44Z","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","page":"275-278","year":"2009","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25."},"type":"conference","_id":"2350","date_created":"2018-04-16T15:05:52Z","status":"public","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society","quality_controlled":"1","user_id":"15278","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}]},{"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","place":"Los Alamitos, CA, USA","abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"status":"public","date_created":"2018-04-06T15:18:24Z","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE Computer Society","quality_controlled":"1","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["EvoCache","evolvable hardware","computer architecture"],"_id":"2262","date_updated":"2023-09-26T13:53:11Z","language":[{"iso":"eng"}],"year":"2009","citation":{"ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009."},"type":"conference","page":"11-18"},{"place":"Los Alamitos, CA, USA","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","user_id":"15278","quality_controlled":"1","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","keyword":["IMORC","graphics"],"publication_identifier":{"isbn":["978-0-7695-3917-1"]},"status":"public","date_created":"2018-04-05T17:11:28Z","date_updated":"2023-09-26T13:52:32Z","_id":"2238","doi":"10.1109/ReConFig.2009.32","type":"conference","citation":{"mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124."},"year":"2009","page":"119-124","language":[{"iso":"eng"}]},{"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","user_id":"15278","publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"status":"public","date_created":"2018-04-06T15:15:47Z","quality_controlled":"1","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","NOC","KNN","accelerator"],"date_updated":"2023-09-26T13:52:52Z","_id":"2261","type":"conference","year":"2009","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344."},"page":"338-344","language":[{"iso":"eng"}]},{"type":"conference","citation":{"ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322."},"year":"2009","page":"319-322","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:53:30Z","_id":"2263","publication_identifier":{"isbn":["1-60132-101-5"]},"status":"public","date_created":"2018-04-06T15:19:51Z","quality_controlled":"1","author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"CSREA Press","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","place":"USA","abstract":[{"text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ","lang":"eng"}]},{"status":"public","date_created":"2018-04-17T10:59:40Z","publisher":"IEEE","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"first_name":"Stefan","full_name":"Lietsch, Stefan","last_name":"Lietsch"},{"full_name":"Thielemans, Kris","first_name":"Kris","last_name":"Thielemans"}],"publication":"IEEE Nuclear Science Symposium Conference Record (NSS)","department":[{"_id":"27"},{"_id":"78"}],"title":"A method for OSEM PET reconstruction on parallel architectures using STIR","user_id":"24135","year":"2008","citation":{"chicago":"Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198.","apa":"Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198","ama":"Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198","bibtex":"@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }","mla":"Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198.","short":"T. Beisel, S. Lietsch, K. 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IEEE; 2006.","mla":"Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","bibtex":"@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }"},"type":"conference","year":"2006","_id":"13624","date_updated":"2022-01-06T06:51:40Z","publication":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"first_name":"Roland","full_name":"Mühlenbernd, Roland","last_name":"Mühlenbernd"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-10-04T21:48:42Z","status":"public","user_id":"398","title":"Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions"},{"_id":"13625","date_updated":"2022-01-06T06:51:40Z","citation":{"chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","apa":"Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).","ama":"Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","short":"K. Danne, M. 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Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }"},"language":[{"iso":"eng"}],"_id":"13626","date_updated":"2022-01-06T06:51:40Z","status":"public","date_created":"2019-10-04T21:53:12Z","publisher":"IEEE CS Press","author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","user_id":"398"},{"department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy"],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society","date_created":"2018-04-17T14:34:03Z","status":"public","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"user_id":"24135","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","page":"213-218","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.","apa":"Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69."},"type":"conference","year":"2005","_id":"2411","date_updated":"2022-01-06T06:56:07Z","doi":"10.1109/ASAP.2005.69"}]