[{"date_updated":"2022-01-06T06:50:48Z","_id":"10623","citation":{"ieee":"T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007.","short":"T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007.","mla":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007.","bibtex":"@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }","chicago":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007.","apa":"Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University.","ama":"Beisel T. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University; 2007."},"year":"2007","type":"mastersthesis","language":[{"iso":"eng"}],"title":"Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen","user_id":"3118","department":[{"_id":"78"}],"author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"}],"publisher":"Paderborn University","date_created":"2019-07-10T09:36:57Z","status":"public"},{"language":[{"iso":"eng"}],"page":"1-2","type":"journal_article","year":"2007","citation":{"bibtex":"@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }","mla":"Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405.","chicago":"Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems 2007 (2007): 1–2. https://doi.org/10.1155/2007/28405.","ama":"Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405","apa":"Bergmann, N., Platzner, M., & Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems, 2007, 1–2. https://doi.org/10.1155/2007/28405","ieee":"N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” {EURASIP} Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007.","short":"N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2."},"intvolume":" 2007","_id":"10625","date_updated":"2022-01-06T06:50:48Z","doi":"10.1155/2007/28405","department":[{"_id":"78"}],"publication":"{EURASIP} Journal on Embedded Systems","author":[{"last_name":"Bergmann","first_name":"Neil","full_name":"Bergmann, Neil"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Teich","first_name":"Jürgen","full_name":"Teich, Jürgen"}],"publisher":"Springer Science+Business Media","date_created":"2019-07-10T09:40:11Z","status":"public","volume":2007,"user_id":"398","title":"Dynamically Reconfigurable Architectures (editorial)"},{"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","year":"2007","citation":{"short":"T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007.","ieee":"T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007.","ama":"Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007.","apa":"Ceylan, T., & Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University.","chicago":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007.","bibtex":"@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }","mla":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007."},"_id":"10643","date_updated":"2022-01-06T06:50:49Z","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Ceylan","first_name":"Toni","full_name":"Ceylan, Toni"},{"full_name":"Yalcin, Coni","first_name":"Coni","last_name":"Yalcin"}],"date_created":"2019-07-10T11:03:44Z","status":"public","user_id":"3118","title":"Distributed Simulation of mobile Robots using EyeSim"},{"language":[{"iso":"eng"}],"page":"295-302","year":"2007","citation":{"ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.","short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques 1, no. 4 (2007): 295–302. https://doi.org/10.1049/iet-cdt:20060186.","apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302. https://doi.org/10.1049/iet-cdt:20060186","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186"},"type":"journal_article","issue":"4","doi":"10.1049/iet-cdt:20060186","intvolume":" 1","_id":"10646","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:10:54Z","status":"public","volume":1,"publication_identifier":{"issn":["1751-8601"]},"department":[{"_id":"78"}],"keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"],"publication":"IET Computers Digital Techniques","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Mühlenbernd","first_name":"Roland","full_name":"Mühlenbernd, Roland"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"3118","title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware"},{"citation":{"short":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007.","ieee":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","chicago":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","ama":"Defo B. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University; 2007.","apa":"Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University.","bibtex":"@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }","mla":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007."},"year":"2007","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10647","status":"public","date_created":"2019-07-10T11:10:55Z","author":[{"first_name":"Bertrand","full_name":"Defo, Bertrand","last_name":"Defo"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"title":"A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization","user_id":"3118"},{"title":"Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme","user_id":"3118","status":"public","date_created":"2019-07-10T11:10:56Z","publisher":"Paderborn University","author":[{"full_name":"Döhre, Sven","first_name":"Sven","last_name":"Döhre"}],"department":[{"_id":"78"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10648","year":"2007","type":"mastersthesis","citation":{"mla":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","bibtex":"@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }","chicago":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","ama":"Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007.","apa":"Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University.","ieee":"S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007.","short":"S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007."},"language":[{"iso":"eng"}]},{"series_title":"LNCS","year":"2007","citation":{"ama":"Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In: Architecture of Computing Systems (ARCS). Vol 4415. LNCS. Springer; 2007:199-208.","apa":"Kaufmann, P., & Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.","chicago":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” In Architecture of Computing Systems (ARCS), 4415:199–208. LNCS. Springer, 2007.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }","mla":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” Architecture of Computing Systems (ARCS), vol. 4415, Springer, 2007, pp. 199–208.","short":"P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208.","ieee":"P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208."},"type":"conference","page":"199-208","language":[{"iso":"eng"}],"intvolume":" 4415","_id":"10689","date_updated":"2022-01-06T06:50:49Z","publisher":"Springer","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Architecture of Computing Systems (ARCS)","volume":4415,"status":"public","date_created":"2019-07-10T11:29:03Z","title":"Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution","user_id":"3118"},{"department":[{"_id":"78"}],"author":[{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"}],"publisher":"Paderborn University","alternative_title":["k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving Mechanism Acceleration"],"date_created":"2019-07-10T11:43:33Z","status":"public","title":"VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen","user_id":"3118","year":"2007","citation":{"short":"R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007.","ieee":"R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","chicago":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","ama":"Meiche R. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University; 2007.","apa":"Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University.","bibtex":"@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }","mla":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007."},"type":"bachelorsthesis","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10709"},{"_id":"10728","date_updated":"2022-01-06T06:50:50Z","citation":{"bibtex":"@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }","mla":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","chicago":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","ama":"Reisch W. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University; 2007.","apa":"Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University.","ieee":"W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","short":"W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007."},"year":"2007","type":"mastersthesis","language":[{"iso":"eng"}],"title":"Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS","user_id":"3118","department":[{"_id":"78"}],"author":[{"last_name":"Reisch","full_name":"Reisch, Waldemar","first_name":"Waldemar"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:54:46Z","status":"public"},{"citation":{"short":"E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007.","ieee":"E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007.","chicago":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007.","apa":"Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University.","ama":"Rethmeier E. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University; 2007.","bibtex":"@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }","mla":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007."},"year":"2007","type":"mastersthesis","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10729","status":"public","date_created":"2019-07-10T11:54:47Z","author":[{"last_name":"Rethmeier","full_name":"Rethmeier, Eike","first_name":"Eike"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"title":"Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem","user_id":"3118"},{"language":[{"iso":"eng"}],"page":"749-756","year":"2007","type":"conference","citation":{"short":"T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.","ieee":"T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.","chicago":"Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 15:749–56. Advances in Parallel Computing. IOS Press, 2007.","ama":"Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756.","apa":"Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.","mla":"Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), vol. 15, IOS Press, 2007, pp. 749–56.","bibtex":"@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances in Parallel Computing} }"},"series_title":"Advances in Parallel Computing","_id":"10735","intvolume":" 15","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T11:58:09Z","status":"public","volume":15,"publication":"Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)","department":[{"_id":"78"}],"publisher":"IOS Press","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"user_id":"398","title":"Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13627","doi":"10.1109/fpl.2007.4380623","language":[{"iso":"eng"}],"citation":{"chicago":"Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380623.","ama":"Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable Mesh Model. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380623","apa":"Giefers, H., & Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380623","mla":"Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380623.","bibtex":"@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation Based on the Reconfigurable Mesh Model}, DOI={10.1109/fpl.2007.4380623}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2007} }","short":"H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.","ieee":"H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable Mesh Model,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007."},"type":"conference","year":"2007","user_id":"398","title":"A Many-Core Implementation Based on the Reconfigurable Mesh Model","publisher":"IEEE","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)","status":"public","date_created":"2019-10-04T21:57:25Z","publication_identifier":{"isbn":["9781424410590","9781424410606"]},"publication_status":"published"},{"publisher":"IEEE","author":[{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T21:58:35Z","publication_identifier":{"isbn":["9781424410590","9781424410606"]},"publication_status":"published","user_id":"398","title":"ReconOS: An RTOS Supporting Hard-and Software Threads","language":[{"iso":"eng"}],"year":"2007","type":"conference","citation":{"short":"E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.","ieee":"E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.","ama":"Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686","apa":"Lübbers, E., & Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380686","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380686.","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.","bibtex":"@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }"},"date_updated":"2022-01-06T06:51:40Z","_id":"13628","doi":"10.1109/fpl.2007.4380686"},{"_id":"2401","date_updated":"2022-01-06T06:56:05Z","doi":"10.1109/FPT.2006.270344","type":"conference","year":"2006","citation":{"ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348.","short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344.","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344","apa":"Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344"},"page":"345-348","abstract":[{"lang":"eng","text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"title":"Optimal Temporal Partitioning based on Slowdown and Retiming","user_id":"24135","publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"keyword":["temporal partitioning","retiming","ILP"],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","department":[{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-17T13:43:21Z"},{"user_id":"3118","title":"Multi-objective Intrinsic Hardware Evolution","status":"public","date_created":"2019-07-10T11:28:14Z","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)","_id":"10688","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","apa":"Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD).","ama":"Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.","mla":"Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","bibtex":"@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }","short":"P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.","ieee":"P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006."},"year":"2006"},{"publisher":"Paderborn University","author":[{"first_name":"Roland","full_name":"Mühlenbernd, Roland","last_name":"Mühlenbernd"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:48:27Z","title":"FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks","user_id":"3118","year":"2006","type":"bachelorsthesis","citation":{"short":"R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006.","ieee":"R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006.","ama":"Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006.","apa":"Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University.","chicago":"Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006.","mla":"Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006.","bibtex":"@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }"},"language":[{"iso":"eng"}],"_id":"10716","date_updated":"2022-01-06T06:50:50Z"},{"user_id":"398","title":"Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions","publication":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"full_name":"Mühlenbernd, Roland","first_name":"Roland","last_name":"Mühlenbernd"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"IEEE","date_created":"2019-10-04T21:48:42Z","status":"public","date_updated":"2022-01-06T06:51:40Z","_id":"13624","language":[{"iso":"eng"}],"year":"2006","type":"conference","citation":{"ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006.","short":"K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","bibtex":"@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006.","apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE.","ama":"Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006."}},{"title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices","user_id":"398","author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","status":"public","date_created":"2019-10-04T21:51:29Z","_id":"13625","date_updated":"2022-01-06T06:51:40Z","type":"conference","citation":{"ieee":"K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","short":"K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","apa":"Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).","ama":"Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.","chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006."},"year":"2006","language":[{"iso":"eng"}]},{"status":"public","date_created":"2019-10-04T21:53:12Z","publisher":"IEEE CS Press","author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","user_id":"398","citation":{"short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006.","apa":"Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.","bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006."},"type":"conference","year":"2006","language":[{"iso":"eng"}],"_id":"13626","date_updated":"2022-01-06T06:51:40Z"},{"user_id":"24135","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"status":"public","date_created":"2018-04-17T14:34:03Z","publisher":"IEEE Computer Society","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","doi":"10.1109/ASAP.2005.69","_id":"2411","date_updated":"2022-01-06T06:56:07Z","citation":{"ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69","apa":"Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218."},"year":"2005","type":"conference","page":"213-218"},{"page":"63-73","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","apa":"Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004."},"year":"2005","type":"journal_article","_id":"2412","intvolume":" 29","date_updated":"2022-01-06T06:56:07Z","doi":"10.1016/j.micpro.2004.06.004","issue":"2-3","department":[{"_id":"518"},{"_id":"78"}],"publication":"Microprocessors and Microsystems","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Elsevier","volume":29,"date_created":"2018-04-17T14:36:10Z","status":"public","abstract":[{"lang":"eng","text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"title":"System-level performance evaluation of reconfigurable processors","user_id":"24135"},{"publication_identifier":{"isbn":["3902463031"]},"publication_status":"published","date_created":"2019-10-04T21:38:53Z","status":"public","publication":"Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)","department":[{"_id":"78"}],"author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"Periodic real-time scheduling for FPGA computers","user_id":"398","type":"conference","year":"2005","citation":{"ieee":"K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","short":"K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","mla":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005, doi:10.1109/wises.2005.1438720.","bibtex":"@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={10.1109/wises.2005.1438720}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","apa":"Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720","ama":"Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720","chicago":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. https://doi.org/10.1109/wises.2005.1438720."},"language":[{"iso":"eng"}],"doi":"10.1109/wises.2005.1438720","_id":"13621","date_updated":"2022-01-06T06:51:40Z"},{"department":[{"_id":"78"}],"publication":"Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2019-10-04T21:42:02Z","status":"public","user_id":"398","title":"Memory-demanding Periodic Real-time Applications on FPGA Computers","language":[{"iso":"eng"}],"type":"conference","citation":{"short":"K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","ieee":"K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005.","chicago":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","apa":"Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS).","ama":"Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.","mla":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","bibtex":"@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }"},"year":"2005","_id":"13622","date_updated":"2022-01-06T06:51:40Z"},{"department":[{"_id":"78"}],"publication":"Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)","author":[{"first_name":"Klaus","full_name":"Danne, Klaus","last_name":"Danne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE CS Press","date_created":"2019-10-04T21:42:46Z","status":"public","publication_identifier":{"isbn":["0780393627"]},"publication_status":"published","user_id":"398","title":"A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware","language":[{"iso":"eng"}],"year":"2005","citation":{"short":"K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.","ieee":"K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), 2005.","ama":"Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787","apa":"Danne, K., & Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press. https://doi.org/10.1109/fpl.2005.1515787","chicago":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press, 2005. https://doi.org/10.1109/fpl.2005.1515787.","mla":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787.","bibtex":"@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }"},"type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13623","doi":"10.1109/fpl.2005.1515787"},{"citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.","apa":"Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.","chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004.","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }"},"type":"conference","year":"2004","page":"63-69","date_updated":"2022-01-06T06:56:08Z","_id":"2415","publisher":"CSREA Press","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"keyword":["hardware virtualization"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2018-04-17T14:45:57Z","abstract":[{"lang":"eng","text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. "}],"title":"Virtualization of Hardware – Introduction and Survey","user_id":"24135"},{"_id":"10742","date_updated":"2022-01-06T06:50:50Z","intvolume":" 53","doi":"10.1109/tc.2004.99","issue":"11","type":"journal_article","citation":{"apa":"Steiger, C., Walder, H., & Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers, 53(11), 1393–1407. https://doi.org/10.1109/tc.2004.99","ama":"Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers 53, no. 11 (2004): 1393–1407. https://doi.org/10.1109/tc.2004.99.","bibtex":"@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }","mla":"Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.","short":"C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers 53 (2004) 1393–1407.","ieee":"C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” {IEEE} Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004."},"year":"2004","page":"1393-1407","language":[{"iso":"eng"}],"title":"Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks","user_id":"3118","author":[{"first_name":"Christoph","full_name":"Steiger, Christoph","last_name":"Steiger"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"{IEEE} Transactions on Computers","volume":53,"status":"public","date_created":"2019-07-10T12:00:43Z"},{"publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540229896","9783540301172"]},"publication_status":"published","date_created":"2019-10-04T21:28:56Z","status":"public","publication":"Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"title":"A Runtime Environment for Reconfigurable Hardware Operating Systems","user_id":"398","extern":"1","place":"Berlin, Heidelberg","page":"831-835","year":"2004","type":"conference","citation":{"ieee":"H. Walder and M. Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835.","short":"H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.","mla":"Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84.","bibtex":"@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }","apa":"Walder, H., & Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-30117-2_84","ama":"Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84","chicago":"Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 831–35. Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84."},"language":[{"iso":"eng"}],"doi":"10.1007/978-3-540-30117-2_84","date_updated":"2022-01-06T06:51:40Z","_id":"13618"},{"language":[{"iso":"eng"}],"type":"conference","year":"2004","citation":{"ieee":"H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.","short":"H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","bibtex":"@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }","mla":"Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","chicago":"Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.","apa":"Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","ama":"Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004."},"_id":"13619","date_updated":"2022-01-06T06:51:40Z","publisher":"CSREA Press","author":[{"first_name":"Hebert","full_name":"Walder, Hebert","last_name":"Walder"},{"last_name":"Nobs","first_name":"Samuel","full_name":"Nobs, Samuel"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T21:31:54Z","extern":"1","user_id":"398","title":"XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems"},{"title":"Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine","user_id":"398","publication":"Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"78"}],"author":[{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"publisher":"IEEE CS Press","publication_identifier":{"isbn":["0769522300"]},"publication_status":"published","date_created":"2019-10-04T21:32:57Z","status":"public","date_updated":"2022-01-06T06:51:40Z","_id":"13620","doi":"10.1109/fccm.2004.31","citation":{"mla":"Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31.","bibtex":"@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }","chicago":"Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31.","ama":"Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31","apa":"Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31","ieee":"M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.","short":"M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004."},"year":"2004","type":"conference","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:56:09Z","_id":"2418","doi":"10.1109/FPT.2003.1275755","page":"252-259","type":"conference","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755","apa":"Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259."},"year":"2003","abstract":[{"text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ","lang":"eng"}],"user_id":"24135","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","publisher":"IEEE Computer Society","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-04-17T15:03:34Z","status":"public"},{"department":[{"_id":"518"},{"_id":"78"}],"title":"The Case for Reconfigurable Hardware in Wearable Computing","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:56:09Z","doi":"10.1007/s00779-003-0243-x","publication":"Personal and Ubiquitous Computing","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"first_name":"Jan","full_name":"Beutel, Jan","last_name":"Beutel"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"full_name":"Tröster, Gerhard","first_name":"Gerhard","last_name":"Tröster"}],"publisher":"Springer","date_created":"2018-04-17T15:04:47Z","status":"public","volume":7,"abstract":[{"text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.","lang":"eng"}],"extern":"1","user_id":"398","page":"299-308","year":"2003","citation":{"bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x","ieee":"C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308."},"type":"journal_article","_id":"2419","intvolume":" 7","issue":"5"},{"date_created":"2018-04-17T15:10:00Z","status":"public","volume":26,"keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"publication":"Journal of Supercomputing","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Kluwer Academic Publishers","user_id":"398","abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"extern":"1","page":"109-129","type":"journal_article","year":"2003","citation":{"apa":"Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.","short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003."},"issue":"2","intvolume":" 26","_id":"2420","publication_identifier":{"issn":["0920-8542"]},"department":[{"_id":"518"},{"_id":"78"}],"title":"Instance-Specific Accelerators for Minimum Covering","language":[{"iso":"eng"}],"doi":"10.1023/a:1024443416592","date_updated":"2022-01-06T06:56:10Z"},{"date_updated":"2022-01-06T06:56:13Z","_id":"2421","intvolume":" 2778","doi":"10.1007/b12007","series_title":"Lecture Notes in Computer Science (LNCS)","page":"151-160","type":"conference","year":"2003","citation":{"mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160."},"abstract":[{"text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.","lang":"eng"}],"title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","user_id":"24135","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","multi-context","FPGA"],"publisher":"Springer","author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"volume":2778,"date_created":"2018-04-17T15:11:25Z","status":"public"},{"date_updated":"2022-01-06T06:56:13Z","_id":"2422","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80.","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003."},"type":"conference","year":"2003","page":"174-180","abstract":[{"lang":"eng","text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs."}],"user_id":"24135","title":"Co-simulation of a Hybrid Multi-Context Architecture","publisher":"CSREA Press","author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","co-simulation"],"status":"public","date_created":"2018-04-17T15:12:56Z","publication_identifier":{"isbn":["1-932415-05-X"]}},{"date_updated":"2022-01-06T06:51:40Z","_id":"13612","doi":"10.1109/date.2003.1253622","citation":{"mla":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }","apa":"Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622","ama":"Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622","chicago":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622.","ieee":"H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295.","short":"H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295."},"year":"2003","type":"conference","page":"290-295","language":[{"iso":"eng"}],"extern":"1","title":"Online scheduling for block-partitioned reconfigurable devices","user_id":"398","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE CS Press","department":[{"_id":"78"}],"publication":"Proceedings Design, Automation and Test in Europe Conference (DATE)","publication_status":"published","publication_identifier":{"isbn":["0769518702"]},"status":"public","date_created":"2019-10-04T21:15:31Z"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13613","doi":"10.1109/ipdps.2003.1213329","citation":{"ieee":"H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.","short":"H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.","mla":"Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.","bibtex":"@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }","apa":"Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329","ama":"Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329","chicago":"Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329."},"year":"2003","type":"conference","language":[{"iso":"eng"}],"extern":"1","title":"Fast online task placement on FPGAs: free space partitioning and 2D-hashing","user_id":"398","publisher":"IEEE CS Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"last_name":"Steiger","first_name":"Christoph","full_name":"Steiger, Christoph"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings International Parallel and Distributed Processing Symposium","publication_identifier":{"isbn":["0769519261"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:17:07Z"},{"date_created":"2019-10-04T21:20:30Z","status":"public","publication":"Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"publisher":"CSREA Press","author":[{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"398","title":"Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations","extern":"1","language":[{"iso":"eng"}],"page":"284-287","citation":{"ieee":"H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.","short":"H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.","mla":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }","chicago":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.","apa":"Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.","ama":"Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287."},"year":"2003","type":"conference","date_updated":"2022-01-06T06:51:40Z","_id":"13614"},{"doi":"10.1007/978-3-540-45234-8_56","_id":"13615","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"page":"575-584","citation":{"apa":"Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56","ama":"Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.","mla":"Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56.","bibtex":"@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }","short":"C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.","ieee":"C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584."},"type":"conference","year":"2003","user_id":"398","title":"Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices","place":"Berlin, Heidelberg","extern":"1","date_created":"2019-10-04T21:20:41Z","status":"public","publication_status":"published","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540408222","9783540452348"]},"publication":"Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"last_name":"Steiger","first_name":"Christoph","full_name":"Steiger, Christoph"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"Springer"},{"doi":"10.1109/real.2003.1253269","_id":"13617","date_updated":"2022-01-06T06:51:40Z","page":"252-235","citation":{"mla":"Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269.","bibtex":"@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }","chicago":"Steiger, Christoph, Herbert Walder, Marco Platzner, and Lothar Thiele. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 252–235. IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269.","apa":"Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press. https://doi.org/10.1109/real.2003.1253269","ama":"Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269","ieee":"C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235.","short":"C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235."},"year":"2003","type":"conference","language":[{"iso":"eng"}],"title":"Online scheduling and placement of real-time tasks to partially reconfigurable devices","user_id":"398","publication_status":"published","publication_identifier":{"isbn":["0769520448"]},"date_created":"2019-10-04T21:22:53Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)","author":[{"last_name":"Steiger","first_name":"Christoph","full_name":"Steiger, Christoph"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE CS Press"},{"publication_identifier":{"isbn":["0-7695-1816-8"]},"status":"public","date_created":"2018-04-17T15:13:50Z","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"publisher":"IEEE Computer Society","publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["wearable computing"],"title":"Reconfigurable Hardware in Wearable Computing Nodes","user_id":"24135","abstract":[{"text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.","lang":"eng"}],"year":"2002","citation":{"ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250.","ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250"},"type":"conference","page":"215-222","doi":"10.1109/ISWC.2002.1167250","date_updated":"2022-01-06T06:56:13Z","_id":"2423"},{"abstract":[{"text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ","lang":"eng"}],"user_id":"24135","title":"Partially Reconfigurable Cores for Xilinx Virtex","publisher":"Springer","author":[{"first_name":"Matthias","full_name":"Dyer, Matthias","last_name":"Dyer"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["partial reconfiguration"],"status":"public","date_created":"2018-04-17T15:14:39Z","volume":2438,"_id":"2424","intvolume":" 2438","date_updated":"2022-01-06T06:56:13Z","doi":"10.1007/3-540-46117-5","series_title":"Lecture Notes in Computer Science (LNCS)","year":"2002","citation":{"short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5","apa":"Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5.","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }"},"type":"conference","page":"292-301"},{"page":"163-172","type":"conference","year":"2002","citation":{"ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671","apa":"Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671"},"_id":"2425","date_updated":"2022-01-06T06:56:13Z","doi":"10.1109/FPGA.2002.1106671","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2018-04-17T15:15:44Z","status":"public","abstract":[{"lang":"eng","text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. "}],"user_id":"24135","title":"Custom Computing Machines for the Set Covering Problem"},{"language":[{"iso":"eng"}],"year":"2002","citation":{"bibtex":"@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }","mla":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.","apa":"Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946","ama":"Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946","chicago":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.","ieee":"M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.","short":"M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159."},"type":"journal_article","page":"145-159","issue":"2","doi":"10.1023/a:1013627403946","_id":"10651","intvolume":" 21","date_updated":"2022-01-06T06:50:49Z","status":"public","date_created":"2019-07-10T11:13:11Z","volume":21,"author":[{"full_name":"Eisenring, Michael","first_name":"Michael","last_name":"Eisenring"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Kluwer Academic Publishers","department":[{"_id":"78"}],"publication":"The Journal of Supercomputing","user_id":"398","title":"A Framework for Run-time Reconfigurable Systems","extern":"1"},{"page":"24-30","year":"2002","citation":{"ieee":"H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.","short":"H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","mla":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","bibtex":"@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }","chicago":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 24–30. CSREA Press, 2002.","ama":"Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.","apa":"Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","_id":"13611","date_created":"2019-10-04T21:13:46Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publisher":"CSREA Press","author":[{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform","user_id":"398","extern":"1"},{"date_updated":"2022-01-06T06:56:17Z","_id":"2428","page":"85-91","type":"conference","citation":{"ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.","apa":"Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001."},"year":"2001","abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}],"title":"Instance-Specific Accelerators for Minimum Covering","user_id":"24135","department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","keyword":["minimum covering","accelerator","funding-sundance"],"publisher":"CSREA Press","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-04-17T15:39:17Z","status":"public"},{"user_id":"24135","title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","abstract":[{"text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.","lang":"eng"}],"date_created":"2018-04-17T15:51:39Z","status":"public","volume":4525,"keyword":["benchmark"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"},{"first_name":"Gerhard","full_name":"Tröster, Gerhard","last_name":"Tröster"}],"doi":"10.1117/12.434376","date_updated":"2022-01-06T06:56:17Z","_id":"2432","intvolume":" 4525","page":"135-146","year":"2001","type":"conference","citation":{"short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.","bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={10.1117/12.434376}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376."},"series_title":"Proc. SPIE"},{"date_created":"2019-07-10T11:47:42Z","status":"public","volume":9,"publication":"{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems","department":[{"_id":"78"}],"author":[{"first_name":"Oskar","full_name":"Mencer, Oskar","last_name":"Mencer"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Morf, Martin","first_name":"Martin","last_name":"Morf"},{"last_name":"J. Flynn","full_name":"J. Flynn, Michael","first_name":"Michael"}],"user_id":"398","title":"Object-oriented domain specific compilers for programming FPGAs","extern":"1","language":[{"iso":"eng"}],"page":"205-210","year":"2001","citation":{"ama":"Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835","apa":"Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835","chicago":"Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9, no. 1 (2001): 205–10. https://doi.org/10.1109/92.920835.","bibtex":"@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }","mla":"Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.","short":"O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.","ieee":"O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, pp. 205–210, 2001."},"type":"journal_article","issue":"1","doi":"10.1109/92.920835","date_updated":"2022-01-06T06:50:50Z","_id":"10713","intvolume":" 9"},{"_id":"13463","date_updated":"2022-01-06T06:51:36Z","citation":{"short":"R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ieee":"R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ama":"Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.","apa":"Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).","chicago":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","mla":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","bibtex":"@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }"},"type":"misc","year":"2001","language":[{"iso":"eng"}],"title":"Dynamically Reconfigurable Processors","user_id":"398","extern":"1","status":"public","date_created":"2019-09-30T09:27:00Z","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)","department":[{"_id":"78"}]},{"year":"2000","type":"journal_article","citation":{"ama":"Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322","apa":"Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322","chicago":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.","mla":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.","bibtex":"@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={10.1109/2.839322}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }","short":"M. Platzner, Computer 33 (2000) 58–60.","ieee":"M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000."},"page":"58-60","issue":"4","_id":"6507","intvolume":" 33","status":"public","date_created":"2019-01-08T09:45:03Z","volume":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Computer","user_id":"398","extern":"1","language":[{"iso":"eng"}],"doi":"10.1109/2.839322","date_updated":"2022-01-06T07:03:08Z","publication_status":"published","publication_identifier":{"issn":["0018-9162"]},"department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"title":"Reconfigurable accelerators for combinatorial problems"},{"title":"Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems","user_id":"398","extern":"1","volume":147,"date_created":"2019-07-10T09:22:58Z","status":"public","publication":"IEE Proceedings -- Computers & Digital Techniques","department":[{"_id":"78"}],"publisher":"IET","author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"doi":"10.1049/ip-cdt:20000496","_id":"10606","date_updated":"2022-01-06T06:50:47Z","intvolume":" 147","page":"159-165","year":"2000","citation":{"mla":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.","bibtex":"@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496}, journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }","ama":"Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496","apa":"Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496","chicago":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.","ieee":"M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital Techniques, vol. 147, pp. 159–165, 2000.","short":"M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques 147 (2000) 159–165."},"type":"journal_article","language":[{"iso":"eng"}]}]