[{"publisher":"Elsevier","author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Microprocessors and Microsystems","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"status":"public","date_created":"2018-04-17T14:36:10Z","volume":29,"abstract":[{"lang":"eng","text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"user_id":"24135","title":"System-level performance evaluation of reconfigurable processors","year":"2005","citation":{"ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004","apa":"Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005."},"type":"journal_article","page":"63-73","_id":"2412","date_updated":"2022-01-06T06:56:07Z","intvolume":" 29","issue":"2-3","doi":"10.1016/j.micpro.2004.06.004"},{"language":[{"iso":"eng"}],"citation":{"apa":"Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720","ama":"Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720","chicago":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. https://doi.org/10.1109/wises.2005.1438720.","bibtex":"@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={10.1109/wises.2005.1438720}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","mla":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005, doi:10.1109/wises.2005.1438720.","short":"K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","ieee":"K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005."},"year":"2005","type":"conference","doi":"10.1109/wises.2005.1438720","date_updated":"2022-01-06T06:51:40Z","_id":"13621","status":"public","date_created":"2019-10-04T21:38:53Z","publication_status":"published","publication_identifier":{"isbn":["3902463031"]},"author":[{"full_name":"Danne, Klaus","first_name":"Klaus","last_name":"Danne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)","department":[{"_id":"78"}],"user_id":"398","title":"Periodic real-time scheduling for FPGA computers"},{"language":[{"iso":"eng"}],"citation":{"short":"K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","ieee":"K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005.","apa":"Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS).","ama":"Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.","chicago":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","mla":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","bibtex":"@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }"},"type":"conference","year":"2005","_id":"13622","date_updated":"2022-01-06T06:51:40Z","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)","department":[{"_id":"78"}],"status":"public","date_created":"2019-10-04T21:42:02Z","user_id":"398","title":"Memory-demanding Periodic Real-time Applications on FPGA Computers"},{"_id":"13623","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/fpl.2005.1515787","type":"conference","year":"2005","citation":{"ieee":"K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), 2005.","short":"K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.","bibtex":"@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","mla":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787.","apa":"Danne, K., & Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press. https://doi.org/10.1109/fpl.2005.1515787","ama":"Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787","chicago":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press, 2005. https://doi.org/10.1109/fpl.2005.1515787."},"language":[{"iso":"eng"}],"title":"A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware","user_id":"398","publication":"Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE CS Press","publication_identifier":{"isbn":["0780393627"]},"publication_status":"published","date_created":"2019-10-04T21:42:46Z","status":"public"},{"citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69.","chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004.","apa":"Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69."},"year":"2004","type":"conference","page":"63-69","_id":"2415","date_updated":"2022-01-06T06:56:08Z","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","department":[{"_id":"518"},{"_id":"78"}],"keyword":["hardware virtualization"],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2018-04-17T14:45:57Z","abstract":[{"text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ","lang":"eng"}],"title":"Virtualization of Hardware – Introduction and Survey","user_id":"24135"},{"user_id":"3118","title":"Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks","publication":"{IEEE} Transactions on Computers","department":[{"_id":"78"}],"author":[{"full_name":"Steiger, Christoph","first_name":"Christoph","last_name":"Steiger"},{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-07-10T12:00:43Z","status":"public","volume":53,"_id":"10742","intvolume":" 53","date_updated":"2022-01-06T06:50:50Z","issue":"11","doi":"10.1109/tc.2004.99","language":[{"iso":"eng"}],"page":"1393-1407","year":"2004","citation":{"mla":"Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.","bibtex":"@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers 53, no. 11 (2004): 1393–1407. https://doi.org/10.1109/tc.2004.99.","ama":"Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99","apa":"Steiger, C., Walder, H., & Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers, 53(11), 1393–1407. https://doi.org/10.1109/tc.2004.99","ieee":"C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” {IEEE} Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.","short":"C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers 53 (2004) 1393–1407."},"type":"journal_article"},{"publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540229896","9783540301172"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:28:56Z","author":[{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer","publication":"Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"title":"A Runtime Environment for Reconfigurable Hardware Operating Systems","user_id":"398","extern":"1","place":"Berlin, Heidelberg","year":"2004","type":"conference","citation":{"chicago":"Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 831–35. Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84.","ama":"Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84","apa":"Walder, H., & Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-30117-2_84","mla":"Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84.","bibtex":"@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }","short":"H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.","ieee":"H. Walder and M. Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835."},"page":"831-835","language":[{"iso":"eng"}],"doi":"10.1007/978-3-540-30117-2_84","date_updated":"2022-01-06T06:51:40Z","_id":"13618"},{"language":[{"iso":"eng"}],"citation":{"apa":"Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","ama":"Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.","chicago":"Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.","bibtex":"@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }","mla":"Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","short":"H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.","ieee":"H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004."},"year":"2004","type":"conference","_id":"13619","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T21:31:54Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publisher":"CSREA Press","author":[{"last_name":"Walder","first_name":"Hebert","full_name":"Walder, Hebert"},{"first_name":"Samuel","full_name":"Nobs, Samuel","last_name":"Nobs"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"398","title":"XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems","extern":"1"},{"year":"2004","type":"conference","citation":{"short":"M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.","ieee":"M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.","chicago":"Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31.","apa":"Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31","ama":"Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31","bibtex":"@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }","mla":"Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31."},"language":[{"iso":"eng"}],"doi":"10.1109/fccm.2004.31","_id":"13620","date_updated":"2022-01-06T06:51:40Z","publication_identifier":{"isbn":["0769522300"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:32:57Z","publisher":"IEEE CS Press","author":[{"full_name":"Dyer, Matthias","first_name":"Matthias","last_name":"Dyer"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"publication":"Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"78"}],"title":"Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine","user_id":"398"},{"publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","status":"public","date_created":"2018-04-17T15:03:34Z","abstract":[{"lang":"eng","text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. "}],"user_id":"24135","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","type":"conference","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259.","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755","apa":"Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755","chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }"},"year":"2003","page":"252-259","date_updated":"2022-01-06T06:56:09Z","_id":"2418","doi":"10.1109/FPT.2003.1275755"},{"title":"The Case for Reconfigurable Hardware in Wearable Computing","department":[{"_id":"518"},{"_id":"78"}],"date_updated":"2022-01-06T06:56:09Z","doi":"10.1007/s00779-003-0243-x","language":[{"iso":"eng"}],"extern":"1","abstract":[{"text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.","lang":"eng"}],"user_id":"398","author":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"first_name":"Jan","full_name":"Beutel, Jan","last_name":"Beutel"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"last_name":"Tröster","first_name":"Gerhard","full_name":"Tröster, Gerhard"}],"publisher":"Springer","publication":"Personal and Ubiquitous Computing","volume":7,"status":"public","date_created":"2018-04-17T15:04:47Z","intvolume":" 7","_id":"2419","issue":"5","type":"journal_article","citation":{"ieee":"C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.","bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x"},"year":"2003","page":"299-308"},{"year":"2003","citation":{"short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.","apa":"Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592."},"type":"journal_article","page":"109-129","issue":"2","intvolume":" 26","_id":"2420","volume":26,"status":"public","date_created":"2018-04-17T15:10:00Z","publisher":"Kluwer Academic Publishers","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"publication":"Journal of Supercomputing","user_id":"398","extern":"1","abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1023/a:1024443416592","date_updated":"2022-01-06T06:56:10Z","publication_identifier":{"issn":["0920-8542"]},"department":[{"_id":"518"},{"_id":"78"}],"title":"Instance-Specific Accelerators for Minimum Covering"},{"doi":"10.1007/b12007","_id":"2421","intvolume":" 2778","date_updated":"2022-01-06T06:56:13Z","page":"151-160","year":"2003","type":"conference","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007."},"series_title":"Lecture Notes in Computer Science (LNCS)","user_id":"24135","title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","abstract":[{"lang":"eng","text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load."}],"date_created":"2018-04-17T15:11:25Z","status":"public","volume":2778,"department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","multi-context","FPGA"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","publisher":"Springer","author":[{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180."},"year":"2003","type":"conference","page":"174-180","_id":"2422","date_updated":"2022-01-06T06:56:13Z","author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","keyword":["Zippy","co-simulation"],"department":[{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["1-932415-05-X"]},"status":"public","date_created":"2018-04-17T15:12:56Z","abstract":[{"text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.","lang":"eng"}],"title":"Co-simulation of a Hybrid Multi-Context Architecture","user_id":"24135"},{"title":"Online scheduling for block-partitioned reconfigurable devices","user_id":"398","extern":"1","publication_identifier":{"isbn":["0769518702"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:15:31Z","publisher":"IEEE CS Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proceedings Design, Automation and Test in Europe Conference (DATE)","department":[{"_id":"78"}],"doi":"10.1109/date.2003.1253622","date_updated":"2022-01-06T06:51:40Z","_id":"13612","year":"2003","type":"conference","citation":{"short":"H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295.","ieee":"H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295.","chicago":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622.","ama":"Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622","apa":"Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622","mla":"Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }"},"page":"290-295","language":[{"iso":"eng"}]},{"department":[{"_id":"78"}],"publication":"Proceedings International Parallel and Distributed Processing Symposium","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Steiger, Christoph","first_name":"Christoph","last_name":"Steiger"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE CS Press","publication_status":"published","publication_identifier":{"isbn":["0769519261"]},"date_created":"2019-10-04T21:17:07Z","status":"public","extern":"1","title":"Fast online task placement on FPGAs: free space partitioning and 2D-hashing","user_id":"398","citation":{"short":"H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.","ieee":"H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.","chicago":"Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329.","apa":"Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329","ama":"Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329","bibtex":"@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }","mla":"Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329."},"type":"conference","year":"2003","language":[{"iso":"eng"}],"_id":"13613","date_updated":"2022-01-06T06:51:40Z","doi":"10.1109/ipdps.2003.1213329"},{"date_updated":"2022-01-06T06:51:40Z","_id":"13614","type":"conference","year":"2003","citation":{"apa":"Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.","ama":"Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.","chicago":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }","mla":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.","short":"H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.","ieee":"H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287."},"page":"284-287","language":[{"iso":"eng"}],"extern":"1","title":"Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations","user_id":"398","publisher":"CSREA Press","author":[{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2019-10-04T21:20:30Z"},{"date_created":"2019-10-04T21:20:41Z","status":"public","publication_status":"published","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540408222","9783540452348"]},"publication":"Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"first_name":"Christoph","full_name":"Steiger, Christoph","last_name":"Steiger"},{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"398","title":"Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices","place":"Berlin, Heidelberg","extern":"1","language":[{"iso":"eng"}],"page":"575-584","year":"2003","type":"conference","citation":{"mla":"Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56.","bibtex":"@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }","apa":"Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56","ama":"Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.","ieee":"C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584.","short":"C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584."},"doi":"10.1007/978-3-540-45234-8_56","date_updated":"2022-01-06T06:51:40Z","_id":"13615"},{"citation":{"short":"C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.","ieee":"C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235.","chicago":"Steiger, Christoph, Herbert Walder, Marco Platzner, and Lothar Thiele. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 252–235. IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269.","apa":"Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press. https://doi.org/10.1109/real.2003.1253269","ama":"Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269","mla":"Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269.","bibtex":"@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }"},"year":"2003","type":"conference","page":"252-235","language":[{"iso":"eng"}],"doi":"10.1109/real.2003.1253269","date_updated":"2022-01-06T06:51:40Z","_id":"13617","publication_identifier":{"isbn":["0769520448"]},"publication_status":"published","status":"public","date_created":"2019-10-04T21:22:53Z","publisher":"IEEE CS Press","author":[{"last_name":"Steiger","full_name":"Steiger, Christoph","first_name":"Christoph"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"department":[{"_id":"78"}],"publication":"Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)","title":"Online scheduling and placement of real-time tasks to partially reconfigurable devices","user_id":"398"},{"page":"215-222","type":"conference","citation":{"ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250.","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222."},"year":"2002","doi":"10.1109/ISWC.2002.1167250","date_updated":"2022-01-06T06:56:13Z","_id":"2423","date_created":"2018-04-17T15:13:50Z","status":"public","publication_identifier":{"isbn":["0-7695-1816-8"]},"keyword":["wearable computing"],"publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","department":[{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"user_id":"24135","title":"Reconfigurable Hardware in Wearable Computing Nodes","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM."}]},{"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["partial reconfiguration"],"publisher":"Springer","author":[{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"volume":2438,"date_created":"2018-04-17T15:14:39Z","status":"public","abstract":[{"text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ","lang":"eng"}],"title":"Partially Reconfigurable Cores for Xilinx Virtex","user_id":"24135","series_title":"Lecture Notes in Computer Science (LNCS)","page":"292-301","citation":{"short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5","apa":"Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }"},"year":"2002","type":"conference","intvolume":" 2438","_id":"2424","date_updated":"2022-01-06T06:56:13Z","doi":"10.1007/3-540-46117-5"},{"page":"163-172","type":"conference","year":"2002","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.","apa":"Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172."},"doi":"10.1109/FPGA.2002.1106671","_id":"2425","date_updated":"2022-01-06T06:56:13Z","date_created":"2018-04-17T15:15:44Z","status":"public","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society","title":"Custom Computing Machines for the Set Covering Problem","user_id":"24135","abstract":[{"lang":"eng","text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. "}]},{"extern":"1","title":"A Framework for Run-time Reconfigurable Systems","user_id":"398","publisher":"Kluwer Academic Publishers","author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"78"}],"publication":"The Journal of Supercomputing","volume":21,"status":"public","date_created":"2019-07-10T11:13:11Z","intvolume":" 21","_id":"10651","date_updated":"2022-01-06T06:50:49Z","doi":"10.1023/a:1013627403946","issue":"2","type":"journal_article","year":"2002","citation":{"bibtex":"@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }","mla":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.","ama":"Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946","apa":"Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946","chicago":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.","ieee":"M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.","short":"M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159."},"page":"145-159","language":[{"iso":"eng"}]},{"page":"24-30","type":"conference","year":"2002","citation":{"bibtex":"@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }","mla":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","chicago":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 24–30. CSREA Press, 2002.","ama":"Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.","apa":"Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.","ieee":"H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.","short":"H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30."},"language":[{"iso":"eng"}],"_id":"13611","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T21:13:46Z","status":"public","publication":"Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"78"}],"publisher":"CSREA Press","author":[{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform","user_id":"398","extern":"1"},{"citation":{"bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001.","apa":"Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91."},"type":"conference","year":"2001","page":"85-91","_id":"2428","date_updated":"2022-01-06T06:56:17Z","status":"public","date_created":"2018-04-17T15:39:17Z","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","keyword":["minimum covering","accelerator","funding-sundance"],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"user_id":"24135","title":"Instance-Specific Accelerators for Minimum Covering","abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}]},{"volume":4525,"date_created":"2018-04-17T15:51:39Z","status":"public","department":[{"_id":"518"},{"_id":"78"}],"publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","keyword":["benchmark"],"author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"first_name":"Gerhard","full_name":"Tröster, Gerhard","last_name":"Tröster"}],"title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","user_id":"24135","abstract":[{"text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.","lang":"eng"}],"page":"135-146","citation":{"ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.","short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={10.1117/12.434376}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376."},"year":"2001","type":"conference","series_title":"Proc. SPIE","doi":"10.1117/12.434376","_id":"2432","date_updated":"2022-01-06T06:56:17Z","intvolume":" 4525"},{"year":"2001","citation":{"chicago":"Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9, no. 1 (2001): 205–10. https://doi.org/10.1109/92.920835.","ama":"Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835","apa":"Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835","bibtex":"@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }","mla":"Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.","short":"O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.","ieee":"O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, pp. 205–210, 2001."},"type":"journal_article","page":"205-210","language":[{"iso":"eng"}],"doi":"10.1109/92.920835","issue":"1","intvolume":" 9","_id":"10713","date_updated":"2022-01-06T06:50:50Z","volume":9,"status":"public","date_created":"2019-07-10T11:47:42Z","author":[{"full_name":"Mencer, Oskar","first_name":"Oskar","last_name":"Mencer"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Morf","full_name":"Morf, Martin","first_name":"Martin"},{"first_name":"Michael","full_name":"J. Flynn, Michael","last_name":"J. Flynn"}],"publication":"{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems","department":[{"_id":"78"}],"title":"Object-oriented domain specific compilers for programming FPGAs","user_id":"398","extern":"1"},{"extern":"1","user_id":"398","title":"Dynamically Reconfigurable Processors","department":[{"_id":"78"}],"author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)","date_created":"2019-09-30T09:27:00Z","status":"public","date_updated":"2022-01-06T06:51:36Z","_id":"13463","language":[{"iso":"eng"}],"type":"misc","citation":{"bibtex":"@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }","mla":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ama":"Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.","apa":"Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).","chicago":"Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ieee":"R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","short":"R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001."},"year":"2001"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:03:08Z","doi":"10.1109/2.839322","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"publication_status":"published","publication_identifier":{"issn":["0018-9162"]},"title":"Reconfigurable accelerators for combinatorial problems","page":"58-60","citation":{"ieee":"M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000.","short":"M. Platzner, Computer 33 (2000) 58–60.","bibtex":"@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={10.1109/2.839322}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }","mla":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.","chicago":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.","apa":"Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322","ama":"Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322"},"type":"journal_article","year":"2000","_id":"6507","intvolume":" 33","issue":"4","publication":"Computer","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-01-08T09:45:03Z","status":"public","volume":33,"extern":"1","user_id":"398"},{"extern":"1","title":"Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems","user_id":"398","publisher":"IET","author":[{"last_name":"Eisenring","first_name":"Michael","full_name":"Eisenring, Michael"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"IEE Proceedings -- Computers & Digital Techniques","volume":147,"status":"public","date_created":"2019-07-10T09:22:58Z","date_updated":"2022-01-06T06:50:47Z","_id":"10606","intvolume":" 147","doi":"10.1049/ip-cdt:20000496","citation":{"ama":"Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496","apa":"Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496","chicago":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.","bibtex":"@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496}, journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }","mla":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.","short":"M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques 147 (2000) 159–165.","ieee":"M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital Techniques, vol. 147, pp. 159–165, 2000."},"type":"journal_article","year":"2000","page":"159-165","language":[{"iso":"eng"}]},{"extern":"1","user_id":"398","title":"Toward embedded qualitative simulation: a specialized computer architecture for QSim","publication":"IEEE Intelligent Systems","department":[{"_id":"78"}],"author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Bernhard","full_name":"Rinner, Bernhard","last_name":"Rinner"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"publisher":"Institute of Electrical {\\&} Electronics Engineers ({IEEE})","date_created":"2019-07-10T11:54:17Z","status":"public","volume":15,"intvolume":" 15","_id":"10725","date_updated":"2022-01-06T06:50:50Z","issue":"2","doi":"10.1109/5254.850829","language":[{"iso":"eng"}],"page":"62-68","citation":{"bibtex":"@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative simulation: a specialized computer architecture for QSim}, volume={15}, DOI={10.1109/5254.850829}, number={2}, journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\\&} Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={2000}, pages={62–68} }","mla":"Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” IEEE Intelligent Systems, vol. 15, no. 2, Institute of Electrical {\\&} Electronics Engineers ({IEEE}), 2000, pp. 62–68, doi:10.1109/5254.850829.","ama":"Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68. doi:10.1109/5254.850829","apa":"Platzner, M., Rinner, B., & Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems, 15(2), 62–68. https://doi.org/10.1109/5254.850829","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” IEEE Intelligent Systems 15, no. 2 (2000): 62–68. https://doi.org/10.1109/5254.850829.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.","short":"M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68."},"type":"journal_article","year":"2000"},{"title":"An Implementation Framework for Run-time Reconfigurable Systems","user_id":"398","extern":"1","date_created":"2019-10-04T21:05:39Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)","author":[{"last_name":"Eisenring","full_name":"Eisenring, Michael H.","first_name":"Michael H."},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","date_updated":"2022-01-06T06:51:40Z","_id":"13609","page":"151-157","citation":{"short":"M.H. Eisenring, M. Platzner, in: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–157.","ieee":"M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time Reconfigurable Systems,” in Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 2000, pp. 151–157.","chicago":"Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 151–57. CSREA Press, 2000.","ama":"Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.","apa":"Eisenring, M. H., & Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.","mla":"Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–57.","bibtex":"@inproceedings{Eisenring_Platzner_2000, title={An Implementation Framework for Run-time Reconfigurable Systems}, booktitle={Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)}, publisher={CSREA Press}, author={Eisenring, Michael H. and Platzner, Marco}, year={2000}, pages={151–157} }"},"year":"2000","type":"conference","language":[{"iso":"eng"}]},{"status":"public","date_created":"2019-10-04T21:09:09Z","author":[{"last_name":"Eisenring","first_name":"Michael","full_name":"Eisenring, Michael"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer","department":[{"_id":"78"}],"publication":"Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)","title":"Optimization of Run-time Reconfigurable Embedded Systems","user_id":"398","extern":"1","year":"2000","type":"conference","citation":{"mla":"Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–74.","bibtex":"@inproceedings{Eisenring_Platzner_2000, title={Optimization of Run-time Reconfigurable Embedded Systems}, booktitle={Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={565–574} }","chicago":"Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 565–74. Springer, 2000.","apa":"Eisenring, M., & Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.","ama":"Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL). Springer; 2000:565-574.","ieee":"M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded Systems,” in Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 2000, pp. 565–574.","short":"M. Eisenring, M. Platzner, in: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–574."},"page":"565-574","language":[{"iso":"eng"}],"_id":"13610","date_updated":"2022-01-06T06:51:40Z"},{"doi":"10.1109/hicss.1999.772883","_id":"13607","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"1999","citation":{"chicago":"Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press, 1999. https://doi.org/10.1109/hicss.1999.772883.","apa":"Mencer, O., & Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press. https://doi.org/10.1109/hicss.1999.772883","ama":"Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press; 1999. doi:10.1109/hicss.1999.772883","mla":"Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999, doi:10.1109/hicss.1999.772883.","bibtex":"@inproceedings{Mencer_Platzner_1999, title={Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment}, DOI={10.1109/hicss.1999.772883}, booktitle={Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)}, publisher={IEEE CS Press}, author={Mencer, Oskar and Platzner, Marco}, year={1999} }","short":"O. Mencer, M. Platzner, in: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999.","ieee":"O. Mencer and M. Platzner, “Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment,” in Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), 1999."},"type":"conference","user_id":"398","title":"Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment","extern":"1","status":"public","date_created":"2019-10-04T20:59:20Z","publication_status":"published","publication_identifier":{"isbn":["0769500013"]},"author":[{"full_name":"Mencer, Oskar","first_name":"Oskar","last_name":"Mencer"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE CS Press","publication":"Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)","department":[{"_id":"78"}]},{"page":"205-214","type":"conference","citation":{"bibtex":"@inproceedings{Eisenring_Platzner_Thiele_1999, series={LCS}, title={Communication Synthesis for Reconfigurable Embedded Systems}, volume={1673}, DOI={10.1007/978-3-540-48302-1_21}, booktitle={Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco and Thiele, Lothar}, year={1999}, pages={205–214}, collection={LCS} }","mla":"Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded Systems.” Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), vol. 1673, Springer, 1999, pp. 205–14, doi:10.1007/978-3-540-48302-1_21.","apa":"Eisenring, M., Platzner, M., & Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer. https://doi.org/10.1007/978-3-540-48302-1_21","ama":"Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214. doi:10.1007/978-3-540-48302-1_21","chicago":"Eisenring, Michael, Marco Platzner, and Lothar Thiele. “Communication Synthesis for Reconfigurable Embedded Systems.” In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), 1673:205–14. LCS. Springer, 1999. https://doi.org/10.1007/978-3-540-48302-1_21.","ieee":"M. Eisenring, M. Platzner, and L. Thiele, “Communication Synthesis for Reconfigurable Embedded Systems,” in Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), 1999, vol. 1673, pp. 205–214.","short":"M. Eisenring, M. Platzner, L. Thiele, in: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 1999, pp. 205–214."},"year":"1999","_id":"13608","intvolume":" 1673","volume":1673,"date_created":"2019-10-04T21:01:05Z","status":"public","publication":"Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)","author":[{"first_name":"Michael","full_name":"Eisenring, Michael","last_name":"Eisenring"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"publisher":"Springer","user_id":"398","extern":"1","language":[{"iso":"eng"}],"series_title":"LCS","doi":"10.1007/978-3-540-48302-1_21","date_updated":"2022-01-06T06:51:40Z","publication_status":"published","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540664574","9783540483021"]},"department":[{"_id":"78"}],"title":"Communication Synthesis for Reconfigurable Embedded Systems"},{"type":"journal_article","citation":{"chicago":"Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik Und Informationstechnik 115 (1998): 143–48.","apa":"Platzner, M. (1998). Reconfigurable Computer Architectures. E&i Elektrotechnik Und Informationstechnik, 115, 143–148.","ama":"Platzner M. Reconfigurable Computer Architectures. e&i Elektrotechnik und Informationstechnik. 1998;115:143-148.","bibtex":"@article{Platzner_1998, title={Reconfigurable Computer Architectures}, volume={115}, journal={e&i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco}, year={1998}, pages={143–148} }","mla":"Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik Und Informationstechnik, vol. 115, Springer, 1998, pp. 143–48.","short":"M. Platzner, E&i Elektrotechnik Und Informationstechnik 115 (1998) 143–148.","ieee":"M. Platzner, “Reconfigurable Computer Architectures,” e&i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998."},"year":"1998","page":"143-148","language":[{"iso":"eng"}],"intvolume":" 115","_id":"10607","date_updated":"2022-01-06T06:50:47Z","volume":115,"status":"public","date_created":"2019-07-10T09:22:59Z","publisher":"Springer","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"e&i Elektrotechnik und Informationstechnik","department":[{"_id":"78"}],"title":"Reconfigurable Computer Architectures","user_id":"398","extern":"1"},{"user_id":"398","title":"Design and Implementation of a Parallel Constraint Satisfaction Algorithm","extern":"1","status":"public","date_created":"2019-07-10T09:23:00Z","volume":5,"author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"}],"publisher":"ISCA","publication":"International Journal of Computers & Their Applications","department":[{"_id":"78"}],"_id":"10608","date_updated":"2022-01-06T06:50:47Z","intvolume":" 5","language":[{"iso":"eng"}],"citation":{"ieee":"M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers & Their Applications, vol. 5, pp. 106–116, 1998.","short":"M. Platzner, B. Rinner, International Journal of Computers & Their Applications 5 (1998) 106–116.","bibtex":"@article{Platzner_Rinner_1998, title={Design and Implementation of a Parallel Constraint Satisfaction Algorithm}, volume={5}, journal={International Journal of Computers & Their Applications}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1998}, pages={106–116} }","mla":"Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers & Their Applications, vol. 5, ISCA, 1998, pp. 106–16.","ama":"Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications. 1998;5:106-116.","apa":"Platzner, M., & Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications, 5, 106–116.","chicago":"Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers & Their Applications 5 (1998): 106–16."},"year":"1998","type":"journal_article","page":"106-116"},{"page":"106-107","citation":{"short":"M. Platzner, B. Rinner, R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation , Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998.","ieee":"M. Platzner, B. Rinner, and R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–107.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1998). A Distributed Computer Architecture for Fast Qualitative Simulation (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities.","ama":"Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities; 1998:106-107.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998.","bibtex":"@book{Platzner_Rinner_Weiss_1998, title={A Distributed Computer Architecture for Fast Qualitative Simulation }, publisher={Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1998}, pages={106–107} }","mla":"Platzner, Marco, et al. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–07."},"year":"1998","type":"misc","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:36Z","_id":"13464","date_created":"2019-09-30T09:33:27Z","status":"public","department":[{"_id":"78"}],"publisher":"Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe's leading Universities","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"},{"first_name":"Reinhold","full_name":"Weiss, Reinhold","last_name":"Weiss"}],"title":"A Distributed Computer Architecture for Fast Qualitative Simulation ","user_id":"398"},{"publication_status":"published","publication_identifier":{"isbn":["9783540649489","9783540680666"],"issn":["0302-9743","1611-3349"]},"department":[{"_id":"78"}],"title":"Acceleration of satisfiability algorithms by reconfigurable hardware","place":"Berlin, Heidelberg","language":[{"iso":"eng"}],"series_title":"LNCS","doi":"10.1007/bfb0055234","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T20:46:34Z","status":"public","publication":"Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) ","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"De Micheli, Giovanni","first_name":"Giovanni","last_name":"De Micheli"}],"publisher":"Springer ","user_id":"398","extern":"1","page":"69-78","type":"conference","citation":{"ieee":"M. Platzner and G. De Micheli, “Acceleration of satisfiability algorithms by reconfigurable hardware,” in Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , 1998, pp. 69–78.","short":"M. Platzner, G. De Micheli, in: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , Berlin, Heidelberg, 1998, pp. 69–78.","bibtex":"@inproceedings{Platzner_De Micheli_1998, place={Berlin, Heidelberg}, series={LNCS}, title={Acceleration of satisfiability algorithms by reconfigurable hardware}, DOI={10.1007/bfb0055234}, booktitle={Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={Springer }, author={Platzner, Marco and De Micheli, Giovanni}, year={1998}, pages={69–78}, collection={LNCS} }","mla":"Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , 1998, pp. 69–78, doi:10.1007/bfb0055234.","apa":"Platzner, M., & De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 69–78). Berlin, Heidelberg: Springer . https://doi.org/10.1007/bfb0055234","ama":"Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:10.1007/bfb0055234","chicago":"Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , 69–78. LNCS. Berlin, Heidelberg: Springer , 1998. https://doi.org/10.1007/bfb0055234."},"year":"1998","_id":"13606"},{"language":[{"iso":"eng"}],"year":"1997","citation":{"bibtex":"@article{Platzner_Rinner_Weiss_1997, title={A Computer Architecture to Support Qualitative Simulation in Industrial Applications}, volume={114}, journal={e & i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={13–18} }","mla":"Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E & i Elektrotechnik Und Informationstechnik, vol. 114, Springer, 1997, pp. 13–18.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E & i Elektrotechnik Und Informationstechnik 114 (1997): 13–18.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. E & i Elektrotechnik Und Informationstechnik, 114, 13–18.","ama":"Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. e & i Elektrotechnik und Informationstechnik. 1997;114:13-18.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e & i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997.","short":"M. Platzner, B. Rinner, R. Weiss, E & i Elektrotechnik Und Informationstechnik 114 (1997) 13–18."},"type":"journal_article","page":"13-18","intvolume":" 114","_id":"10609","date_updated":"2022-01-06T06:50:47Z","status":"public","date_created":"2019-07-10T09:23:09Z","volume":114,"publisher":"Springer","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"department":[{"_id":"78"}],"publication":"e & i Elektrotechnik und Informationstechnik","user_id":"398","title":"A Computer Architecture to Support Qualitative Simulation in Industrial Applications","extern":"1"},{"extern":"1","title":"Parallel qualitative simulation","user_id":"398","department":[{"_id":"78"}],"publication":"Simulation Practice and Theory","publisher":"Elsevier","author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"},{"last_name":"Weiss","full_name":"Weiss, Reinhold","first_name":"Reinhold"}],"volume":5,"date_created":"2019-07-10T11:54:16Z","status":"public","intvolume":" 5","_id":"10724","date_updated":"2022-01-06T06:50:50Z","doi":"10.1016/s0928-4869(97)00008-6","issue":"7-8","page":"623-638","type":"journal_article","citation":{"short":"M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997) 623–638.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative Simulation.” Simulation Practice and Theory 5, no. 7–8 (1997): 623–38. https://doi.org/10.1016/s0928-4869(97)00008-6.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1997). Parallel qualitative simulation. Simulation Practice and Theory, 5(7–8), 623–638. https://doi.org/10.1016/s0928-4869(97)00008-6","ama":"Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6","bibtex":"@article{Platzner_Rinner_Weiss_1997, title={Parallel qualitative simulation}, volume={5}, DOI={10.1016/s0928-4869(97)00008-6}, number={7–8}, journal={Simulation Practice and Theory}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={623–638} }","mla":"Platzner, Marco, et al. “Parallel Qualitative Simulation.” Simulation Practice and Theory, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:10.1016/s0928-4869(97)00008-6."},"year":"1997","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"type":"conference","year":"1997","citation":{"mla":"Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, vol. 3166, 1997.","bibtex":"@inproceedings{Platzner_Peters_1997, title={Fast Signature Segmentation on a Multi-DSP Architecture}, volume={3166}, booktitle={Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing}, author={Platzner, Marco and Peters, Liliane}, year={1997} }","ama":"Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing. Vol 3166. ; 1997.","apa":"Platzner, M., & Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).","chicago":"Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, Vol. 3166, 1997.","ieee":"M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,” in Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997, vol. 3166.","short":"M. Platzner, L. Peters, in: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997."},"intvolume":" 3166","_id":"13603","date_updated":"2022-01-06T06:51:40Z","status":"public","date_created":"2019-10-04T20:40:55Z","volume":3166,"author":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Peters, Liliane","first_name":"Liliane","last_name":"Peters"}],"department":[{"_id":"78"}],"publication":"Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing","user_id":"398","title":"Fast Signature Segmentation on a Multi-DSP Architecture","extern":"1"},{"user_id":"398","title":"Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP","extern":"1","date_created":"2019-10-04T20:43:29Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT)","author":[{"last_name":"Röwekamp","full_name":"Röwekamp, Thomas","first_name":"Thomas"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Peters","full_name":"Peters, Liliane ","first_name":"Liliane "}],"date_updated":"2022-01-06T06:51:40Z","_id":"13604","language":[{"iso":"eng"}],"page":"829-833","type":"conference","year":"1997","citation":{"short":"T. Röwekamp, M. Platzner, L. Peters, in: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–833.","ieee":"T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–833.","chicago":"Röwekamp, Thomas, Marco Platzner, and Liliane Peters. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 829–33, 1997.","apa":"Röwekamp, T., Platzner, M., & Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) (pp. 829–833).","ama":"Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1997:829-833.","mla":"Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–33.","bibtex":"@inproceedings{Röwekamp_Platzner_Peters_1997, title={Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP}, booktitle={Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT)}, author={Röwekamp, Thomas and Platzner, Marco and Peters, Liliane }, year={1997}, pages={829–833} }"}},{"_id":"13602","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"1996","citation":{"short":"E. Lind, M. Platzner, B. Rinner, in: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.","ieee":"E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically Reconfigurable Processors,” in Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.","chicago":"Lind, Erich, Marco Platzner, and Bernhard Rinner. “A Multi-DSP System with Dynamically Reconfigurable Processors.” In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.","ama":"Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1996.","apa":"Lind, E., Platzner, M., & Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT).","mla":"Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.” Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.","bibtex":"@inproceedings{Lind_Platzner_Rinner_1996, title={A Multi-DSP System with Dynamically Reconfigurable Processors}, booktitle={Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT)}, author={Lind, Erich and Platzner, Marco and Rinner, Bernhard }, year={1996} }"},"type":"conference","extern":"1","user_id":"398","title":"A Multi-DSP System with Dynamically Reconfigurable Processors","publication":"Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT)","department":[{"_id":"78"}],"author":[{"last_name":"Lind","full_name":"Lind, Erich","first_name":"Erich"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Bernhard ","full_name":"Rinner, Bernhard ","last_name":"Rinner"}],"date_created":"2019-10-04T20:37:59Z","status":"public"},{"author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"},{"last_name":"Weiss","full_name":"Weiss, Reinhold","first_name":"Reinhold"}],"publisher":"Springer","department":[{"_id":"78"}],"publication":"J.UCS Journal of Universal Computer Science","status":"public","date_created":"2019-07-10T09:23:10Z","volume":12,"extern":"1","user_id":"398","title":"Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation","language":[{"iso":"eng"}],"type":"journal_article","citation":{"bibtex":"@article{Platzner_Rinner_Weiss_1995, title={Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation}, volume={12}, journal={J.UCS Journal of Universal Computer Science}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1995}, pages={811–820} }","mla":"Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science, vol. 12, Springer, 1995, pp. 811–20.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science 12 (1995): 811–20.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal Computer Science, 12, 811–820.","ama":"Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. JUCS Journal of Universal Computer Science. 1995;12:811-820.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995.","short":"M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science 12 (1995) 811–820."},"year":"1995","page":"811-820","_id":"10610","date_updated":"2022-01-06T06:50:47Z","intvolume":" 12"},{"publication":"Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing ","department":[{"_id":"78"}],"publisher":"IEEE CS Press","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Rinner, Bernhard","first_name":"Bernhard","last_name":"Rinner"},{"last_name":"Weiss","first_name":"Reinhold ","full_name":"Weiss, Reinhold "}],"date_created":"2019-09-30T10:56:45Z","status":"public","extern":"1","user_id":"398","title":"A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs","language":[{"iso":"eng"}],"page":"311-318","year":"1995","citation":{"short":"M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–318.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs,” in Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 1995, pp. 311–318.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 311–18. IEEE CS Press, 1995.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (pp. 311–318). IEEE CS Press.","ama":"Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing . IEEE CS Press; 1995:311-318.","mla":"Platzner, Marco, et al. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–18.","bibtex":"@inproceedings{Platzner_Rinner_Weiss_1995, title={A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs}, booktitle={Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing }, publisher={IEEE CS Press}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold }, year={1995}, pages={311–318} }"},"type":"conference","date_updated":"2022-01-06T06:51:36Z","_id":"13469"},{"status":"public","date_created":"2019-09-30T11:02:15Z","author":[{"last_name":"Brenner","full_name":"Brenner, Eugen","first_name":"Eugen"},{"last_name":"Ginthör-Kalcsics","full_name":"Ginthör-Kalcsics, Robert","first_name":"Robert"},{"last_name":"Hranitzky","full_name":"Hranitzky, Robert","first_name":"Robert"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard ","first_name":"Bernhard "},{"first_name":"Christian ","full_name":"Steger, Christian ","last_name":"Steger"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference","user_id":"398","title":"High-Performance Simulators Based on Multi-TMS320C40","language":[{"iso":"eng"}],"citation":{"mla":"Brenner, Eugen, et al. “High-Performance Simulators Based on Multi-TMS320C40.” Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995.","bibtex":"@inproceedings{Brenner_Ginthör-Kalcsics_Hranitzky_Platzner_Rinner_Steger_Weiss_1995, title={High-Performance Simulators Based on Multi-TMS320C40}, booktitle={Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference}, author={Brenner, Eugen and Ginthör-Kalcsics, Robert and Hranitzky, Robert and Platzner, Marco and Rinner, Bernhard and Steger, Christian and Weiss, Reinhold}, year={1995} }","chicago":"Brenner, Eugen, Robert Ginthör-Kalcsics, Robert Hranitzky, Marco Platzner, Bernhard Rinner, Christian Steger, and Reinhold Weiss. “High-Performance Simulators Based on Multi-TMS320C40.” In Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995.","apa":"Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., & Weiss, R. (1995). High-Performance Simulators Based on Multi-TMS320C40. In Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference.","ama":"Brenner E, Ginthör-Kalcsics R, Hranitzky R, et al. High-Performance Simulators Based on Multi-TMS320C40. In: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference. ; 1995.","ieee":"E. Brenner et al., “High-Performance Simulators Based on Multi-TMS320C40,” in Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995.","short":"E. Brenner, R. Ginthör-Kalcsics, R. Hranitzky, M. Platzner, B. Rinner, C. Steger, R. Weiss, in: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995."},"type":"conference","year":"1995","date_updated":"2022-01-06T06:51:36Z","_id":"13470","conference":{"name":"Robert Ginthör-Kalcsics"}},{"date_created":"2019-09-30T11:15:06Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the EURO-PAR'95 International Conference on Parallel Processing","author":[{"last_name":"Friedl","first_name":"Gerald","full_name":"Friedl, Gerald"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Bernhard","full_name":"Rinner, Bernhard","last_name":"Rinner"}],"publisher":"Springer International Publishing","user_id":"398","title":"A Special-Purpose Coprocessor for Qualitative Simulation","extern":"1","language":[{"iso":"eng"}],"page":"695-698","citation":{"bibtex":"@inproceedings{Friedl_Platzner_Rinner_1995, title={A Special-Purpose Coprocessor for Qualitative Simulation}, booktitle={Proceedings of the EURO-PAR’95 International Conference on Parallel Processing}, publisher={Springer International Publishing}, author={Friedl, Gerald and Platzner, Marco and Rinner, Bernhard}, year={1995}, pages={695–698} }","mla":"Friedl, Gerald, et al. “A Special-Purpose Coprocessor for Qualitative Simulation.” Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–98.","chicago":"Friedl, Gerald, Marco Platzner, and Bernhard Rinner. “A Special-Purpose Coprocessor for Qualitative Simulation.” In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 695–98. Springer International Publishing, 1995.","ama":"Friedl G, Platzner M, Rinner B. A Special-Purpose Coprocessor for Qualitative Simulation. In: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing. Springer International Publishing; 1995:695-698.","apa":"Friedl, G., Platzner, M., & Rinner, B. (1995). A Special-Purpose Coprocessor for Qualitative Simulation. In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing (pp. 695–698). Springer International Publishing.","ieee":"G. Friedl, M. Platzner, and B. Rinner, “A Special-Purpose Coprocessor for Qualitative Simulation,” in Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 1995, pp. 695–698.","short":"G. Friedl, M. Platzner, B. Rinner, in: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–698."},"year":"1995","type":"conference","date_updated":"2022-01-06T06:51:36Z","_id":"13471"},{"title":"Parallel Qualitative Simulation","user_id":"398","extern":"1","status":"public","date_created":"2019-09-30T11:16:45Z","author":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"},{"full_name":"Weiss, Reinhold ","first_name":"Reinhold ","last_name":"Weiss"}],"publisher":"Elsevier","publication":"Proceedings of the EUROSIM Congress","department":[{"_id":"78"}],"_id":"13472","date_updated":"2022-01-06T06:51:36Z","year":"1995","citation":{"ieee":"M. Platzner, B. Rinner, and R. Weiss, “Parallel Qualitative Simulation,” in Proceedings of the EUROSIM Congress, 1995, pp. 231–236.","short":"M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–236.","bibtex":"@inproceedings{Platzner_Rinner_Weiss_1995, title={Parallel Qualitative Simulation}, booktitle={Proceedings of the EUROSIM Congress}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold }, year={1995}, pages={231–236} }","mla":"Platzner, Marco, et al. “Parallel Qualitative Simulation.” Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–36.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative Simulation.” In Proceedings of the EUROSIM Congress, 231–36. Elsevier, 1995.","ama":"Platzner M, Rinner B, Weiss R. Parallel Qualitative Simulation. In: Proceedings of the EUROSIM Congress. Elsevier; 1995:231-236.","apa":"Platzner, M., Rinner, B., & Weiss, R. (1995). Parallel Qualitative Simulation. In Proceedings of the EUROSIM Congress (pp. 231–236). Elsevier."},"type":"conference","page":"231-236","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"page":"494-501","citation":{"ieee":"M. Platzner and B. Rinner, “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture,” in Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, 1995, pp. 494–501.","short":"M. Platzner, B. Rinner, in: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501.","bibtex":"@inproceedings{Platzner_Rinner_1995, title={Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture}, booktitle={Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1995}, pages={494–501} }","mla":"Platzner, Marco, and Bernhard Rinner. “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture.” Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501.","apa":"Platzner, M., & Rinner, B. (1995). Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems (pp. 494–501). ISCA.","ama":"Platzner M, Rinner B. Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems. ISCA; 1995:494-501.","chicago":"Platzner, Marco, and Bernhard Rinner. “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture.” In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, 494–501. ISCA, 1995."},"year":"1995","type":"conference","_id":"13473","date_updated":"2022-01-06T06:51:36Z","date_created":"2019-09-30T11:19:05Z","status":"public","department":[{"_id":"78"}],"publication":"Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems","author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"}],"publisher":"ISCA","user_id":"398","title":"Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture","extern":"1"}]