[{"project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"citation":{"ama":"Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. <i>4th Workshop On Approximate Computing (WAPCO 2018)</i>. 2018.","bibtex":"@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018} }","mla":"Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” <i>4th Workshop On Approximate Computing (WAPCO 2018)</i>, 2018.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making the Case for Proof-Carrying Approximate Circuits.” <i>4th Workshop On Approximate Computing (WAPCO 2018)</i>, 2018.","short":"L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018).","apa":"Witschen, L. M., Wiersema, T., &#38; Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. <i>4th Workshop On Approximate Computing (WAPCO 2018)</i>.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” <i>4th Workshop On Approximate Computing (WAPCO 2018)</i>. 2018."},"file_date_updated":"2018-11-26T08:00:53Z","publication":"4th Workshop On Approximate Computing (WAPCO 2018)","department":[{"_id":"7"},{"_id":"34"},{"_id":"78"}],"type":"preprint","date_created":"2018-02-01T14:24:54Z","file":[{"creator":"tobias82","date_created":"2018-11-26T08:00:53Z","file_name":"WitschenWP2018[1].pdf","access_level":"closed","file_size":287224,"relation":"main_file","date_updated":"2018-11-26T08:00:53Z","file_id":"5821","content_type":"application/pdf","success":1}],"has_accepted_license":"1","date_updated":"2022-01-06T06:51:06Z","author":[{"id":"49051","last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"status":"public","title":"Making the Case for Proof-carrying Approximate Circuits","year":"2018","user_id":"49051","ddc":["000"],"language":[{"iso":"eng"}],"_id":"1165"},{"has_accepted_license":"1","conference":{"end_date":"2018-07-12","location":"Milan, Italy","start_date":"2018-07-10","name":"The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors"},"status":"public","ddc":["040"],"user_id":"43646","publisher":"IEEE","_id":"5547","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}],"citation":{"bibtex":"@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }","ama":"Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>","mla":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>.","chicago":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>.","short":"A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.","ieee":"A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, Milan, Italy, 2018.","apa":"Lösch, A., &#38; Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. Milan, Italy: IEEE. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>"},"file_date_updated":"2018-11-14T09:40:42Z","date_updated":"2022-01-06T07:01:59Z","publication_status":"published","author":[{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"isbn":["9781538674796"]},"year":"2018","title":"A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes","doi":"10.1109/asap.2018.8445098","language":[{"iso":"eng"}],"publication":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","department":[{"_id":"78"}],"type":"conference","date_created":"2018-11-14T09:26:53Z","file":[{"success":1,"content_type":"application/pdf","file_id":"5552","file_size":2464949,"access_level":"closed","file_name":"loesch_asap2018.pdf","date_updated":"2018-11-14T09:40:42Z","relation":"main_file","date_created":"2018-11-14T09:40:42Z","creator":"aloesch"}]},{"keyword":["Approximate computing","High-level synthesis","Accuracy","Monte-Carlo tree search","Circuit simulation"],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T09:21:38Z","abstract":[{"text":"Approximate computing has become a very popular design\r\nstrategy that exploits error resilient computations to achieve higher\r\nperformance and energy efficiency. Automated synthesis of approximate\r\ncircuits is performed via functional approximation, in which various\r\nparts of the target circuit are extensively examined with a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy and computational budget (i.e., power). However, as the number\r\nof possible approximate transformations increases, traditional search\r\ntechniques suffer from a combinatorial explosion due to the large\r\nbranching factor. In this work, we present a comprehensive framework\r\nfor automated synthesis of approximate circuits from either structural\r\nor behavioral descriptions. We adapt the Monte Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the large design\r\nspace exploration, which enables a broader range of potential possible\r\napproximations through lightweight random simulations. The proposed\r\nframework is able to recognize the design Pareto set even with low\r\ncomputational budgets. Experimental results highlight the capabilities of\r\nthe proposed synthesis framework by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined quality constraints.","lang":"eng"}],"publication":"26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","citation":{"chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” In <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 219–24, 2018. <a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">https://doi.org/10.1109/VLSI-SoC.2018.8645026</a>.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>. ; 2018:219-224. doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based Framework for Synthesis of Approximate Circuits}, DOI={<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>}, booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2018}, pages={219–224} }","apa":"Awais, M., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i> (pp. 219–224). <a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">https://doi.org/10.1109/VLSI-SoC.2018.8645026</a>","mla":"Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2018, pp. 219–24, doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2018, pp. 219–224."},"user_id":"64665","doi":"10.1109/VLSI-SoC.2018.8645026","page":"219-224","language":[{"iso":"eng"}],"_id":"10598","date_updated":"2022-01-06T06:50:46Z","title":"An MCTS-based Framework for Synthesis of Approximate Circuits","status":"public","year":"2018","author":[{"full_name":"Awais, Muhammad","first_name":"Muhammad","last_name":"Awais","orcid":"https://orcid.org/0000-0003-4148-2969","id":"64665"},{"id":"61186","first_name":"Hassan","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}]},{"date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287"}],"status":"public","title":"Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data","year":"2018","user_id":"3118","publisher":"Ruhr-University Bochum","_id":"10782","language":[{"iso":"eng"}],"extern":"1","citation":{"ama":"Clausing L. <i>Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data</i>. Ruhr-University Bochum; 2018.","bibtex":"@book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }","mla":"Clausing, Lennart. <i>Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data</i>. Ruhr-University Bochum, 2018.","chicago":"Clausing, Lennart. <i>Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data</i>. Ruhr-University Bochum, 2018.","short":"L. Clausing, Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.","apa":"Clausing, L. (2018). <i>Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data</i>. Ruhr-University Bochum.","ieee":"L. Clausing, <i>Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data</i>. Ruhr-University Bochum, 2018."},"department":[{"_id":"78"}],"type":"mastersthesis","date_created":"2019-07-10T12:13:18Z"},{"project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"short":"F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.","chicago":"Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018.","apa":"Jentzsch, F. P. (2018). <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn.","ieee":"F. P. Jentzsch, <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018.","ama":"Jentzsch FP. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn; 2018.","bibtex":"@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }","mla":"Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018."},"supervisor":[{"first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias","id":"3118"}],"type":"bachelorsthesis","keyword":["Approximate Computing","Proof-Carrying Hardware","Formal Verification"],"department":[{"_id":"78"}],"date_created":"2018-01-15T16:48:05Z","date_updated":"2022-01-06T06:50:54Z","status":"public","title":"Enforcing IP Core Connection Properties with Verifiable Security Monitors","year":"2018","author":[{"full_name":"Jentzsch, Felix Paul","first_name":"Felix Paul","last_name":"Jentzsch"}],"user_id":"477","_id":"1097","publisher":"Universität Paderborn","language":[{"iso":"eng"}]},{"date_created":"2019-08-26T13:33:00Z","department":[{"_id":"78"}],"type":"journal_article","citation":{"ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” <i>IEEE Access</i>, pp. 14078–14092, 2018.","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., &#38; Platzner, M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. <i>IEEE Access</i>, 14078–14092. <a href=\"https://doi.org/10.1109/access.2018.2799852\">https://doi.org/10.1109/access.2018.2799852</a>","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet, and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” <i>IEEE Access</i>, 2018, 14078–92. <a href=\"https://doi.org/10.1109/access.2018.2799852\">https://doi.org/10.1109/access.2018.2799852</a>.","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018) 14078–14092.","mla":"Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” <i>IEEE Access</i>, 2018, pp. 14078–92, doi:<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>.","bibtex":"@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }","ama":"Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. <i>IEEE Access</i>. 2018:14078-14092. doi:<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>"},"publication":"IEEE Access","language":[{"iso":"eng"}],"_id":"12965","page":"14078-14092","doi":"10.1109/access.2018.2799852","user_id":"398","author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"last_name":"Abdallah","first_name":"Riadh Ben","full_name":"Abdallah, Riadh Ben"},{"full_name":"Khalgui, Mohamed","last_name":"Khalgui","first_name":"Mohamed"},{"last_name":"Li","first_name":"Zhiwu","full_name":"Li, Zhiwu"},{"full_name":"Alnowibet, Khalid","last_name":"Alnowibet","first_name":"Khalid"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"issn":["2169-3536"]},"title":"R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints","year":"2018","status":"public","date_updated":"2022-01-06T06:51:27Z","publication_status":"published"},{"date_updated":"2022-01-06T06:59:25Z","status":"public","title":"An FPGA Accelerator for Checking Resolution Proofs","year":"2017","author":[{"full_name":"Hansmeier, Tim","first_name":"Tim","orcid":"0000-0003-1377-3339","last_name":"Hansmeier","id":"49992"}],"user_id":"3118","_id":"3580","publisher":"Universität Paderborn","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"supervisor":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"citation":{"ieee":"T. Hansmeier, <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität Paderborn, 2017.","apa":"Hansmeier, T. (2017). <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität Paderborn.","chicago":"Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität Paderborn, 2017.","short":"T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität Paderborn, 2017.","mla":"Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität Paderborn, 2017.","bibtex":"@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }","ama":"Hansmeier T. <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität Paderborn; 2017."},"type":"bachelorsthesis","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"date_created":"2018-07-20T13:44:34Z"},{"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"}],"citation":{"bibtex":"@book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }","ama":"Witschen LM. <i>A Framework for the Synthesis of Approximate Circuits</i>. Universität Paderborn; 2017.","mla":"Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate Circuits</i>. Universität Paderborn, 2017.","chicago":"Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate Circuits</i>. Universität Paderborn, 2017.","short":"L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität Paderborn, 2017.","ieee":"L. M. Witschen, <i>A Framework for the Synthesis of Approximate Circuits</i>. Universität Paderborn, 2017.","apa":"Witschen, L. M. (2017). <i>A Framework for the Synthesis of Approximate Circuits</i>. Universität Paderborn."},"type":"mastersthesis","department":[{"_id":"78"},{"_id":"7"}],"date_created":"2018-02-01T14:21:19Z","date_updated":"2022-01-06T06:51:03Z","status":"public","year":"2017","title":"A Framework for the Synthesis of Approximate Circuits","author":[{"full_name":"Witschen, Linus Matthias","last_name":"Witschen","first_name":"Linus Matthias","id":"49051"}],"user_id":"477","publisher":"Universität Paderborn","_id":"1157","language":[{"iso":"eng"}]},{"date_created":"2017-10-17T12:41:05Z","department":[{"_id":"78"}],"type":"mastersthesis","citation":{"short":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten, Universität Paderborn, 2017.","chicago":"Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017.","apa":"Knorr, C. (2017). <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn.","ieee":"C. Knorr, <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017.","ama":"Knorr C. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn; 2017.","bibtex":"@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }","mla":"Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017."},"supervisor":[{"full_name":"Lösch, Achim","first_name":"Achim","last_name":"Lösch","id":"43646"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"language":[{"iso":"ger"}],"_id":"74","publisher":"Universität Paderborn","user_id":"477","author":[{"first_name":"Christoph","last_name":"Knorr","full_name":"Knorr, Christoph"}],"title":"OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten","year":"2017","status":"public","date_updated":"2022-01-06T07:03:36Z"},{"volume":94,"doi":"10.1016/j.ijepes.2017.07.007","user_id":"3118","_id":"9919","language":[{"iso":"eng"}],"page":"287-299","intvolume":"        94","date_updated":"2019-10-06T21:56:18Z","publication_status":"published","author":[{"full_name":"Shen, Cong","last_name":"Shen","first_name":"Cong"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Martin","last_name":"Braun","full_name":"Braun, Martin"}],"status":"public","title":"Three-Stage Power System Restoration Methodology Considering Renewable Energies","year":"2017","department":[{"_id":"78"}],"keyword":["Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations"],"type":"journal_article","date_created":"2019-05-22T13:14:20Z","abstract":[{"lang":"eng","text":"This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network."}],"citation":{"ama":"Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. <i>Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)</i>. 2017;94:287-299. doi:<a href=\"https://doi.org/10.1016/j.ijepes.2017.07.007\">10.1016/j.ijepes.2017.07.007</a>","bibtex":"@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, volume={94}, DOI={<a href=\"https://doi.org/10.1016/j.ijepes.2017.07.007\">10.1016/j.ijepes.2017.07.007</a>}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={287–299} }","mla":"Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” <i>Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)</i>, vol. 94, 2017, pp. 287–99, doi:<a href=\"https://doi.org/10.1016/j.ijepes.2017.07.007\">10.1016/j.ijepes.2017.07.007</a>.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” <i>Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)</i> 94 (2017): 287–99. <a href=\"https://doi.org/10.1016/j.ijepes.2017.07.007\">https://doi.org/10.1016/j.ijepes.2017.07.007</a>.","short":"C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017) 287–299.","apa":"Shen, C., Kaufmann, P., &#38; Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. <i>Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)</i>, <i>94</i>, 287–299. <a href=\"https://doi.org/10.1016/j.ijepes.2017.07.007\">https://doi.org/10.1016/j.ijepes.2017.07.007</a>","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” <i>Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)</i>, vol. 94, pp. 287–299, 2017."},"publication":"Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)"},{"has_accepted_license":"1","date_updated":"2022-01-06T07:03:08Z","author":[{"id":"43646","full_name":"Lösch, Achim","first_name":"Achim","last_name":"Lösch"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements","status":"public","year":"2017","user_id":"477","doi":"10.1109/ASAP.2017.7995272","ddc":["040"],"language":[{"iso":"eng"}],"_id":"65","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"abstract":[{"text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.","lang":"eng"}],"citation":{"bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. ; 2017. doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>","mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017, doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>.","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.","chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>.","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, 2017.","apa":"Lösch, A., &#38; Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>"},"file_date_updated":"2018-11-14T09:37:55Z","publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:41:04Z","file":[{"file_name":"loesch_asap2017.pdf","access_level":"closed","file_size":467545,"relation":"main_file","date_updated":"2018-11-14T09:37:55Z","file_id":"5550","content_type":"application/pdf","success":1,"creator":"aloesch","date_created":"2018-11-14T09:37:55Z"}]},{"file_date_updated":"2018-11-02T16:08:17Z","citation":{"ama":"Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>. 2017;(4):61:1--61:23. doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>","bibtex":"@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }","mla":"Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, ACM, 2017, pp. 61:1--61:23, doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>.","short":"T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23.","chicago":"Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4 (2017): 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>.","apa":"Isenberg, T., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>, (4), 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>","ieee":"T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, pp. 61:1--61:23, 2017."},"project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"page":"61:1--61:23","_id":"68","publisher":"ACM","user_id":"3118","ddc":["000"],"status":"public","has_accepted_license":"1","file":[{"creator":"ups","date_created":"2018-11-02T16:08:17Z","file_name":"a61-isenberg.pdf","access_level":"closed","file_size":806356,"relation":"main_file","date_updated":"2018-11-02T16:08:17Z","file_id":"5324","content_type":"application/pdf","success":1}],"date_created":"2017-10-17T12:41:04Z","type":"journal_article","department":[{"_id":"77"},{"_id":"78"}],"issue":"4","publication":"ACM Transactions on Design Automation of Electronic Systems","abstract":[{"lang":"eng","text":"Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits."}],"language":[{"iso":"eng"}],"doi":"10.1145/3054743","year":"2017","title":"Proof-Carrying Hardware via Inductive Invariants","author":[{"last_name":"Isenberg","first_name":"Tobias","full_name":"Isenberg, Tobias"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"id":"573","first_name":"Heike","last_name":"Wehrheim","full_name":"Wehrheim, Heike"},{"id":"3118","last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias"}],"date_updated":"2022-01-06T07:03:20Z"},{"author":[{"first_name":"Philip","last_name":"H.W. Leong","full_name":"H.W. Leong, Philip"},{"first_name":"Hideharu","last_name":"Amano","full_name":"Amano, Hideharu"},{"full_name":"Anderson, Jason","last_name":"Anderson","first_name":"Jason"},{"full_name":"Bertels, Koen","first_name":"Koen","last_name":"Bertels"},{"last_name":"M.P. Cardoso","first_name":"Jo\\~{a}o","full_name":"M.P. Cardoso, Jo\\~{a}o"},{"first_name":"Oliver","last_name":"Diessel","full_name":"Diessel, Oliver"},{"last_name":"Gogniat","first_name":"Guy","full_name":"Gogniat, Guy"},{"full_name":"Hutton, Mike","last_name":"Hutton","first_name":"Mike"},{"full_name":"Lee, JunKyu","last_name":"Lee","first_name":"JunKyu"},{"first_name":"Wayne","last_name":"Luk","full_name":"Luk, Wayne"},{"full_name":"Lysaght, Patrick","first_name":"Patrick","last_name":"Lysaght"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"K. Prasanna, Viktor","first_name":"Viktor","last_name":"K. Prasanna"},{"last_name":"Rissa","first_name":"Tero","full_name":"Rissa, Tero"},{"full_name":"Silvano, Cristina","first_name":"Cristina","last_name":"Silvano"},{"full_name":"So, Hayden","first_name":"Hayden","last_name":"So"},{"full_name":"Wang, Yu","last_name":"Wang","first_name":"Yu"}],"title":"The First 25 Years of the FPL Conference – Significant Papers","status":"public","year":"2017","date_updated":"2022-01-06T06:50:47Z","language":[{"iso":"eng"}],"_id":"10600","doi":"10.1145/2996468","user_id":"398","citation":{"mla":"H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017, doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>.","bibtex":"@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }","ama":"H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. 2017. doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>","ieee":"P. H.W. Leong <i>et al.</i>, “The First 25 Years of the FPL Conference – Significant Papers,” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017.","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017).","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>."},"publication":"ACM Transactions on Reconfigurable Technology and Systems","date_created":"2019-07-10T09:22:27Z","department":[{"_id":"78"}],"type":"journal_article"},{"doi":"10.1109/TETC.2016.2641599","user_id":"398","language":[{"iso":"eng"}],"_id":"10601","date_updated":"2022-01-06T06:50:47Z","status":"public","title":"Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)","year":"2017","author":[{"last_name":"F. DeMara","first_name":"Ronald","full_name":"F. DeMara, Ronald"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"last_name":"Ottavi","first_name":"Marco","full_name":"Ottavi, Marco"}],"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:28Z","publication":"IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing","citation":{"chicago":"F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>.","short":"R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017).","ieee":"R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017.","apa":"F. DeMara, R., Platzner, M., &#38; Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>","bibtex":"@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }","ama":"F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. 2017. doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>","mla":"F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017, doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>."}},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:23:11Z","citation":{"bibtex":"@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }","ama":"Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>. 2017:160-172. doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>","mla":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, Elsevier, 2017, pp. 160–72, doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, 2017, 160–72. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>.","short":"J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.","ieee":"J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” <i>Microprocessors and Microsystems</i>, pp. 160–172, 2017.","apa":"Anwer, J., &#38; Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>, 160–172. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>"},"publication":"Microprocessors and Microsystems","user_id":"3118","doi":"10.1016/j.micpro.2017.06.002","_id":"10611","language":[{"iso":"eng"}],"publisher":"Elsevier","page":"160-172","date_updated":"2022-01-06T06:50:47Z","author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"year":"2017","title":"Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus","status":"public"},{"citation":{"chicago":"Kaltschmidt, Christian. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017.","short":"C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control, Paderborn University, 2017.","apa":"Kaltschmidt, C. (2017). <i>An AR-based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University.","ieee":"C. Kaltschmidt, <i>An AR-based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017.","ama":"Kaltschmidt C. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University; 2017.","bibtex":"@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }","mla":"Kaltschmidt, Christian. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017."},"department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2019-07-10T09:25:11Z","date_updated":"2022-01-06T06:50:47Z","author":[{"full_name":"Kaltschmidt, Christian","first_name":"Christian","last_name":"Kaltschmidt"}],"status":"public","title":"An AR-based Training and Assessment System for Myoelectrical Prosthetic Control","year":"2017","user_id":"3118","publisher":"Paderborn University","_id":"10613","language":[{"iso":"eng"}]},{"publication":"Design, Automation and Test in Europe (DATE)","citation":{"mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” <i>Design, Automation and Test in Europe (DATE)</i>, 2017, doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>.","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: <i>Design, Automation and Test in Europe (DATE)</i>. ; 2017. doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in <i>Design, Automation and Test in Europe (DATE)</i>, 2017.","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., &#38; Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In <i>Design, Automation and Test in Europe (DATE)</i>. <a href=\"https://doi.org/10.23919/DATE.2017.7927137\">https://doi.org/10.23919/DATE.2017.7927137</a>","short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. 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