[{"file":[{"date_created":"2018-11-14T09:37:55Z","creator":"aloesch","file_id":"5550","success":1,"content_type":"application/pdf","relation":"main_file","date_updated":"2018-11-14T09:37:55Z","file_name":"loesch_asap2017.pdf","access_level":"closed","file_size":467545}],"date_created":"2017-10-17T12:41:04Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file_date_updated":"2018-11-14T09:37:55Z","citation":{"mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017, doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>.","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. ; 2017. doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>","bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","apa":"Lösch, A., &#38; Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, 2017.","chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>.","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017."},"abstract":[{"lang":"eng","text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules."}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"65","language":[{"iso":"eng"}],"doi":"10.1109/ASAP.2017.7995272","ddc":["040"],"user_id":"477","status":"public","title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements","year":"2017","author":[{"full_name":"Lösch, Achim","first_name":"Achim","last_name":"Lösch","id":"43646"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T07:03:08Z","has_accepted_license":"1"},{"has_accepted_license":"1","status":"public","ddc":["000"],"user_id":"3118","_id":"68","publisher":"ACM","page":"61:1--61:23","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"citation":{"ama":"Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>. 2017;(4):61:1--61:23. doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>","bibtex":"@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }","mla":"Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, ACM, 2017, pp. 61:1--61:23, doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>.","chicago":"Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4 (2017): 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>.","short":"T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23.","apa":"Isenberg, T., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>, (4), 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>","ieee":"T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, pp. 61:1--61:23, 2017."},"file_date_updated":"2018-11-02T16:08:17Z","date_updated":"2022-01-06T07:03:20Z","author":[{"full_name":"Isenberg, Tobias","last_name":"Isenberg","first_name":"Tobias"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike","id":"573"},{"id":"3118","first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias"}],"title":"Proof-Carrying Hardware via Inductive Invariants","year":"2017","doi":"10.1145/3054743","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits."}],"publication":"ACM Transactions on Design Automation of Electronic Systems","issue":"4","department":[{"_id":"77"},{"_id":"78"}],"type":"journal_article","date_created":"2017-10-17T12:41:04Z","file":[{"relation":"main_file","date_updated":"2018-11-02T16:08:17Z","file_name":"a61-isenberg.pdf","access_level":"closed","file_size":806356,"file_id":"5324","success":1,"content_type":"application/pdf","creator":"ups","date_created":"2018-11-02T16:08:17Z"}]},{"user_id":"398","doi":"10.1145/2996468","language":[{"iso":"eng"}],"_id":"10600","date_updated":"2022-01-06T06:50:47Z","title":"The First 25 Years of the FPL Conference – Significant Papers","status":"public","year":"2017","author":[{"full_name":"H.W. Leong, Philip","first_name":"Philip","last_name":"H.W. Leong"},{"first_name":"Hideharu","last_name":"Amano","full_name":"Amano, Hideharu"},{"full_name":"Anderson, Jason","last_name":"Anderson","first_name":"Jason"},{"last_name":"Bertels","first_name":"Koen","full_name":"Bertels, Koen"},{"full_name":"M.P. Cardoso, Jo\\~{a}o","last_name":"M.P. Cardoso","first_name":"Jo\\~{a}o"},{"last_name":"Diessel","first_name":"Oliver","full_name":"Diessel, Oliver"},{"first_name":"Guy","last_name":"Gogniat","full_name":"Gogniat, Guy"},{"full_name":"Hutton, Mike","last_name":"Hutton","first_name":"Mike"},{"full_name":"Lee, JunKyu","last_name":"Lee","first_name":"JunKyu"},{"last_name":"Luk","first_name":"Wayne","full_name":"Luk, Wayne"},{"full_name":"Lysaght, Patrick","last_name":"Lysaght","first_name":"Patrick"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"K. Prasanna, Viktor","last_name":"K. Prasanna","first_name":"Viktor"},{"full_name":"Rissa, Tero","last_name":"Rissa","first_name":"Tero"},{"first_name":"Cristina","last_name":"Silvano","full_name":"Silvano, Cristina"},{"last_name":"So","first_name":"Hayden","full_name":"So, Hayden"},{"first_name":"Yu","last_name":"Wang","full_name":"Wang, Yu"}],"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:27Z","publication":"ACM Transactions on Reconfigurable Technology and Systems","citation":{"ama":"H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. 2017. doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>","bibtex":"@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }","mla":"H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017, doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>.","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017).","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>.","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>","ieee":"P. H.W. Leong <i>et al.</i>, “The First 25 Years of the FPL Conference – Significant Papers,” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017."}},{"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:28Z","publication":"IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing","citation":{"short":"R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017).","chicago":"F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>.","ieee":"R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017.","apa":"F. DeMara, R., Platzner, M., &#38; Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>","bibtex":"@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }","ama":"F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. 2017. doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>","mla":"F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017, doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>."},"user_id":"398","doi":"10.1109/TETC.2016.2641599","_id":"10601","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:47Z","year":"2017","status":"public","title":"Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)","author":[{"last_name":"F. DeMara","first_name":"Ronald","full_name":"F. DeMara, Ronald"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"first_name":"Marco","last_name":"Ottavi","full_name":"Ottavi, Marco"}]},{"publisher":"Elsevier","_id":"10611","language":[{"iso":"eng"}],"page":"160-172","user_id":"3118","doi":"10.1016/j.micpro.2017.06.002","author":[{"first_name":"Jahanzeb","last_name":"Anwer","full_name":"Anwer, Jahanzeb"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"year":"2017","title":"Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus","status":"public","date_updated":"2022-01-06T06:50:47Z","date_created":"2019-07-10T09:23:11Z","department":[{"_id":"78"}],"type":"journal_article","citation":{"mla":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, Elsevier, 2017, pp. 160–72, doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>.","ama":"Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>. 2017:160-172. doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>","bibtex":"@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }","apa":"Anwer, J., &#38; Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>, 160–172. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>","ieee":"J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” <i>Microprocessors and Microsystems</i>, pp. 160–172, 2017.","short":"J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, 2017, 160–72. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>."},"publication":"Microprocessors and Microsystems"},{"language":[{"iso":"eng"}],"_id":"10613","publisher":"Paderborn University","user_id":"3118","author":[{"full_name":"Kaltschmidt, Christian","last_name":"Kaltschmidt","first_name":"Christian"}],"status":"public","title":"An AR-based Training and Assessment System for Myoelectrical Prosthetic Control","year":"2017","date_updated":"2022-01-06T06:50:47Z","date_created":"2019-07-10T09:25:11Z","department":[{"_id":"78"}],"type":"bachelorsthesis","citation":{"ama":"Kaltschmidt C. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University; 2017.","bibtex":"@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }","mla":"Kaltschmidt, Christian. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017.","chicago":"Kaltschmidt, Christian. <i>An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017.","short":"C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control, Paderborn University, 2017.","apa":"Kaltschmidt, C. (2017). <i>An AR-based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University.","ieee":"C. Kaltschmidt, <i>An AR-based Training and Assessment System for Myoelectrical Prosthetic Control</i>. Paderborn University, 2017."}},{"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:02:56Z","publication":"Design, Automation and Test in Europe (DATE)","citation":{"mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” <i>Design, Automation and Test in Europe (DATE)</i>, 2017, doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>.","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: <i>Design, Automation and Test in Europe (DATE)</i>. ; 2017. doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., &#38; Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In <i>Design, Automation and Test in Europe (DATE)</i>. <a href=\"https://doi.org/10.23919/DATE.2017.7927137\">https://doi.org/10.23919/DATE.2017.7927137</a>","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in <i>Design, Automation and Test in Europe (DATE)</i>, 2017.","short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017.","chicago":"Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens, and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” In <i>Design, Automation and Test in Europe (DATE)</i>, 2017. <a href=\"https://doi.org/10.23919/DATE.2017.7927137\">https://doi.org/10.23919/DATE.2017.7927137</a>."},"user_id":"3118","doi":"10.23919/DATE.2017.7927137","_id":"10630","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","year":"2017","title":"A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller","status":"public","author":[{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"full_name":"Thombansen, Georg","last_name":"Thombansen","first_name":"Georg"},{"first_name":"Linus Matthias","last_name":"Witschen","full_name":"Witschen, Linus Matthias","id":"49051"},{"last_name":"Wiens","first_name":"Alex","full_name":"Wiens, Alex"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}]},{"date_updated":"2022-01-06T06:50:49Z","author":[{"first_name":"Umair","last_name":"Riaz","full_name":"Riaz, Umair"}],"title":"Acceleration of Industrial Analytics Functions on a Platform FPGA","year":"2017","status":"public","user_id":"3118","language":[{"iso":"eng"}],"_id":"10666","publisher":"Paderborn University","citation":{"mla":"Riaz, Umair. <i>Acceleration of Industrial Analytics Functions on a Platform FPGA</i>. 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Cham: Springer . <a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">https://doi.org/10.1007/978-3-319-62569-0_8</a>","bibtex":"@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>}, booktitle={Communications in Computer and Information Science}, publisher={Springer }, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}, year={2017} }","ama":"Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: <i>Communications in Computer and Information Science</i>. Cham: Springer ; 2017. doi:<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>","mla":"Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” <i>Communications in Computer and Information Science</i>, Springer , 2017, doi:<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>."},"publication":"Communications in Computer and Information Science"},{"page":"112--122","_id":"222","publisher":"Elsevier","user_id":"477","ddc":["040"],"status":"public","has_accepted_license":"1","file_date_updated":"2018-03-21T10:36:08Z","citation":{"chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, 2016, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers &#38; Electrical Engineering (2016) 112--122.","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” <i>Computers &#38; Electrical Engineering</i>, pp. 112--122, 2016.","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>. 2016:112--122. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>}, journal={Computers &#38; Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, Elsevier, 2016, pp. 112--122, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>."},"project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"}],"language":[{"iso":"eng"}],"doi":"10.1016/j.compeleceng.2016.04.005","year":"2016","title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","author":[{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"},{"first_name":"Arne","last_name":"Bockhorn","full_name":"Bockhorn, Arne"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:55:29Z","file":[{"success":1,"content_type":"application/pdf","file_id":"1511","file_size":931048,"access_level":"closed","file_name":"222-1-s2.0-S0045790616300684-main.pdf","date_updated":"2018-03-21T10:36:08Z","relation":"main_file","date_created":"2018-03-21T10:36:08Z","creator":"florida"}],"date_created":"2017-10-17T12:41:35Z","type":"journal_article","department":[{"_id":"78"}],"publication":"Computers & Electrical Engineering","abstract":[{"lang":"eng","text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved."}]}]