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Cham: Springer ; 2017. doi:<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>"},"publication":"Communications in Computer and Information Science","department":[{"_id":"78"}],"type":"conference","place":"Cham","date_created":"2019-11-12T08:33:13Z","date_updated":"2022-01-06T06:52:10Z","publication_status":"published","author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"last_name":"Abdallah","first_name":"Riadh Ben","full_name":"Abdallah, Riadh Ben"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"publication_identifier":{"isbn":["9783319625683","9783319625690"],"issn":["1865-0929","1865-0937"]},"status":"public","year":"2017","title":"I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems","doi":"10.1007/978-3-319-62569-0_8","user_id":"398","publisher":"Springer ","_id":"14893","language":[{"iso":"eng"}]},{"has_accepted_license":"1","status":"public","user_id":"477","ddc":["040"],"publisher":"Elsevier","_id":"222","page":"112--122","project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"citation":{"mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, Elsevier, 2016, pp. 112--122, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>.","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>}, journal={Computers &#38; Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>. 2016:112--122. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” <i>Computers &#38; Electrical Engineering</i>, pp. 112--122, 2016.","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, 2016, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers &#38; Electrical Engineering (2016) 112--122."},"file_date_updated":"2018-03-21T10:36:08Z","date_updated":"2022-01-06T06:55:29Z","author":[{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"},{"full_name":"Bockhorn, Arne","first_name":"Arne","last_name":"Bockhorn"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","year":"2016","doi":"10.1016/j.compeleceng.2016.04.005","language":[{"iso":"eng"}],"abstract":[{"text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.","lang":"eng"}],"publication":"Computers & Electrical Engineering","department":[{"_id":"78"}],"type":"journal_article","date_created":"2017-10-17T12:41:35Z","file":[{"creator":"florida","date_created":"2018-03-21T10:36:08Z","file_name":"222-1-s2.0-S0045790616300684-main.pdf","access_level":"closed","file_size":931048,"relation":"main_file","date_updated":"2018-03-21T10:36:08Z","file_id":"1511","success":1,"content_type":"application/pdf"}]},{"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","citation":{"ieee":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. 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IEEE. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","ama":"Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2016. doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>","short":"A. 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IEEE, 2016. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>."},"extern":"1","date_created":"2018-11-23T15:00:28Z","type":"conference","department":[{"_id":"78"}],"status":"public","title":"FPGA-based acceleration of high density myoelectric signal processing","year":"2016","publication_identifier":{"isbn":["9781467394062"]},"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Witschen, Linus","last_name":"Witschen","first_name":"Linus"},{"full_name":"Thombansen, Georg","first_name":"Georg","last_name":"Thombansen"},{"full_name":"Kraus, Florian","first_name":"Florian","last_name":"Kraus","id":"14053"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T07:02:42Z","publication_status":"published","_id":"5812","language":[{"iso":"eng"}],"publisher":"IEEE","doi":"10.1109/reconfig.2015.7393312","user_id":"14053"},{"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T09:23:26Z","citation":{"ama":"Cedric Mertens J. <i>Sprint Diagnostic with RTK-GPS \\&#38; IMU Sensor Fusion</i>. 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Paderborn University.","ieee":"A. S. Nassery, <i>Implementation of Bilinear Pairings on Reconfigurable Hardware</i>. Paderborn University, 2016.","chicago":"Nassery, Abdul Sami. <i>Implementation of Bilinear Pairings on Reconfigurable Hardware</i>. Paderborn University, 2016.","short":"A.S. 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Paderborn University, 2016.","bibtex":"@book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }","ama":"Amin O. <i>Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method</i>. Paderborn University; 2016.","ieee":"O. Amin, <i>Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method</i>. Paderborn University, 2016.","apa":"Amin, O. (2016). <i>Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method</i>. Paderborn University.","short":"O. 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Adaptive playouts for online learning of policies during Monte Carlo Tree Search. <i>Journal Theoretical Computer Science</i>, <i>644</i>, 53–62. <a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">https://doi.org/10.1016/j.tcs.2016.06.029</a>","ieee":"T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” <i>Journal Theoretical Computer Science</i>, vol. 644, pp. 53–62, 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” <i>Journal Theoretical Computer Science</i> 644 (2016): 53–62. <a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">https://doi.org/10.1016/j.tcs.2016.06.029</a>.","short":"T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62.","ama":"Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. <i>Journal Theoretical Computer Science</i>. 2016;644:53-62. doi:<a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">10.1016/j.tcs.2016.06.029</a>","bibtex":"@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={<a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">10.1016/j.tcs.2016.06.029</a>}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }"},"date_created":"2019-07-10T11:14:43Z","type":"journal_article","department":[{"_id":"78"}]},{"supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"citation":{"ama":"Horstmann J. <i>Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs</i>. 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