[{"date_created":"2019-07-10T11:43:31Z","department":[{"_id":"78"}],"type":"mastersthesis","citation":{"bibtex":"@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }","ama":"Ibne Ashraf I. <i>Private/Shared Data Classification and Implementation for a Multi-Softcore Platform</i>. Paderborn University; 2016.","mla":"Ibne Ashraf, Ishraq. <i>Private/Shared Data Classification and Implementation for a Multi-Softcore Platform</i>. Paderborn University, 2016.","short":"I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform, Paderborn University, 2016.","chicago":"Ibne Ashraf, Ishraq. <i>Private/Shared Data Classification and Implementation for a Multi-Softcore Platform</i>. Paderborn University, 2016.","ieee":"I. Ibne Ashraf, <i>Private/Shared Data Classification and Implementation for a Multi-Softcore Platform</i>. Paderborn University, 2016.","apa":"Ibne Ashraf, I. (2016). <i>Private/Shared Data Classification and Implementation for a Multi-Softcore Platform</i>. Paderborn University."},"supervisor":[{"first_name":"Nam","last_name":"Ho","full_name":"Ho, Nam"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"_id":"10707","language":[{"iso":"eng"}],"publisher":"Paderborn University","user_id":"3118","author":[{"full_name":"Ibne Ashraf, Ishraq","last_name":"Ibne Ashraf","first_name":"Ishraq"}],"title":"Private/Shared Data Classification and Implementation for a Multi-Softcore Platform","status":"public","year":"2016","date_updated":"2022-01-06T06:50:50Z"},{"author":[{"full_name":"Meisner, Sebastian","last_name":"Meisner","first_name":"Sebastian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"title":"Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level","status":"public","year":"2016","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"_id":"10712","series_title":"ReConFig","page":"1-8","doi":"10.1109/ReConFig.2016.7857193","user_id":"3118","citation":{"short":"S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>, 1–8. ReConFig, 2016. <a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">https://doi.org/10.1109/ReConFig.2016.7857193</a>.","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on</i>, 2016, pp. 1–8.","apa":"Meisner, S., &#38; Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">https://doi.org/10.1109/ReConFig.2016.7857193</a>","bibtex":"@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }","ama":"Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>. ReConFig. ; 2016:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>, 2016, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>."},"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on","date_created":"2019-07-10T11:47:25Z","department":[{"_id":"78"}],"type":"conference"},{"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T12:05:20Z","citation":{"short":"M. Schmidt, Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung, Paderborn University, 2016.","chicago":"Schmidt, Marco. <i>Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung</i>. Paderborn University, 2016.","ieee":"M. Schmidt, <i>Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung</i>. Paderborn University, 2016.","apa":"Schmidt, M. (2016). <i>Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung</i>. Paderborn University.","bibtex":"@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }","ama":"Schmidt M. <i>Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung</i>. Paderborn University; 2016.","mla":"Schmidt, Marco. <i>Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung</i>. Paderborn University, 2016."},"user_id":"3118","language":[{"iso":"eng"}],"_id":"10755","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","year":"2016","title":"Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung","status":"public","author":[{"full_name":"Schmidt, Marco","first_name":"Marco","last_name":"Schmidt"}]},{"series_title":"Lecture Notes in Computer Science","_id":"10758","publisher":"Springer","user_id":"3118","volume":9597,"year":"2016","title":"Applications of Evolutionary Computation - 19th European Conference, EvoApplications","status":"public","author":[{"full_name":"Squillero, Giovanni","first_name":"Giovanni","last_name":"Squillero"},{"first_name":"Paolo","last_name":"Burelli","full_name":"Burelli, Paolo"},{"last_name":"M. Mora","first_name":"Antonio","full_name":"M. Mora, Antonio"},{"full_name":"Agapitos, Alexandros","last_name":"Agapitos","first_name":"Alexandros"},{"full_name":"S. Bush, William","last_name":"S. Bush","first_name":"William"},{"full_name":"Cagnoni, Stefano","first_name":"Stefano","last_name":"Cagnoni"},{"full_name":"Cotta, Carlos","last_name":"Cotta","first_name":"Carlos"},{"first_name":"Ivanoe","last_name":"De Falco","full_name":"De Falco, Ivanoe"},{"full_name":"Della Cioppa, Antonio","last_name":"Della Cioppa","first_name":"Antonio"},{"last_name":"Divina","first_name":"Federico","full_name":"Divina, Federico"},{"last_name":"Eiben","first_name":"A.E.","full_name":"Eiben, A.E."},{"full_name":"I. Esparcia-Alc{\\'a}zar, Anna","last_name":"I. Esparcia-Alc{\\'a}zar","first_name":"Anna"},{"last_name":"Fern{\\'a}ndez de Vega","first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"full_name":"Glette, Kyrre","first_name":"Kyrre","last_name":"Glette"},{"first_name":"Evert","last_name":"Haasdijk","full_name":"Haasdijk, Evert"},{"last_name":"Ignacio Hidalgo","first_name":"J.","full_name":"Ignacio Hidalgo, J."},{"full_name":"Kampouridis, Michael","last_name":"Kampouridis","first_name":"Michael"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Mavrovouniotis","first_name":"Michalis","full_name":"Mavrovouniotis, Michalis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"full_name":"Schaefer, Robert","last_name":"Schaefer","first_name":"Robert"},{"first_name":"Kevin","last_name":"Sim","full_name":"Sim, Kevin"},{"full_name":"Tarantino, Ernesto","last_name":"Tarantino","first_name":"Ernesto"},{"full_name":"Urquhart, Neil","last_name":"Urquhart","first_name":"Neil"},{"full_name":"Zhang (editors), Mengjie","last_name":"Zhang (editors)","first_name":"Mengjie"}],"date_updated":"2022-01-06T06:50:50Z","intvolume":"      9597","date_created":"2019-07-10T12:06:36Z","type":"book","department":[{"_id":"78"}],"citation":{"ama":"Squillero G, Burelli P, M. Mora A, et al. <i>Applications of Evolutionary Computation - 19th European Conference, EvoApplications</i>. Vol 9597. Springer; 2016.","short":"G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 19th European Conference, EvoApplications, Springer, 2016.","chicago":"Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. <i>Applications of Evolutionary Computation - 19th European Conference, EvoApplications</i>. Vol. 9597. Lecture Notes in Computer Science. Springer, 2016.","bibtex":"@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2016, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 19th European Conference, EvoApplications}, volume={9597}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2016}, collection={Lecture Notes in Computer Science} }","mla":"Squillero, Giovanni, et al. <i>Applications of Evolutionary Computation - 19th European Conference, EvoApplications</i>. Vol. 9597, Springer, 2016.","apa":"Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2016). <i>Applications of Evolutionary Computation - 19th European Conference, EvoApplications</i> (Vol. 9597). Springer.","ieee":"G. Squillero <i>et al.</i>, <i>Applications of Evolutionary Computation - 19th European Conference, EvoApplications</i>, vol. 9597. Springer, 2016."}},{"date_created":"2019-07-10T12:07:54Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 30th European Simulation and Modelling Conference (ESM)","citation":{"apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., &#38; Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","mla":"Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>. ; 2016.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }"},"language":[{"iso":"eng"}],"_id":"10766","user_id":"3118","title":"RCo-Design: New Visual Environment for Reconfigurable Embedded Systems","year":"2016","status":"public","author":[{"first_name":"Ines","last_name":"Ghribi","full_name":"Ghribi, Ines"},{"full_name":"Ben Abdallah, Riadh","last_name":"Ben Abdallah","first_name":"Riadh"},{"full_name":"Khalgui, Mohamed","last_name":"Khalgui","first_name":"Mohamed"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:50Z"},{"user_id":"3118","page":"185-195","_id":"10768","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","title":"New Co-design Methodology for Real-time Embedded Systems","year":"2016","status":"public","author":[{"first_name":"Ines","last_name":"Ghribi","full_name":"Ghribi, Ines"},{"full_name":"Ben Abdallah, Riadh","last_name":"Ben Abdallah","first_name":"Riadh"},{"last_name":"Khalgui","first_name":"Mohamed","full_name":"Khalgui, Mohamed"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T12:07:56Z","publication":"Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)","citation":{"ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in <i>Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)</i>, 2016, pp. 185–195.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., &#38; Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In <i>Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)</i> (pp. 185–195).","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In <i>Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)</i>, 185–95, 2016.","mla":"Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” <i>Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)</i>, 2016, pp. 185–95.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: <i>Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)</i>. ; 2016:185-195."}},{"extern":"1","citation":{"ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, vol. PP, no. 99, pp. 1–1, 2016.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &#38; De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, <i>PP</i>(99), 1–1. <a href=\"https://doi.org/10.1109/TCAD.2016.2547908\">https://doi.org/10.1109/TCAD.2016.2547908</a>","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1.","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i> PP, no. 99 (2016): 1–1. <a href=\"https://doi.org/10.1109/TCAD.2016.2547908\">https://doi.org/10.1109/TCAD.2016.2547908</a>.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/TCAD.2016.2547908\">10.1109/TCAD.2016.2547908</a>.","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={<a href=\"https://doi.org/10.1109/TCAD.2016.2547908\">10.1109/TCAD.2016.2547908</a>}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. 2016;PP(99):1-1. doi:<a href=\"https://doi.org/10.1109/TCAD.2016.2547908\">10.1109/TCAD.2016.2547908</a>"},"publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issue":"99","department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T12:08:14Z","date_updated":"2022-01-06T06:50:50Z","author":[{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","last_name":"Ghasemzadeh Mohammadi"},{"first_name":"Pierre-Emmanuel","last_name":"Gaillardon","full_name":"Gaillardon, Pierre-Emmanuel"},{"full_name":"De Micheli, Giovanni","last_name":"De Micheli","first_name":"Giovanni"}],"title":"Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation","status":"public","year":"2016","volume":"PP","user_id":"3118","doi":"10.1109/TCAD.2016.2547908","_id":"10769","publisher":"IEEE","language":[{"iso":"eng"}],"page":"1-1"},{"user_id":"3118","_id":"10781","language":[{"iso":"eng"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Hermansen","first_name":"Sven","full_name":"Hermansen, Sven"}],"status":"public","year":"2016","title":"Custom Memory Controller for ReconOS","department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2019-07-10T12:13:16Z","citation":{"bibtex":"@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }","ama":"Hermansen S. <i>Custom Memory Controller for ReconOS</i>. Paderborn University; 2016.","mla":"Hermansen, Sven. <i>Custom Memory Controller for ReconOS</i>. Paderborn University, 2016.","chicago":"Hermansen, Sven. <i>Custom Memory Controller for ReconOS</i>. Paderborn University, 2016.","short":"S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016.","ieee":"S. Hermansen, <i>Custom Memory Controller for ReconOS</i>. Paderborn University, 2016.","apa":"Hermansen, S. (2016). <i>Custom Memory Controller for ReconOS</i>. Paderborn University."}},{"citation":{"mla":"Lewis, Peter R., et al., editors. <i>Self-Aware Computing Systems: An Engineering Approach</i>. Springer, 2016, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0\">10.1007/978-3-319-39675-0</a>.","ama":"Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. <i>Self-Aware Computing Systems: An Engineering Approach</i>. Cham: Springer; 2016. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0\">10.1007/978-3-319-39675-0</a>","bibtex":"@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0\">10.1007/978-3-319-39675-0</a>}, publisher={Springer}, year={2016} }","apa":"Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., &#38; Yao, X. (Eds.). (2016). <i>Self-aware Computing Systems: An Engineering Approach</i>. Cham: Springer. <a href=\"https://doi.org/10.1007/978-3-319-39675-0\">https://doi.org/10.1007/978-3-319-39675-0</a>","ieee":"P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., <i>Self-aware Computing Systems: An Engineering Approach</i>. Cham: Springer, 2016.","short":"P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016.","chicago":"Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. <i>Self-Aware Computing Systems: An Engineering Approach</i>. Cham: Springer, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0\">https://doi.org/10.1007/978-3-319-39675-0</a>."},"abstract":[{"lang":"eng","text":"Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering."}],"place":"Cham","date_created":"2019-08-27T13:39:43Z","department":[{"_id":"78"}],"type":"book_editor","publication_identifier":{"issn":["1619-7127"],"isbn":["9783319396743","9783319396750"]},"year":"2016","title":"Self-aware Computing Systems: An Engineering Approach","status":"public","date_updated":"2022-01-06T06:51:27Z","publication_status":"published","_id":"12972","language":[{"iso":"eng"}],"publisher":"Springer","editor":[{"last_name":"Lewis","first_name":"Peter R.","full_name":"Lewis, Peter R."},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Rinner, Bernhard","last_name":"Rinner","first_name":"Bernhard"},{"first_name":"Jim","last_name":"Tørresen","full_name":"Tørresen, Jim"},{"first_name":"Xin","last_name":"Yao","full_name":"Yao, Xin"}],"doi":"10.1007/978-3-319-39675-0","user_id":"398"},{"doi":"10.1109/reconfig.2015.7393312","user_id":"49051","publisher":"IEEE","_id":"15873","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:52:38Z","publication_status":"published","title":"FPGA-based acceleration of high density myoelectric signal processing","year":"2016","status":"public","conference":{"name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","location":"Mexiko City, Mexiko"},"publication_identifier":{"isbn":["9781467394062"]},"author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","id":"49051"},{"first_name":"Georg","last_name":"Thombansen","full_name":"Thombansen, Georg"},{"full_name":"Kraus, Florian","first_name":"Florian","last_name":"Kraus"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"type":"conference","keyword":["Electromyography","Feature extraction","Delays","Hardware  Pattern recognition","Prosthetics","High definition video"],"department":[{"_id":"78"}],"date_created":"2020-02-11T07:48:56Z","publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","citation":{"apa":"Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., &#38; Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. Mexiko City, Mexiko: IEEE. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>","ieee":"A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, Mexiko City, Mexiko, 2016.","short":"A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","chicago":"Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE, 2016. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>.","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2016, doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>.","ama":"Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2016. doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }"}},{"date_created":"2019-09-09T09:01:09Z","type":"conference","department":[{"_id":"78"}],"publication":"Computer and Games","citation":{"ieee":"T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in <i>Computer and Games</i>, 2016.","apa":"Graf, T., &#38; Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In <i>Computer and Games</i>.","short":"T. Graf, M. Platzner, in: Computer and Games, 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In <i>Computer and Games</i>, 2016.","mla":"Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” <i>Computer and Games</i>, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","ama":"Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: <i>Computer and Games</i>. ; 2016."},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"language":[{"iso":"eng"}],"_id":"13151","user_id":"398","year":"2016","status":"public","title":"Using Deep Convolutional Neural Networks in Monte Carlo Tree Search","author":[{"full_name":"Graf, Tobias","last_name":"Graf","first_name":"Tobias"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:51:29Z"},{"author":[{"full_name":"Graf, Tobias","last_name":"Graf","first_name":"Tobias"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"year":"2016","title":"Monte-Carlo Simulation Balancing Revisited","status":"public","date_updated":"2022-01-06T06:51:29Z","_id":"13152","language":[{"iso":"eng"}],"user_id":"398","citation":{"mla":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” <i>IEEE Computational Intelligence and Games</i>, 2016.","bibtex":"@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }","ama":"Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: <i>IEEE Computational Intelligence and Games</i>. ; 2016.","ieee":"T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in <i>IEEE Computational Intelligence and Games</i>, 2016.","apa":"Graf, T., &#38; Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In <i>IEEE Computational Intelligence and Games</i>.","chicago":"Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In <i>IEEE Computational Intelligence and Games</i>, 2016.","short":"T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016."},"publication":"IEEE Computational Intelligence and Games","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2019-09-09T09:06:39Z","department":[{"_id":"78"}],"type":"conference"},{"user_id":"477","ddc":["040"],"_id":"132","page":"1--8","has_accepted_license":"1","status":"public","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"chicago":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>, 1--8, 2016. <a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">https://doi.org/10.1109/ReCoSoC.2016.7533910</a>.","short":"T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","ieee":"T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)</i>, 2016, pp. 1--8.","apa":"Wiersema, T., &#38; Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)</i> (pp. 1--8). <a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">https://doi.org/10.1109/ReCoSoC.2016.7533910</a>","bibtex":"@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }","ama":"Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>. ; 2016:1--8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>","mla":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>, 2016, pp. 1--8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>."},"file_date_updated":"2018-03-21T13:02:30Z","doi":"10.1109/ReCoSoC.2016.7533910","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:30Z","author":[{"full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias","id":"3118"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware","year":"2016","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:41:17Z","file":[{"file_id":"1562","success":1,"content_type":"application/pdf","file_name":"132-07533910.pdf","file_size":911171,"access_level":"closed","relation":"main_file","date_updated":"2018-03-21T13:02:30Z","date_created":"2018-03-21T13:02:30Z","creator":"florida"}],"abstract":[{"lang":"eng","text":"Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module."}],"publication":"Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)"},{"project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"quality_controlled":"1","citation":{"ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. <i>FPGAs for Software Programmers</i>. Springer International Publishing; 2016:227-244. doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” <i>FPGAs for Software Programmers</i>, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>.","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In <i>FPGAs for Software Programmers</i>, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., &#38; Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, &#38; D. Ziener (Eds.), <i>FPGAs for Software Programmers</i> (pp. 227–244). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in <i>FPGAs for Software Programmers</i>, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244."},"place":"Cham","status":"public","editor":[{"first_name":"Dirk","last_name":"Koch","full_name":"Koch, Dirk"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"full_name":"Ziener, Daniel","last_name":"Ziener","first_name":"Daniel"}],"user_id":"15278","_id":"29","publisher":"Springer International Publishing","page":"227-244","abstract":[{"lang":"eng","text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems."}],"publication":"FPGAs for Software Programmers","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"book_chapter","date_created":"2017-07-26T15:07:06Z","publication_status":"published","date_updated":"2023-09-26T13:25:38Z","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","id":"16153"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"}],"year":"2016","title":"ReconOS","doi":"10.1007/978-3-319-26408-0_13","language":[{"iso":"eng"}]},{"abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"publication":"Self-aware Computing Systems","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"type":"book_chapter","date_created":"2017-10-17T12:41:22Z","file":[{"creator":"aloesch","date_created":"2018-11-14T13:20:32Z","file_size":833054,"access_level":"closed","file_name":"chapter8.pdf","date_updated":"2018-11-14T13:20:32Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"5613"}],"date_updated":"2023-09-26T13:27:44Z","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"full_name":"Lösch, Achim","last_name":"Lösch","first_name":"Achim","id":"43646"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"Self-aware Compute Nodes","year":"2016","doi":"10.1007/978-3-319-39675-0_8","series_title":"Natural Computing Series (NCS)","language":[{"iso":"eng"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"quality_controlled":"1","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in <i>Self-aware Computing Systems</i>, Cham: Springer International Publishing, 2016, pp. 145–165.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2016). Self-aware Compute Nodes. In <i>Self-aware Computing Systems</i> (pp. 145–165). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In <i>Self-Aware Computing Systems</i>, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>.","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” <i>Self-Aware Computing Systems</i>, Springer International Publishing, 2016, pp. 145–65, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: <i>Self-Aware Computing Systems</i>. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>"},"file_date_updated":"2018-11-14T13:20:32Z","place":"Cham","has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","publisher":"Springer International Publishing","_id":"156","page":"145-165"},{"language":[{"iso":"eng"}],"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","year":"2016","author":[{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias","id":"3145"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2023-09-26T13:27:00Z","file":[{"date_created":"2018-03-21T12:41:55Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1541","access_level":"closed","file_size":261356,"file_name":"168-07459438.pdf","date_updated":"2018-03-21T12:41:55Z","relation":"main_file"}],"date_created":"2017-10-17T12:41:24Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"page":"912-917","publisher":"EDA Consortium / IEEE","_id":"168","ddc":["040"],"user_id":"15278","status":"public","has_accepted_license":"1","file_date_updated":"2018-03-21T12:41:55Z","citation":{"mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, EDA Consortium / IEEE, 2016, pp. 912–17.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., &#38; Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 2016, pp. 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. EDA Consortium / IEEE; 2016:912-917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–17. EDA Consortium / IEEE, 2016.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }"},"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}]},{"author":[{"id":"3118","last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"last_name":"Wu","first_name":"Sen","full_name":"Wu, Sen"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"year":"2015","title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach","date_updated":"2022-01-06T06:57:30Z","series_title":"LNCS","language":[{"iso":"eng"}],"doi":"10.1007/978-3-319-16214-0_32","publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","abstract":[{"lang":"eng","text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level."}],"date_created":"2017-10-17T12:41:44Z","file":[{"date_created":"2018-03-21T09:32:42Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1477","file_size":344309,"access_level":"closed","file_name":"269-paper_53.pdf","date_updated":"2018-03-21T09:32:42Z","relation":"main_file"}],"department":[{"_id":"78"}],"type":"conference","status":"public","has_accepted_license":"1","_id":"269","page":"365--372","ddc":["040"],"user_id":"477","citation":{"ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 2015, pp. 365--372.","apa":"Wiersema, T., Wu, S., &#38; Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i> (pp. 365--372). <a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">https://doi.org/10.1007/978-3-319-16214-0_32</a>","short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 365--372. LNCS, 2015. <a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">https://doi.org/10.1007/978-3-319-16214-0_32</a>.","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 2015, pp. 365--372, doi:<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>.","bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }","ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>. LNCS. ; 2015:365--372. doi:<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>"},"file_date_updated":"2018-03-21T09:32:42Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}]},{"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2018-06-26T14:06:07Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"}],"supervisor":[{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"citation":{"ieee":"C. Knorr, <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","apa":"Knorr, C. (2015). <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn.","short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","chicago":"Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","mla":"Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","ama":"Knorr C. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn; 2015."},"user_id":"477","_id":"3364","publisher":"Universität Paderborn","language":[{"iso":"ger"}],"date_updated":"2022-01-06T06:59:13Z","title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","status":"public","year":"2015","author":[{"full_name":"Knorr, Christoph","last_name":"Knorr","first_name":"Christoph"}]},{"intvolume":"        48","date_updated":"2022-01-06T06:53:19Z","author":[{"first_name":"Jim","last_name":"Torresen","full_name":"Torresen, Jim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Xin","last_name":"Yao","full_name":"Yao, Xin"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","year":"2015","doi":"10.1109/MC.2015.205","language":[{"iso":"eng"}],"issue":"7","publication":"IEEE Computer","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["self-awareness","self-expression"],"type":"journal_article","date_created":"2018-03-23T14:06:12Z","file":[{"creator":"ups","date_created":"2018-11-02T15:47:45Z","access_level":"closed","file_size":5605009,"file_name":"07163237.pdf","date_updated":"2018-11-02T15:47:45Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"5313"}],"has_accepted_license":"1","status":"public","volume":48,"ddc":["000"],"user_id":"16153","_id":"1772","publisher":"IEEE Computer Society","page":"18-20","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"citation":{"chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i> 48, no. 7 (2015): 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","apa":"Torresen, J., Plessl, C., &#38; Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>, <i>48</i>(7), 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” <i>IEEE Computer</i>, vol. 48, no. 7, pp. 18–20, 2015.","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>. 2015;48(7):18-20. doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i>, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>."},"file_date_updated":"2018-11-02T15:47:45Z"},{"_id":"10615","language":[{"iso":"eng"}],"publisher":"Paderborn University","user_id":"3118","author":[{"full_name":"Ahmed, Abdullah Fathi","last_name":"Ahmed","first_name":"Abdullah Fathi"}],"title":"Self-Optimizing Organic Cache","year":"2015","status":"public","date_updated":"2022-01-06T06:50:47Z","date_created":"2019-07-10T09:25:13Z","department":[{"_id":"78"}],"type":"mastersthesis","citation":{"ieee":"A. F. Ahmed, <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","apa":"Ahmed, A. F. (2015). <i>Self-Optimizing Organic Cache</i>. Paderborn University.","chicago":"Ahmed, Abdullah Fathi. <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.","mla":"Ahmed, Abdullah Fathi. <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }","ama":"Ahmed AF. <i>Self-Optimizing Organic Cache</i>. Paderborn University; 2015."},"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}]}]