[{"date_created":"2017-10-17T12:41:17Z","author":[{"last_name":"Wiersema","id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2022-01-06T06:51:30Z","doi":"10.1109/ReCoSoC.2016.7533910","title":"Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware","has_accepted_license":"1","page":"1--8","citation":{"ama":"Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>. ; 2016:1--8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>","ieee":"T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)</i>, 2016, pp. 1--8.","chicago":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>, 1--8, 2016. <a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">https://doi.org/10.1109/ReCoSoC.2016.7533910</a>.","apa":"Wiersema, T., &#38; Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)</i> (pp. 1--8). <a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">https://doi.org/10.1109/ReCoSoC.2016.7533910</a>","bibtex":"@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }","short":"T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.","mla":"Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” <i>Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016)</i>, 2016, pp. 1--8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2016.7533910\">10.1109/ReCoSoC.2016.7533910</a>."},"year":"2016","department":[{"_id":"78"}],"user_id":"477","_id":"132","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T13:02:30Z","ddc":["040"],"publication":"Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)","type":"conference","status":"public","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":911171,"access_level":"closed","file_id":"1562","file_name":"132-07533910.pdf","date_updated":"2018-03-21T13:02:30Z","date_created":"2018-03-21T13:02:30Z","creator":"florida"}],"abstract":[{"lang":"eng","text":"Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module."}]},{"project":[{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"29","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"editor":[{"full_name":"Koch, Dirk","last_name":"Koch","first_name":"Dirk"},{"first_name":"Frank","last_name":"Hannig","full_name":"Hannig, Frank"},{"full_name":"Ziener, Daniel","last_name":"Ziener","first_name":"Daniel"}],"status":"public","type":"book_chapter","doi":"10.1007/978-3-319-26408-0_13","date_updated":"2023-09-26T13:25:38Z","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"place":"Cham","citation":{"ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. <i>FPGAs for Software Programmers</i>. Springer International Publishing; 2016:227-244. doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in <i>FPGAs for Software Programmers</i>, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In <i>FPGAs for Software Programmers</i>, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., &#38; Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, &#38; D. Ziener (Eds.), <i>FPGAs for Software Programmers</i> (pp. 227–244). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” <i>FPGAs for Software Programmers</i>, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244."},"page":"227-244","publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems."}],"publication":"FPGAs for Software Programmers","title":"ReconOS","publisher":"Springer International Publishing","date_created":"2017-07-26T15:07:06Z","year":"2016","quality_controlled":"1"},{"publication":"Self-aware Computing Systems","abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"file":[{"creator":"aloesch","date_created":"2018-11-14T13:20:32Z","date_updated":"2018-11-14T13:20:32Z","access_level":"closed","file_id":"5613","file_name":"chapter8.pdf","file_size":833054,"content_type":"application/pdf","relation":"main_file","success":1}],"ddc":["040"],"language":[{"iso":"eng"}],"quality_controlled":"1","year":"2016","publisher":"Springer International Publishing","date_created":"2017-10-17T12:41:22Z","title":"Self-aware Compute Nodes","type":"book_chapter","status":"public","_id":"156","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"user_id":"15278","series_title":"Natural Computing Series (NCS)","file_date_updated":"2018-11-14T13:20:32Z","has_accepted_license":"1","place":"Cham","page":"145-165","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in <i>Self-aware Computing Systems</i>, Cham: Springer International Publishing, 2016, pp. 145–165.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In <i>Self-Aware Computing Systems</i>, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: <i>Self-Aware Computing Systems</i>. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2016). Self-aware Compute Nodes. In <i>Self-aware Computing Systems</i> (pp. 145–165). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” <i>Self-Aware Computing Systems</i>, Springer International Publishing, 2016, pp. 145–65, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>."},"date_updated":"2023-09-26T13:27:44Z","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Lösch, Achim","id":"43646","last_name":"Lösch","first_name":"Achim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"doi":"10.1007/978-3-319-39675-0_8"},{"date_created":"2017-10-17T12:41:24Z","publisher":"EDA Consortium / IEEE","title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","quality_controlled":"1","year":"2016","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file":[{"date_created":"2018-03-21T12:41:55Z","creator":"florida","date_updated":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","access_level":"closed","file_id":"1541","file_size":261356,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"author":[{"full_name":"Lösch, Achim","id":"43646","last_name":"Lösch","first_name":"Achim"},{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:27:00Z","has_accepted_license":"1","citation":{"apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., &#38; Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, EDA Consortium / IEEE, 2016, pp. 912–17.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 2016, pp. 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–17. EDA Consortium / IEEE, 2016.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. EDA Consortium / IEEE; 2016:912-917."},"page":"912-917","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30","grant_number":"01|H11004A"}],"_id":"168","file_date_updated":"2018-03-21T12:41:55Z","type":"conference","status":"public"},{"has_accepted_license":"1","page":"365--372","citation":{"ama":"Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>. LNCS. ; 2015:365--372. doi:<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>","chicago":"Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 365--372. LNCS, 2015. <a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">https://doi.org/10.1007/978-3-319-16214-0_32</a>.","ieee":"T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 2015, pp. 365--372.","apa":"Wiersema, T., Wu, S., &#38; Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i> (pp. 365--372). <a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">https://doi.org/10.1007/978-3-319-16214-0_32</a>","bibtex":"@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }","short":"T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.","mla":"Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” <i>Proceedings of the International Symposium in Reconfigurable Computing (ARC)</i>, 2015, pp. 365--372, doi:<a href=\"https://doi.org/10.1007/978-3-319-16214-0_32\">10.1007/978-3-319-16214-0_32</a>."},"author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Sen","full_name":"Wu, Sen","last_name":"Wu"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2022-01-06T06:57:30Z","doi":"10.1007/978-3-319-16214-0_32","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"477","series_title":"LNCS","_id":"269","project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"3","name":"SFB 901 - Project Area B"}],"file_date_updated":"2018-03-21T09:32:42Z","year":"2015","date_created":"2017-10-17T12:41:44Z","title":"On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach","publication":"Proceedings of the International Symposium in Reconfigurable Computing (ARC)","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T09:32:42Z","creator":"florida","date_created":"2018-03-21T09:32:42Z","file_size":344309,"access_level":"closed","file_id":"1477","file_name":"269-paper_53.pdf"}],"abstract":[{"text":"Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["040"]},{"citation":{"apa":"Knorr, C. (2015). <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn.","bibtex":"@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }","mla":"Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","short":"C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015.","chicago":"Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","ieee":"C. Knorr, <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn, 2015.","ama":"Knorr C. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>. Universität Paderborn; 2015."},"year":"2015","title":"Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten","date_created":"2018-06-26T14:06:07Z","author":[{"full_name":"Knorr, Christoph","last_name":"Knorr","first_name":"Christoph"}],"supervisor":[{"first_name":"Achim","last_name":"Lösch","id":"43646","full_name":"Lösch, Achim"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T06:59:13Z","status":"public","type":"bachelorsthesis","language":[{"iso":"ger"}],"user_id":"477","department":[{"_id":"78"}],"project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"3364"},{"status":"public","type":"journal_article","file_date_updated":"2018-11-02T15:47:45Z","user_id":"16153","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"1772","citation":{"bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i>, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>.","apa":"Torresen, J., Plessl, C., &#38; Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>, <i>48</i>(7), 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>. 2015;48(7):18-20. doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” <i>IEEE Computer</i>, vol. 48, no. 7, pp. 18–20, 2015.","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i> 48, no. 7 (2015): 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>."},"page":"18-20","intvolume":"        48","has_accepted_license":"1","doi":"10.1109/MC.2015.205","author":[{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Yao, Xin","last_name":"Yao","first_name":"Xin"}],"volume":48,"date_updated":"2022-01-06T06:53:19Z","file":[{"date_updated":"2018-11-02T15:47:45Z","date_created":"2018-11-02T15:47:45Z","creator":"ups","file_size":5605009,"file_name":"07163237.pdf","access_level":"closed","file_id":"5313","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"IEEE Computer","language":[{"iso":"eng"}],"ddc":["000"],"keyword":["self-awareness","self-expression"],"year":"2015","issue":"7","title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","date_created":"2018-03-23T14:06:12Z","publisher":"IEEE Computer Society"},{"date_updated":"2022-01-06T06:50:47Z","publisher":"Paderborn University","supervisor":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"}],"author":[{"last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi","first_name":"Abdullah Fathi"}],"date_created":"2019-07-10T09:25:13Z","title":"Self-Optimizing Organic Cache","year":"2015","citation":{"ama":"Ahmed AF. <i>Self-Optimizing Organic Cache</i>. Paderborn University; 2015.","chicago":"Ahmed, Abdullah Fathi. <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","ieee":"A. F. Ahmed, <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","apa":"Ahmed, A. F. (2015). <i>Self-Optimizing Organic Cache</i>. Paderborn University.","bibtex":"@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }","mla":"Ahmed, Abdullah Fathi. <i>Self-Optimizing Organic Cache</i>. Paderborn University, 2015.","short":"A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015."},"_id":"10615","user_id":"3118","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"},{"type":"dissertation","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"status":"public","_id":"10624","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"user_id":"3118","language":[{"iso":"eng"}],"publication_identifier":{"isbn":["978-3-8325-4155-2"]},"year":"2015","place":"Berlin","page":"183","citation":{"short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","mla":"Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH.","chicago":"Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.","ieee":"T. Beisel, <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.","ama":"Beisel T. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH; 2015."},"date_updated":"2022-01-06T06:50:48Z","publisher":"Logos Verlag Berlin GmbH","author":[{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"}],"date_created":"2019-07-10T09:36:58Z","supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing"},{"type":"mastersthesis","status":"public","_id":"10668","department":[{"_id":"78"}],"user_id":"3118","language":[{"iso":"eng"}],"year":"2015","citation":{"ama":"Hangmann H. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University; 2015.","chicago":"Hangmann, Hendrik. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015.","ieee":"H. Hangmann, <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015.","apa":"Hangmann, H. (2015). <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University.","bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","mla":"Hangmann, Hendrik. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015.","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015."},"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","author":[{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"}],"date_created":"2019-07-10T11:15:13Z","supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"title":"Evolution of Heat Flow Prediction Models for FPGA Devices"},{"status":"public","type":"mastersthesis","language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10671","citation":{"short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015.","mla":"Haupt, Christian. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015.","bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }","apa":"Haupt, C. (2015). <i>Computer Vision basierte Klassifikation von HD EMG Signalen</i>. Paderborn University.","ama":"Haupt C. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University; 2015.","chicago":"Haupt, Christian. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015.","ieee":"C. Haupt, <i>Computer Vision basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015."},"year":"2015","title":"Computer Vision basierte Klassifikation von HD EMG Signalen","date_created":"2019-07-10T11:17:57Z","supervisor":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"}],"author":[{"first_name":"Christian","last_name":"Haupt","full_name":"Haupt, Christian"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z"},{"doi":"10.1109/AHS.2015.7231178","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","date_created":"2019-07-10T11:18:00Z","author":[{"first_name":"Nam","last_name":"Ho","full_name":"Ho, Nam"},{"full_name":"Ahmed, Abdullah Fathi","last_name":"Ahmed","first_name":"Abdullah Fathi"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2022-01-06T06:50:49Z","page":"1-7","citation":{"short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>.","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. 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ACM.","mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” <i>Genetic and Evolutionary Computation (GECCO)</i>, ACM, 2015, pp. 409–16.","bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }","short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: <i>Genetic and Evolutionary Computation (GECCO)</i>. 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