[{"date_created":"2019-07-10T09:36:58Z","place":"Berlin","type":"dissertation","department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"citation":{"mla":"Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Logos Verlag Berlin GmbH, 2015.","ama":"Beisel T. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH; 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","apa":"Beisel, T. (2015). <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH.","ieee":"T. Beisel, <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.","chicago":"Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015."},"supervisor":[{"full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","id":"16153"}],"abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30","grant_number":"01|H11004"}],"page":"183","language":[{"iso":"eng"}],"_id":"10624","publisher":"Logos Verlag Berlin GmbH","user_id":"3118","status":"public","year":"2015","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","publication_identifier":{"isbn":["978-3-8325-4155-2"]},"author":[{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"}],"date_updated":"2022-01-06T06:50:48Z"},{"user_id":"3118","_id":"10668","language":[{"iso":"eng"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","year":"2015","status":"public","title":"Evolution of Heat Flow Prediction Models for FPGA Devices","author":[{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"}],"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:15:13Z","supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"citation":{"chicago":"Hangmann, Hendrik. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015.","short":"H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015.","apa":"Hangmann, H. (2015). <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University.","ieee":"H. Hangmann, <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015.","ama":"Hangmann H. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University; 2015.","bibtex":"@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }","mla":"Hangmann, Hendrik. <i>Evolution of Heat Flow Prediction Models for FPGA Devices</i>. Paderborn University, 2015."}},{"status":"public","year":"2015","title":"Computer Vision basierte Klassifikation von HD EMG Signalen","author":[{"full_name":"Haupt, Christian","last_name":"Haupt","first_name":"Christian"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"Paderborn University","_id":"10671","language":[{"iso":"eng"}],"user_id":"3118","supervisor":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"}],"citation":{"ama":"Haupt C. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University; 2015.","bibtex":"@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }","mla":"Haupt, Christian. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015.","chicago":"Haupt, Christian. <i>Computer Vision Basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015.","short":"C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015.","apa":"Haupt, C. (2015). <i>Computer Vision basierte Klassifikation von HD EMG Signalen</i>. Paderborn University.","ieee":"C. Haupt, <i>Computer Vision basierte Klassifikation von HD EMG Signalen</i>. Paderborn University, 2015."},"date_created":"2019-07-10T11:17:57Z","type":"mastersthesis","department":[{"_id":"78"}]},{"project":[{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","citation":{"ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>.","short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7."},"type":"conference","keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"department":[{"_id":"78"}],"date_created":"2019-07-10T11:18:00Z","date_updated":"2022-01-06T06:50:49Z","status":"public","year":"2015","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"first_name":"Abdullah Fathi","last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"user_id":"3118","doi":"10.1109/AHS.2015.7231178","page":"1-7","language":[{"iso":"eng"}],"_id":"10673"},{"page":"409-416","publisher":"ACM","_id":"10693","user_id":"3118","title":"Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing","status":"public","year":"2015","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"full_name":"Shen, Cong","last_name":"Shen","first_name":"Cong"}],"date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:30:00Z","type":"conference","department":[{"_id":"78"}],"publication":"Genetic and Evolutionary Computation (GECCO)","citation":{"mla":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” <i>Genetic and Evolutionary Computation (GECCO)</i>, ACM, 2015, pp. 409–16.","bibtex":"@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }","ama":"Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: <i>Genetic and Evolutionary Computation (GECCO)</i>. ACM; 2015:409-416.","ieee":"P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in <i>Genetic and Evolutionary Computation (GECCO)</i>, 2015, pp. 409–416.","apa":"Kaufmann, P., &#38; Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In <i>Genetic and Evolutionary Computation (GECCO)</i> (pp. 409–416). ACM.","short":"P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.","chicago":"Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In <i>Genetic and Evolutionary Computation (GECCO)</i>, 409–16. ACM, 2015."}},{"date_created":"2019-07-10T11:47:24Z","type":"conference","department":[{"_id":"78"}],"publication":"Field Programmable Technology (FPT), 2015 International Conference on","citation":{"mla":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” <i>Field Programmable Technology (FPT), 2015 International Conference On</i>, 2015, pp. 212–15, doi:<a href=\"https://doi.org/10.1109/FPT.2015.7393153\">10.1109/FPT.2015.7393153</a>.","bibtex":"@inproceedings{Meisner_Platzner_2015, series={FPT}, title={Comparison of thread signatures for error detection in hybrid multi-cores}, DOI={<a href=\"https://doi.org/10.1109/FPT.2015.7393153\">10.1109/FPT.2015.7393153</a>}, booktitle={Field Programmable Technology (FPT), 2015 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2015}, pages={212–215}, collection={FPT} }","ama":"Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: <i>Field Programmable Technology (FPT), 2015 International Conference On</i>. FPT. ; 2015:212-215. doi:<a href=\"https://doi.org/10.1109/FPT.2015.7393153\">10.1109/FPT.2015.7393153</a>","ieee":"S. Meisner and M. Platzner, “Comparison of thread signatures for error detection in hybrid multi-cores,” in <i>Field Programmable Technology (FPT), 2015 International Conference on</i>, 2015, pp. 212–215.","apa":"Meisner, S., &#38; Platzner, M. (2015). Comparison of thread signatures for error detection in hybrid multi-cores. In <i>Field Programmable Technology (FPT), 2015 International Conference on</i> (pp. 212–215). <a href=\"https://doi.org/10.1109/FPT.2015.7393153\">https://doi.org/10.1109/FPT.2015.7393153</a>","chicago":"Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” In <i>Field Programmable Technology (FPT), 2015 International Conference On</i>, 212–15. FPT, 2015. <a href=\"https://doi.org/10.1109/FPT.2015.7393153\">https://doi.org/10.1109/FPT.2015.7393153</a>.","short":"S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215."},"page":"212-215","_id":"10711","series_title":"FPT","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2015.7393153","user_id":"3118","status":"public","year":"2015","title":"Comparison of thread signatures for error detection in hybrid multi-cores","author":[{"full_name":"Meisner, Sebastian","last_name":"Meisner","first_name":"Sebastian"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:50:50Z"},{"date_created":"2019-07-10T11:48:25Z","department":[{"_id":"78"}],"type":"bachelorsthesis","citation":{"ieee":"R. Meißner, <i>Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs</i>. Universität Paderborn, 2015.","apa":"Meißner, R. (2015). <i>Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs</i>. Universität Paderborn.","mla":"Meißner, Roland. <i>Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs</i>. Universität Paderborn, 2015.","bibtex":"@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }","ama":"Meißner R. <i>Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs</i>. Universität Paderborn; 2015.","short":"R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs, Universität Paderborn, 2015.","chicago":"Meißner, Roland. <i>Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs</i>. Universität Paderborn, 2015."},"supervisor":[{"last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118"}],"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"}],"publisher":"Universität Paderborn","_id":"10714","language":[{"iso":"eng"}],"user_id":"477","author":[{"full_name":"Meißner, Roland","last_name":"Meißner","first_name":"Roland"}],"title":"Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs","year":"2015","status":"public","date_updated":"2022-01-06T06:50:50Z"},{"author":[{"last_name":"Posewsky","first_name":"Thorbjörn","full_name":"Posewsky, Thorbjörn"}],"status":"public","title":"Acceleration of Artificial Neural Networks on a Zynq Platform","year":"2015","date_updated":"2022-01-06T06:50:50Z","publisher":"Paderborn University","_id":"10726","language":[{"iso":"eng"}],"user_id":"3118","citation":{"apa":"Posewsky, T. (2015). <i>Acceleration of Artificial Neural Networks on a Zynq Platform</i>. Paderborn University.","mla":"Posewsky, Thorbjörn. <i>Acceleration of Artificial Neural Networks on a Zynq Platform</i>. Paderborn University, 2015.","ieee":"T. Posewsky, <i>Acceleration of Artificial Neural Networks on a Zynq Platform</i>. Paderborn University, 2015.","chicago":"Posewsky, Thorbjörn. <i>Acceleration of Artificial Neural Networks on a Zynq Platform</i>. Paderborn University, 2015.","short":"T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform, Paderborn University, 2015.","ama":"Posewsky T. <i>Acceleration of Artificial Neural Networks on a Zynq Platform</i>. Paderborn University; 2015.","bibtex":"@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }"},"supervisor":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"}],"date_created":"2019-07-10T11:54:44Z","department":[{"_id":"78"}],"type":"mastersthesis"},{"date_created":"2019-07-10T12:06:35Z","place":"Copenhagen, Denmark","department":[{"_id":"78"}],"type":"book","citation":{"ieee":"A. M. Mora <i>et al.</i>, <i>Applications of Evolutionary Computation - 18th European Conference, EvoApplications</i>, vol. 9028. Copenhagen, Denmark: Springer, 2015.","apa":"M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2015). <i>Applications of Evolutionary Computation - 18th European Conference, EvoApplications</i> (Vol. 9028). Copenhagen, Denmark: Springer.","chicago":"M. Mora, Antonio, Giovanni Squillero, Alexandros Agapitos, Paolo Burelli, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. <i>Applications of Evolutionary Computation - 18th European Conference, EvoApplications</i>. Vol. 9028. Lecture Notes in Computer Science. Copenhagen, Denmark: Springer, 2015.","short":"A. M. Mora, G. Squillero, A. Agapitos, P. Burelli, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\\’a}zar, F. Fern{\\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 18th European Conference, EvoApplications, Springer, Copenhagen, Denmark, 2015.","mla":"M. Mora, Antonio, et al. <i>Applications of Evolutionary Computation - 18th European Conference, EvoApplications</i>. Vol. 9028, Springer, 2015.","bibtex":"@book{M. Mora_Squillero_Agapitos_Burelli_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2015, place={Copenhagen, Denmark}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 18th European Conference, EvoApplications}, volume={9028}, publisher={Springer}, author={M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2015}, collection={Lecture Notes in Computer Science} }","ama":"M. Mora A, Squillero G, Agapitos A, et al. <i>Applications of Evolutionary Computation - 18th European Conference, EvoApplications</i>. Vol 9028. Copenhagen, Denmark: Springer; 2015."},"series_title":"Lecture Notes in Computer Science","_id":"10757","publisher":"Springer","volume":9028,"user_id":"3118","author":[{"full_name":"M. Mora, Antonio","last_name":"M. Mora","first_name":"Antonio"},{"first_name":"Giovanni","last_name":"Squillero","full_name":"Squillero, Giovanni"},{"full_name":"Agapitos, Alexandros","last_name":"Agapitos","first_name":"Alexandros"},{"full_name":"Burelli, Paolo","first_name":"Paolo","last_name":"Burelli"},{"full_name":"S. Bush, William","first_name":"William","last_name":"S. Bush"},{"first_name":"Stefano","last_name":"Cagnoni","full_name":"Cagnoni, Stefano"},{"full_name":"Cotta, Carlos","last_name":"Cotta","first_name":"Carlos"},{"full_name":"De Falco, Ivanoe","first_name":"Ivanoe","last_name":"De Falco"},{"last_name":"Della Cioppa","first_name":"Antonio","full_name":"Della Cioppa, Antonio"},{"full_name":"Divina, Federico","first_name":"Federico","last_name":"Divina"},{"full_name":"Eiben, A.E.","last_name":"Eiben","first_name":"A.E."},{"full_name":"I. Esparcia-Alc{\\'a}zar, Anna","first_name":"Anna","last_name":"I. Esparcia-Alc{\\'a}zar"},{"last_name":"Fern{\\'a}ndez de Vega","first_name":"Francisco","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"full_name":"Glette, Kyrre","last_name":"Glette","first_name":"Kyrre"},{"full_name":"Haasdijk, Evert","first_name":"Evert","last_name":"Haasdijk"},{"last_name":"Ignacio Hidalgo","first_name":"J.","full_name":"Ignacio Hidalgo, J."},{"last_name":"Kampouridis","first_name":"Michael","full_name":"Kampouridis, Michael"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Michalis","last_name":"Mavrovouniotis","full_name":"Mavrovouniotis, Michalis"},{"full_name":"Thanh Nguyen, Trung","first_name":"Trung","last_name":"Thanh Nguyen"},{"last_name":"Schaefer","first_name":"Robert","full_name":"Schaefer, Robert"},{"full_name":"Sim, Kevin","first_name":"Kevin","last_name":"Sim"},{"first_name":"Ernesto","last_name":"Tarantino","full_name":"Tarantino, Ernesto"},{"first_name":"Neil","last_name":"Urquhart","full_name":"Urquhart, Neil"},{"first_name":"Mengjie","last_name":"Zhang (editors)","full_name":"Zhang (editors), Mengjie"}],"year":"2015","title":"Applications of Evolutionary Computation - 18th European Conference, EvoApplications","status":"public","intvolume":"      9028","date_updated":"2022-01-06T06:50:50Z"},{"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T12:07:53Z","publication":"Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)","citation":{"apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In <i>Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)</i> (pp. 1–3). Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293747\">https://doi.org/10.1109/FPL.2015.7293747</a>","ieee":"P. H.W. Leong <i>et al.</i>, “Significant papers from the first 25 years of the FPL conference,” in <i>Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015, pp. 1–3.","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~ao M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “Significant Papers from the First 25 Years of the FPL Conference.” In <i>Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 1–3. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293747\">https://doi.org/10.1109/FPL.2015.7293747</a>.","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3.","mla":"H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.” <i>Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, pp. 1–3, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293747\">10.1109/FPL.2015.7293747</a>.","ama":"H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. 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Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>. 2015;2015. doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, Art. no. 859425, 2015, doi: <a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>, <i>2015</i>, Article 859425. <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i> 2015 (2015). <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015)."},"quality_controlled":"1","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"296","publisher":"Hindawi","ddc":["040"],"user_id":"15278","volume":2015,"status":"public","has_accepted_license":"1","file":[{"date_updated":"2018-03-20T07:47:56Z","relation":"main_file","access_level":"closed","file_size":2993898,"file_name":"296-859425.pdf","content_type":"application/pdf","success":1,"file_id":"1444","creator":"florida","date_created":"2018-03-20T07:47:56Z"}],"date_created":"2017-10-17T12:41:49Z","type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"International Journal of Reconfigurable Computing (IJRC)","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"article_number":"859425","language":[{"iso":"eng"}],"doi":"10.1155/2015/859425","title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","year":"2015","author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:29:08Z","intvolume":"      2015"},{"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"creator":"florida","date_created":"2018-03-20T07:46:46Z","access_level":"open_access","file_size":1176620,"file_name":"303-plessl15_adapt.pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","content_type":"application/pdf","file_id":"1442"}],"date_created":"2017-10-17T12:41:51Z","abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:29:59Z","title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","year":"2015","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"oa":"1","external_id":{"arxiv":["1412.3906"]},"quality_controlled":"1","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"file_date_updated":"2019-08-01T09:10:44Z","citation":{"short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","apa":"Damschen, M., &#38; Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>. ; 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015."},"user_id":"15278","ddc":["040"],"_id":"303","has_accepted_license":"1","status":"public"},{"quality_controlled":"1","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","citation":{"chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM, 2015. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>.","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM; 2015. doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>, ACM, 2015, doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., &#38; Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>","ieee":"J. Schumacher <i>et al.</i>, “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: <a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>."},"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-03-23T14:09:33Z","date_updated":"2023-09-26T13:31:01Z","status":"public","year":"2015","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"full_name":"T. Anderson, J.","first_name":"J.","last_name":"T. Anderson"},{"first_name":"A.","last_name":"Borga","full_name":"Borga, A."},{"first_name":"H.","last_name":"Boterenbrood","full_name":"Boterenbrood, H."},{"first_name":"H.","last_name":"Chen","full_name":"Chen, H."},{"full_name":"Chen, K.","last_name":"Chen","first_name":"K."},{"full_name":"Drake, G.","first_name":"G.","last_name":"Drake"},{"full_name":"Francis, D.","last_name":"Francis","first_name":"D."},{"full_name":"Gorini, B.","first_name":"B.","last_name":"Gorini"},{"full_name":"Lanni, F.","first_name":"F.","last_name":"Lanni"},{"full_name":"Lehmann-Miotto, Giovanna","last_name":"Lehmann-Miotto","first_name":"Giovanna"},{"full_name":"Levinson, L.","first_name":"L.","last_name":"Levinson"},{"first_name":"J.","last_name":"Narevicius","full_name":"Narevicius, J."},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"full_name":"Roich, A.","first_name":"A.","last_name":"Roich"},{"first_name":"S.","last_name":"Ryu","full_name":"Ryu, S."},{"full_name":"P. Schreuder, F.","first_name":"F.","last_name":"P. Schreuder"},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"first_name":"J.","last_name":"Vermeulen","full_name":"Vermeulen, J."},{"first_name":"J.","last_name":"Zhang","full_name":"Zhang, J."}],"doi":"10.1145/2675743.2771824","user_id":"15278","language":[{"iso":"eng"}],"_id":"1773","publisher":"ACM"},{"year":"2015","title":"Aktuelles Schlagwort: Approximate Computing","status":"public","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"full_name":"Schreier, Peter J.","first_name":"Peter J.","last_name":"Schreier"}],"date_updated":"2023-09-26T13:30:22Z","page":"396-399","publisher":"Springer","_id":"1768","language":[{"iso":"eng"}],"doi":"10.1007/s00287-015-0911-z","user_id":"15278","issue":"5","publication":"Informatik Spektrum","citation":{"bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5 (2015): 396–99. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>.","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>. 2015;(5):396-399. doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” <i>Informatik Spektrum</i>, no. 5, pp. 396–399, 2015, doi: <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>.","apa":"Plessl, C., Platzner, M., &#38; Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>, <i>5</i>, 396–399. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5, Springer, 2015, pp. 396–99, doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>."},"quality_controlled":"1","date_created":"2018-03-23T13:58:34Z","type":"journal_article","keyword":["approximate computing","survey"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}]}]