[{"_id":"10767","language":[{"iso":"eng"}],"user_id":"3118","author":[{"full_name":"Ghribi, Ines","first_name":"Ines","last_name":"Ghribi"},{"last_name":"Ben Abdallah","first_name":"Riadh","full_name":"Ben Abdallah, Riadh"},{"first_name":"Mohamed","last_name":"Khalgui","full_name":"Khalgui, Mohamed"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"status":"public","title":"New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software","year":"2015","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:07:55Z","department":[{"_id":"78"}],"type":"conference","citation":{"apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., &#38; Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In <i>Proceedings of the 29th European Simulation and Modelling Conference (ESM)</i>.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,” in <i>Proceedings of the 29th European Simulation and Modelling Conference (ESM)</i>, 2015.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” In <i>Proceedings of the 29th European Simulation and Modelling Conference (ESM)</i>, 2015.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.","mla":"Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” <i>Proceedings of the 29th European Simulation and Modelling Conference (ESM)</i>, 2015.","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: <i>Proceedings of the 29th European Simulation and Modelling Conference (ESM)</i>. ; 2015.","bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2015, title={New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}, booktitle={Proceedings of the 29th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2015} }"},"publication":"Proceedings of the 29th European Simulation and Modelling Conference (ESM)"},{"page":"1117-1126","_id":"10770","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"3118","doi":"10.1109/TNANO.2015.2482359","volume":14,"status":"public","title":"From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires","year":"2015","author":[{"last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"date_updated":"2022-01-06T06:50:50Z","intvolume":"        14","date_created":"2019-07-10T12:08:15Z","type":"journal_article","department":[{"_id":"78"}],"issue":"6","publication":"IEEE Transactions on Nanotechnology","citation":{"chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i> 14, no. 6 (2015): 1117–26. <a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">https://doi.org/10.1109/TNANO.2015.2482359</a>.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &#38; De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>, <i>14</i>(6), 1117–1126. <a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">https://doi.org/10.1109/TNANO.2015.2482359</a>","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, pp. 1117–1126, 2015.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>. 2015;14(6):1117-1126. doi:<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>","bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>."},"extern":"1"},{"page":"491-496","_id":"10771","language":[{"iso":"eng"}],"publisher":"IEEE","user_id":"3118","doi":"10.1109/ISVLSI.2015.13","title":"On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors","status":"public","year":"2015","author":[{"last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186"},{"full_name":"Gaillardon, Pierre-Emmanuel","last_name":"Gaillardon","first_name":"Pierre-Emmanuel"},{"full_name":"Zhang, Jian","last_name":"Zhang","first_name":"Jian"},{"first_name":"Giovanni","last_name":"De Micheli","full_name":"De Micheli, Giovanni"},{"first_name":"Eduardo","last_name":"Sanchez","full_name":"Sanchez, Eduardo"},{"full_name":"Reorda, Matteo Sonza","first_name":"Matteo Sonza","last_name":"Reorda"}],"date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:08:16Z","type":"conference","department":[{"_id":"78"}],"publication":"2015 IEEE Computer Society Annual Symposium on VLSI","citation":{"mla":"Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” <i>2015 IEEE Computer Society Annual Symposium on VLSI</i>, IEEE, 2015, pp. 491–96, doi:<a href=\"https://doi.org/10.1109/ISVLSI.2015.13\">10.1109/ISVLSI.2015.13</a>.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015, title={On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}, DOI={<a href=\"https://doi.org/10.1109/ISVLSI.2015.13\">10.1109/ISVLSI.2015.13</a>}, booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}, year={2015}, pages={491–496} }","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: <i>2015 IEEE Computer Society Annual Symposium on VLSI</i>. IEEE; 2015:491-496. doi:<a href=\"https://doi.org/10.1109/ISVLSI.2015.13\">10.1109/ISVLSI.2015.13</a>","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors,” in <i>2015 IEEE Computer Society Annual Symposium on VLSI</i>, 2015, pp. 491–496.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., &#38; Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In <i>2015 IEEE Computer Society Annual Symposium on VLSI</i> (pp. 491–496). IEEE. <a href=\"https://doi.org/10.1109/ISVLSI.2015.13\">https://doi.org/10.1109/ISVLSI.2015.13</a>","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” In <i>2015 IEEE Computer Society Annual Symposium on VLSI</i>, 491–96. IEEE, 2015. <a href=\"https://doi.org/10.1109/ISVLSI.2015.13\">https://doi.org/10.1109/ISVLSI.2015.13</a>.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496."},"extern":"1"},{"page":"453-458","_id":"10772","publisher":"EDA Consortium","language":[{"iso":"eng"}],"doi":"10.7873/DATE.2015.0428","user_id":"3118","status":"public","title":"Fault modeling in controllable polarity silicon nanowire circuits","year":"2015","author":[{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan"},{"last_name":"Gaillardon","first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel"},{"full_name":"De Micheli, Giovanni","last_name":"De Micheli","first_name":"Giovanni"}],"date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:08:17Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 2015 Design, Automation & Test in Europe Conference \\& Exhibition","citation":{"ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: <i>Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition</i>. EDA Consortium; 2015:453-458. doi:<a href=\"https://doi.org/10.7873/DATE.2015.0428\">10.7873/DATE.2015.0428</a>","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault modeling in controllable polarity silicon nanowire circuits}, DOI={<a href=\"https://doi.org/10.7873/DATE.2015.0428\">10.7873/DATE.2015.0428</a>}, booktitle={Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={453–458} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” <i>Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition</i>, EDA Consortium, 2015, pp. 453–58, doi:<a href=\"https://doi.org/10.7873/DATE.2015.0428\">10.7873/DATE.2015.0428</a>.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition, EDA Consortium, 2015, pp. 453–458.","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” In <i>Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition</i>, 453–58. EDA Consortium, 2015. <a href=\"https://doi.org/10.7873/DATE.2015.0428\">https://doi.org/10.7873/DATE.2015.0428</a>.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &#38; De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In <i>Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition</i> (pp. 453–458). EDA Consortium. <a href=\"https://doi.org/10.7873/DATE.2015.0428\">https://doi.org/10.7873/DATE.2015.0428</a>","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling in controllable polarity silicon nanowire circuits,” in <i>Proceedings of the 2015 Design, Automation &#38; Test in Europe Conference \\&#38; Exhibition</i>, 2015, pp. 453–458."},"extern":"1"},{"date_created":"2019-07-10T12:11:36Z","department":[{"_id":"78"}],"keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"type":"conference","citation":{"short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015.","apa":"Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>."},"publication":"25th International Conference on Field Programmable Logic and Applications (FPL)","extern":"1","language":[{"iso":"eng"}],"_id":"10779","publisher":"Imperial College","user_id":"398","doi":"10.1109/FPL.2015.7293994","author":[{"full_name":"Guettatfi, Zakarya","first_name":"Zakarya","last_name":"Guettatfi"},{"full_name":"Kermia, Omar","last_name":"Kermia","first_name":"Omar"},{"full_name":"Khouas, Abdelhakim","first_name":"Abdelhakim","last_name":"Khouas"}],"publication_identifier":{"issn":["1946-147X"]},"year":"2015","status":"public","title":"Over effective hard real-time hardware tasks scheduling and allocation","date_updated":"2022-01-06T06:50:50Z"},{"_id":"13153","language":[{"iso":"eng"}],"publisher":"Springer International Publishing","page":"1-11","user_id":"40778","doi":"10.1007/978-3-319-27992-3_1","author":[{"first_name":"Tobias","last_name":"Graf","full_name":"Graf, Tobias"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"year":"2015","status":"public","title":"Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning","date_updated":"2022-01-06T06:51:29Z","date_created":"2019-09-09T09:07:46Z","department":[{"_id":"78"}],"type":"conference","citation":{"bibtex":"@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-27992-3_1\">10.1007/978-3-319-27992-3_1</a>}, booktitle={Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015}, pages={1–11} }","ama":"Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: <i>Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers</i>. Springer International Publishing; 2015:1-11. doi:<a href=\"https://doi.org/10.1007/978-3-319-27992-3_1\">10.1007/978-3-319-27992-3_1</a>","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” <i>Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers</i>, Springer International Publishing, 2015, pp. 1–11, doi:<a href=\"https://doi.org/10.1007/978-3-319-27992-3_1\">10.1007/978-3-319-27992-3_1</a>.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” In <i>Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers</i>, 1–11. Springer International Publishing, 2015. <a href=\"https://doi.org/10.1007/978-3-319-27992-3_1\">https://doi.org/10.1007/978-3-319-27992-3_1</a>.","short":"T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11.","ieee":"T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning,” in <i>Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers</i>, 2015, pp. 1–11.","apa":"Graf, T., &#38; Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In <i>Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers</i> (pp. 1–11). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-27992-3_1\">https://doi.org/10.1007/978-3-319-27992-3_1</a>"},"publication":"Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}]},{"doi":"10.1155/2015/859425","article_number":"859425","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:29:08Z","intvolume":"      2015","year":"2015","title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","author":[{"last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"id":"16153","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"date_created":"2018-03-20T07:47:56Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1444","file_size":2993898,"access_level":"closed","file_name":"296-859425.pdf","date_updated":"2018-03-20T07:47:56Z","relation":"main_file"}],"date_created":"2017-10-17T12:41:49Z","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"publication":"International Journal of Reconfigurable Computing (IJRC)","user_id":"15278","ddc":["040"],"volume":2015,"publisher":"Hindawi","_id":"296","has_accepted_license":"1","status":"public","quality_controlled":"1","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"file_date_updated":"2018-03-20T07:47:56Z","citation":{"short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i> 2015 (2015). <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, Art. no. 859425, 2015, doi: <a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>, <i>2015</i>, Article 859425. <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>. 2015;2015. doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, 859425, Hindawi, 2015, doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>."}},{"abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:41:51Z","file":[{"date_updated":"2019-08-01T09:10:44Z","relation":"main_file","file_size":1176620,"access_level":"open_access","file_name":"303-plessl15_adapt.pdf","content_type":"application/pdf","file_id":"1442","creator":"florida","date_created":"2018-03-20T07:46:46Z"}],"date_updated":"2023-09-26T13:29:59Z","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","year":"2015","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>. ; 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","apa":"Damschen, M., &#38; Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>."},"file_date_updated":"2019-08-01T09:10:44Z","oa":"1","external_id":{"arxiv":["1412.3906"]},"has_accepted_license":"1","status":"public","user_id":"15278","ddc":["040"],"_id":"303"},{"date_created":"2018-03-23T14:09:33Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","citation":{"ieee":"J. Schumacher <i>et al.</i>, “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: <a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>.","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>, ACM, 2015, doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., &#38; Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM; 2015. doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM, 2015. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>."},"quality_controlled":"1","publisher":"ACM","_id":"1773","language":[{"iso":"eng"}],"doi":"10.1145/2675743.2771824","user_id":"15278","status":"public","year":"2015","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","author":[{"last_name":"Schumacher","first_name":"Jörn","full_name":"Schumacher, Jörn"},{"last_name":"T. Anderson","first_name":"J.","full_name":"T. Anderson, J."},{"full_name":"Borga, A.","first_name":"A.","last_name":"Borga"},{"full_name":"Boterenbrood, H.","first_name":"H.","last_name":"Boterenbrood"},{"full_name":"Chen, H.","first_name":"H.","last_name":"Chen"},{"full_name":"Chen, K.","last_name":"Chen","first_name":"K."},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"full_name":"Francis, D.","first_name":"D.","last_name":"Francis"},{"full_name":"Gorini, B.","first_name":"B.","last_name":"Gorini"},{"full_name":"Lanni, F.","first_name":"F.","last_name":"Lanni"},{"first_name":"Giovanna","last_name":"Lehmann-Miotto","full_name":"Lehmann-Miotto, Giovanna"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"full_name":"Narevicius, J.","last_name":"Narevicius","first_name":"J."},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"},{"full_name":"Roich, A.","first_name":"A.","last_name":"Roich"},{"last_name":"Ryu","first_name":"S.","full_name":"Ryu, S."},{"full_name":"P. Schreuder, F.","first_name":"F.","last_name":"P. Schreuder"},{"first_name":"Wainer","last_name":"Vandelli","full_name":"Vandelli, Wainer"},{"full_name":"Vermeulen, J.","last_name":"Vermeulen","first_name":"J."},{"last_name":"Zhang","first_name":"J.","full_name":"Zhang, J."}],"date_updated":"2023-09-26T13:31:01Z"},{"keyword":["approximate computing","survey"],"type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"date_created":"2018-03-23T13:58:34Z","quality_controlled":"1","publication":"Informatik Spektrum","issue":"5","citation":{"chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5 (2015): 396–99. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>.","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>. 2015;(5):396-399. doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","apa":"Plessl, C., Platzner, M., &#38; Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>, <i>5</i>, 396–399. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5, Springer, 2015, pp. 396–99, doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>.","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” <i>Informatik Spektrum</i>, no. 5, pp. 396–399, 2015, doi: <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>."},"doi":"10.1007/s00287-015-0911-z","user_id":"15278","page":"396-399","language":[{"iso":"eng"}],"_id":"1768","publisher":"Springer","date_updated":"2023-09-26T13:30:22Z","title":"Aktuelles Schlagwort: Approximate Computing","status":"public","year":"2015","author":[{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Schreier, Peter J.","first_name":"Peter J.","last_name":"Schreier"}]},{"citation":{"bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>. EDA Consortium / IEEE; 2015:1078-1083. doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–83. EDA Consortium / IEEE, 2015. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 2015, pp. 1078–1083, doi: <a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, EDA Consortium / IEEE, 2015, pp. 1078–83, doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","apa":"Damschen, M., Riebler, H., Vaz, G. F., &#38; Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–1083. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>"},"file_date_updated":"2018-03-21T10:29:49Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","status":"public","has_accepted_license":"1","_id":"238","publisher":"EDA Consortium / IEEE","page":"1078-1083","ddc":["040"],"user_id":"15278","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"date_created":"2017-10-17T12:41:38Z","file":[{"creator":"florida","date_created":"2018-03-21T10:29:49Z","date_updated":"2018-03-21T10:29:49Z","relation":"main_file","file_size":380552,"access_level":"closed","file_name":"238-plessl15_date.pdf","success":1,"content_type":"application/pdf","file_id":"1500"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","author":[{"first_name":"Marvin","last_name":"Damschen","full_name":"Damschen, Marvin"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis","id":"30332"},{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","year":"2015","date_updated":"2023-09-26T13:31:44Z","language":[{"iso":"eng"}],"doi":"10.7873/DATE.2015.1124"},{"date_created":"2017-10-17T12:41:59Z","file":[{"file_name":"347-meisner13_xx_SFB1__1_.pdf","access_level":"closed","file_size":1168877,"relation":"main_file","date_updated":"2018-03-20T07:26:16Z","file_id":"1417","success":1,"content_type":"application/pdf","creator":"florida","date_created":"2018-03-20T07:26:16Z"}],"department":[{"_id":"78"}],"type":"conference","publication":"Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)","abstract":[{"lang":"eng","text":"Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead."}],"series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"doi":"10.1007/978-3-319-05960-0_30","author":[{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"title":"Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection","year":"2014","date_updated":"2022-01-06T06:59:18Z","citation":{"short":"S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” In <i>Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)</i>, edited by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels, 283–90. Lecture Notes in Computer Science. Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_30\">https://doi.org/10.1007/978-3-319-05960-0_30</a>.","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection,” in <i>Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)</i>, 2014, pp. 283–290.","apa":"Meisner, S., &#38; Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio, J. P. Cardoso, &#38; K. Bertels (Eds.), <i>Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)</i> (pp. 283–290). Springer. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_30\">https://doi.org/10.1007/978-3-319-05960-0_30</a>","bibtex":"@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_30\">10.1007/978-3-319-05960-0_30</a>}, booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner, Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture Notes in Computer Science} }","ama":"Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. <i>Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)</i>. Lecture Notes in Computer Science. Springer; 2014:283-290. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_30\">10.1007/978-3-319-05960-0_30</a>","mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” <i>Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)</i>, edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_30\">10.1007/978-3-319-05960-0_30</a>."},"file_date_updated":"2018-03-20T07:26:16Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"publisher":"Springer","_id":"347","page":"283-290","editor":[{"last_name":"Goehringer","first_name":"Diana","full_name":"Goehringer, Diana"},{"full_name":"Santambrogio, MarcoDomenico","last_name":"Santambrogio","first_name":"MarcoDomenico"},{"full_name":"Cardoso, JoãoM.P.","last_name":"Cardoso","first_name":"JoãoM.P."},{"last_name":"Bertels","first_name":"Koen","full_name":"Bertels, Koen"}],"user_id":"398","ddc":["040"],"status":"public","has_accepted_license":"1"},{"citation":{"mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” <i>Proc. Conf. on Computers and Games (CG)</i>, no. 8427, Springer, 2014, pp. 14–25, doi:<a href=\"https://doi.org/10.1007/978-3-319-09165-5_2\">10.1007/978-3-319-09165-5_2</a>.","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-09165-5_2\">10.1007/978-3-319-09165-5_2</a>}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: <i>Proc. Conf. on Computers and Games (CG)</i>. Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:<a href=\"https://doi.org/10.1007/978-3-319-09165-5_2\">10.1007/978-3-319-09165-5_2</a>","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in <i>Proc. Conf. on Computers and Games (CG)</i>, 2014, no. 8427, pp. 14–25.","apa":"Graf, T., Schaefers, L., &#38; Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In <i>Proc. Conf. on Computers and Games (CG)</i> (pp. 14–25). Switzerland: Springer. <a href=\"https://doi.org/10.1007/978-3-319-09165-5_2\">https://doi.org/10.1007/978-3-319-09165-5_2</a>","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In <i>Proc. Conf. on Computers and Games (CG)</i>, 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-09165-5_2\">https://doi.org/10.1007/978-3-319-09165-5_2</a>.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25."},"publication":"Proc. Conf. on Computers and Games (CG)","issue":"8427","department":[{"_id":"27"},{"_id":"78"}],"type":"conference","date_created":"2018-03-26T13:50:37Z","place":"Switzerland","date_updated":"2022-01-06T06:53:20Z","author":[{"first_name":"Tobias","last_name":"Graf","full_name":"Graf, Tobias"},{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"title":"On Semeai Detection in Monte-Carlo Go","year":"2014","status":"public","user_id":"24135","doi":"10.1007/978-3-319-09165-5_2","_id":"1782","series_title":"Lecture Notes in Computer Science","publisher":"Springer","page":"14-25"},{"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"short":"T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.","chicago":"Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 167–74, 2014. <a href=\"https://doi.org/10.1109/FPT.2014.7082771\">https://doi.org/10.1109/FPT.2014.7082771</a>.","ieee":"T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2014, pp. 167–174.","apa":"Wiersema, T., Drzevitzky, S., &#38; Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i> (pp. 167–174). <a href=\"https://doi.org/10.1109/FPT.2014.7082771\">https://doi.org/10.1109/FPT.2014.7082771</a>","bibtex":"@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={<a href=\"https://doi.org/10.1109/FPT.2014.7082771\">10.1109/FPT.2014.7082771</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}, year={2014}, pages={167–174} }","ama":"Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. ; 2014:167-174. doi:<a href=\"https://doi.org/10.1109/FPT.2014.7082771\">10.1109/FPT.2014.7082771</a>","mla":"Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2014, pp. 167–74, doi:<a href=\"https://doi.org/10.1109/FPT.2014.7082771\">10.1109/FPT.2014.7082771</a>."},"file_date_updated":"2018-03-20T06:57:44Z","ddc":["040"],"user_id":"477","_id":"399","page":"167-174","has_accepted_license":"1","status":"public","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:09Z","file":[{"success":1,"content_type":"application/pdf","file_id":"1380","date_updated":"2018-03-20T06:57:44Z","relation":"main_file","access_level":"closed","file_size":404328,"file_name":"399-wiersema14_fpt_IEEE_approved.pdf","date_created":"2018-03-20T06:57:44Z","creator":"florida"}],"abstract":[{"lang":"eng","text":"Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric."}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","doi":"10.1109/FPT.2014.7082771","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:00:05Z","author":[{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"full_name":"Drzevitzky, Stephanie","first_name":"Stephanie","last_name":"Drzevitzky"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"title":"Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring","year":"2014"},{"editor":[{"full_name":"Albert, Elvira","first_name":"Elvira","last_name":"Albert"},{"first_name":"Emil","last_name":"Sekerinski","full_name":"Sekerinski, Emil"}],"user_id":"477","ddc":["040"],"_id":"408","page":"307-322","has_accepted_license":"1","status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"chicago":"Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim. “Integrating Software and Hardware Verification.” In <i>Proceedings of the 11th International Conference on Integrated Formal Methods (IFM)</i>, edited by Elvira Albert and Emil Sekerinski, 307–22. LNCS, 2014. <a href=\"https://doi.org/10.1007/978-3-319-10181-1_19\">https://doi.org/10.1007/978-3-319-10181-1_19</a>.","short":"M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.","ieee":"M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in <i>Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)</i>, 2014, pp. 307–322.","apa":"Jakobs, M.-C., Platzner, M., Wiersema, T., &#38; Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert &#38; E. Sekerinski (Eds.), <i>Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)</i> (pp. 307–322). <a href=\"https://doi.org/10.1007/978-3-319-10181-1_19\">https://doi.org/10.1007/978-3-319-10181-1_19</a>","bibtex":"@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating Software and Hardware Verification}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-10181-1_19\">10.1007/978-3-319-10181-1_19</a>}, booktitle={Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors}, year={2014}, pages={307–322}, collection={LNCS} }","ama":"Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. <i>Proceedings of the 11th International Conference on Integrated Formal Methods (IFM)</i>. LNCS. ; 2014:307-322. doi:<a href=\"https://doi.org/10.1007/978-3-319-10181-1_19\">10.1007/978-3-319-10181-1_19</a>","mla":"Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.” <i>Proceedings of the 11th International Conference on Integrated Formal Methods (IFM)</i>, edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:<a href=\"https://doi.org/10.1007/978-3-319-10181-1_19\">10.1007/978-3-319-10181-1_19</a>."},"file_date_updated":"2018-03-16T11:35:28Z","doi":"10.1007/978-3-319-10181-1_19","series_title":"LNCS","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:00:14Z","author":[{"full_name":"Jakobs, Marie-Christine","last_name":"Jakobs","first_name":"Marie-Christine"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"},{"full_name":"Wehrheim, Heike","first_name":"Heike","last_name":"Wehrheim","id":"573"}],"title":"Integrating Software and Hardware Verification","year":"2014","department":[{"_id":"77"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:11Z","file":[{"file_size":561325,"access_level":"closed","file_name":"408-jakobs14_ifm.pdf","date_updated":"2018-03-16T11:35:28Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"1364","creator":"florida","date_created":"2018-03-16T11:35:28Z"}],"abstract":[{"text":"Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.","lang":"eng"}],"publication":"Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)"},{"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–6, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">https://doi.org/10.1109/ReConFig.2014.7032514</a>.","short":"T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">https://doi.org/10.1109/ReConFig.2014.7032514</a>","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–6.","ama":"Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. ; 2014:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>","bibtex":"@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2014}, pages={1–6} }","mla":"Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>."},"file_date_updated":"2018-03-16T11:30:58Z","ddc":["040"],"user_id":"477","_id":"433","page":"1-6 ","has_accepted_license":"1","status":"public","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:16Z","file":[{"file_id":"1355","success":1,"content_type":"application/pdf","relation":"main_file","date_updated":"2018-03-16T11:30:58Z","file_name":"433-wiersema14_reconfig_IEEE_approved.pdf","access_level":"closed","file_size":369333,"date_created":"2018-03-16T11:30:58Z","creator":"florida"}],"abstract":[{"text":"Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2014.7032514","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:00:56Z","author":[{"first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias","id":"3118"},{"last_name":"Bockhorn","first_name":"Arne","full_name":"Bockhorn, Arne"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA","year":"2014"},{"volume":6,"user_id":"3118","doi":"10.1109/TCIAIG.2014.2346997","language":[{"iso":"eng"}],"_id":"10602","page":"361-374","intvolume":"         6","date_updated":"2022-01-06T06:50:47Z","author":[{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"title":"A Novel Technique and its Application to Computer Go","year":"2014","status":"public","department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:22:43Z","citation":{"ieee":"L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, pp. 361–374, 2014.","mla":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, 2014, pp. 361–74, doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>.","apa":"Schaefers, L., &#38; Platzner, M. (2014). A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, <i>6</i>(3), 361–374. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>","bibtex":"@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }","short":"L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374.","ama":"Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>. 2014;6(3):361-374. doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>","chicago":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i> 6, no. 3 (2014): 361–74. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>."},"issue":"3","publication":"IEEE Transactions on Computational Intelligence and AI in Games"},{"citation":{"apa":"Giefers, H., &#38; Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>, <i>63</i>(12), 2919–2932. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>","ieee":"H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, pp. 2919–2932, 2014.","chicago":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i> 63, no. 12 (2014): 2919–32. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>.","short":"H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.","mla":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, 2014, pp. 2919–32, doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>.","ama":"Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>. 2014;63(12):2919-2932. doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>","bibtex":"@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }"},"publication":"IEEE Transactions on Computers","issue":"12","date_created":"2019-07-10T09:22:44Z","department":[{"_id":"78"}],"type":"journal_article","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"title":"An FPGA-based Reconfigurable Mesh Many-Core","status":"public","year":"2014","intvolume":"        63","date_updated":"2022-01-06T06:50:47Z","_id":"10603","language":[{"iso":"eng"}],"page":"2919 - 2932","volume":63,"doi":"10.1109/TC.2013.174","user_id":"398"},{"department":[{"_id":"78"}],"type":"conference","date_created":"2019-07-10T09:32:58Z","citation":{"ieee":"J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014.","apa":"Anwer, J., Platzner, M., &#38; Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In <i>Reconfigurable Architectures Workshop (RAW)</i>. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>","short":"J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.","chicago":"Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” In <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW, 2014. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>.","mla":"Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>.","bibtex":"@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy Configurations: An Automated Design Space Exploration}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>}, booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }","ama":"Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW. ; 2014. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>"},"publication":"Reconfigurable Architectures Workshop (RAW)","doi":"10.1109/IPDPSW.2014.37","user_id":"3118","language":[{"iso":"eng"}],"_id":"10621","series_title":"RAW","date_updated":"2022-01-06T06:50:48Z","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"first_name":"Sebastian","last_name":"Meisner","full_name":"Meisner, Sebastian"}],"year":"2014","status":"public","title":"FPGA Redundancy Configurations: An Automated Design Space Exploration"},{"supervisor":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"}],"citation":{"bibtex":"@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn, Arne}, year={2014} }","ama":"Bockhorn A. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University; 2014.","mla":"Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University, 2014.","chicago":"Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University, 2014.","short":"A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board, Paderborn University, 2014.","ieee":"A. Bockhorn, <i>Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board</i>. Paderborn University, 2014.","apa":"Bockhorn, A. (2014). <i>Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board</i>. Paderborn University."},"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T09:40:25Z","date_updated":"2022-01-06T06:50:48Z","status":"public","year":"2014","title":"Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board","author":[{"full_name":"Bockhorn, Arne","first_name":"Arne","last_name":"Bockhorn"}],"user_id":"3118","language":[{"iso":"eng"}],"_id":"10627","publisher":"Paderborn University"}]