[{"user_id":"3118","publisher":"Paderborn University","_id":"10715","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","year":"2014","status":"public","title":"Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs","author":[{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"}],"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:48:26Z","citation":{"short":"R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.","chicago":"Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University, 2014.","ieee":"R. Mittendorf, <i>Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs</i>. Paderborn University, 2014.","apa":"Mittendorf, R. (2014). <i>Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs</i>. Paderborn University.","bibtex":"@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }","ama":"Mittendorf R. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University; 2014.","mla":"Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University, 2014."}},{"citation":{"ieee":"C. Rüthing, <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","apa":"Rüthing, C. (2014). <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University.","chicago":"Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","short":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.","mla":"Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","bibtex":"@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }","ama":"Rüthing C. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University; 2014."},"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:58:05Z","date_updated":"2022-01-06T06:50:50Z","status":"public","title":"The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores","year":"2014","author":[{"full_name":"Rüthing, Christoph","first_name":"Christoph","last_name":"Rüthing"}],"user_id":"3118","_id":"10732","language":[{"iso":"eng"}],"publisher":"Paderborn University"},{"publication_status":"published","date_updated":"2022-01-06T06:50:50Z","author":[{"full_name":"Schäfers, Lars","last_name":"Schäfers","first_name":"Lars"}],"publication_identifier":{"isbn":["978-3-8325-3748-7"]},"title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","status":"public","year":"2014","user_id":"3118","_id":"10733","language":[{"iso":"eng"}],"publisher":"Logos Verlag Berlin GmbH","page":"133","abstract":[{"lang":"eng","text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches."}],"citation":{"short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.","chicago":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","apa":"Schäfers, L. (2014). <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH.","ieee":"L. Schäfers, <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","ama":"Schäfers L. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH; 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","mla":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Logos Verlag Berlin GmbH, 2014."},"supervisor":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"type":"dissertation","date_created":"2019-07-10T11:58:06Z","place":"Berlin"},{"publication":"IEEE Power and Energy Society General Meeting (IEEE GM)","citation":{"short":"C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” In <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence After a Power System Blackout,” in <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014.","apa":"Shen, C., Kaufmann, P., &#38; Braun, M. (2014). Optimizing the Generator Start-up Sequence After a Power System Blackout. In <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","ama":"Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>. ; 2014.","mla":"Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014."},"date_created":"2019-07-10T11:59:36Z","type":"conference","department":[{"_id":"78"}],"year":"2014","status":"public","title":"Optimizing the Generator Start-up Sequence After a Power System Blackout","author":[{"full_name":"Shen, Cong","first_name":"Cong","last_name":"Shen"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Martin","last_name":"Braun","full_name":"Braun, Martin"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10738","user_id":"3118"},{"author":[{"last_name":"Shen","first_name":"Cong","full_name":"Shen, Cong"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"full_name":"Braun, Martin","first_name":"Martin","last_name":"Braun"}],"year":"2014","status":"public","title":"A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm","date_updated":"2022-01-06T06:50:50Z","publisher":"IEEE","_id":"10739","user_id":"3118","citation":{"ieee":"C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm,” in <i>Power Systems Computation Conference (PSCC)</i>, 2014.","apa":"Shen, C., Kaufmann, P., &#38; Braun, M. (2014). A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In <i>Power Systems Computation Conference (PSCC)</i>. IEEE.","short":"C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” In <i>Power Systems Computation Conference (PSCC)</i>. IEEE, 2014.","mla":"Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” <i>Power Systems Computation Conference (PSCC)</i>, IEEE, 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","ama":"Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: <i>Power Systems Computation Conference (PSCC)</i>. IEEE; 2014."},"publication":"Power Systems Computation Conference (PSCC)","date_created":"2019-07-10T11:59:37Z","department":[{"_id":"78"}],"type":"conference"},{"citation":{"apa":"Surmund, S. (2014). <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University.","ieee":"S. Surmund, <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","chicago":"Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","short":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","mla":"Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","ama":"Surmund S. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University; 2014.","bibtex":"@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }"},"supervisor":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T12:00:45Z","date_updated":"2022-01-06T06:50:50Z","year":"2014","title":"Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA","status":"public","author":[{"last_name":"Surmund","first_name":"Sebastian","full_name":"Surmund, Sebastian"}],"user_id":"3118","_id":"10744","language":[{"iso":"eng"}],"publisher":"Paderborn University"},{"department":[{"_id":"78"}],"type":"book","date_created":"2019-07-10T12:06:33Z","place":"Granada, Spain","citation":{"mla":"I. Esparcia-Alc{\\’a}zar, Anna, et al. <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i>. Vol. 8602, Springer, 2014.","ama":"I. Esparcia-Alc{\\’a}zar A, Eiben AE, Agapitos A, et al. <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i>. Vol 8602. Granada, Spain: Springer; 2014.","bibtex":"@book{I. Esparcia-Alc{\\’a}zar_Eiben_Agapitos_Sim{\\~o}es_G.B. Tettamanzi_Della Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 17th European Conference, EvoApplications}, volume={8602}, publisher={Springer}, author={I. Esparcia-Alc{\\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros and Sim{\\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }","apa":"I. Esparcia-Alc{\\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\\~o}es, A., G.B. Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i> (Vol. 8602). Granada, Spain: Springer.","ieee":"A. I. Esparcia-Alc{\\’a}zar <i>et al.</i>, <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i>, vol. 8602. Granada, Spain: Springer, 2014.","short":"A. I. Esparcia-Alc{\\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\\~o}es, A. G.B. Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk, F. Divina, F. Fern{\\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo, K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\\v s}{\\’\\i}k, R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush (editors), Applications of Evolutionary Computation - 17th European Conference, EvoApplications, Springer, Granada, Spain, 2014.","chicago":"I. Esparcia-Alc{\\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela Sim{\\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et al. <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i>. Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014."},"volume":8602,"user_id":"3118","publisher":"Springer","_id":"10756","series_title":"Lecture Notes in Computer Science","intvolume":"      8602","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Anna","last_name":"I. Esparcia-Alc{\\'a}zar","full_name":"I. Esparcia-Alc{\\'a}zar, Anna"},{"last_name":"Eiben","first_name":"A.E.","full_name":"Eiben, A.E."},{"full_name":"Agapitos, Alexandros","first_name":"Alexandros","last_name":"Agapitos"},{"full_name":"Sim{\\~o}es, Anabela","last_name":"Sim{\\~o}es","first_name":"Anabela"},{"full_name":"G.B. Tettamanzi, Andrea","last_name":"G.B. Tettamanzi","first_name":"Andrea"},{"first_name":"Antonio","last_name":"Della Cioppa","full_name":"Della Cioppa, Antonio"},{"full_name":"M. Mora, Antonio","first_name":"Antonio","last_name":"M. Mora"},{"first_name":"Carlos","last_name":"Cotta","full_name":"Cotta, Carlos"},{"full_name":"Tarantino, Ernesto","first_name":"Ernesto","last_name":"Tarantino"},{"last_name":"Haasdijk","first_name":"Evert","full_name":"Haasdijk, Evert"},{"full_name":"Divina, Federico","last_name":"Divina","first_name":"Federico"},{"first_name":"Francisco","last_name":"Fern{\\'a}ndez de Vega","full_name":"Fern{\\'a}ndez de Vega, Francisco"},{"first_name":"Giovanni","last_name":"Squillero","full_name":"Squillero, Giovanni"},{"first_name":"Ivanoe","last_name":"De Falco","full_name":"De Falco, Ivanoe"},{"first_name":"J.","last_name":"Ignacio Hidalgo","full_name":"Ignacio Hidalgo, J."},{"full_name":"Sim, Kevin","first_name":"Kevin","last_name":"Sim"},{"first_name":"Kyrre","last_name":"Glette","full_name":"Glette, Kyrre"},{"full_name":"Zhang, Mengjie","last_name":"Zhang","first_name":"Mengjie"},{"full_name":"Urquhart, Neil","last_name":"Urquhart","first_name":"Neil"},{"first_name":"Paolo","last_name":"Burelli","full_name":"Burelli, Paolo"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Petr","last_name":"Po{\\v s}{\\'\\i}k","full_name":"Po{\\v s}{\\'\\i}k, Petr"},{"last_name":"Schaefer","first_name":"Robert","full_name":"Schaefer, Robert"},{"first_name":"Rolf","last_name":"Drechsler","full_name":"Drechsler, Rolf"},{"full_name":"Antipolis, Sophia","last_name":"Antipolis","first_name":"Sophia"},{"full_name":"Cagnoni, Stefano","last_name":"Cagnoni","first_name":"Stefano"},{"full_name":"Thanh Nguyen, Trung","last_name":"Thanh Nguyen","first_name":"Trung"},{"full_name":"S. Bush (editors), William","first_name":"William","last_name":"S. Bush (editors)"}],"year":"2014","title":"Applications of Evolutionary Computation - 17th European Conference, EvoApplications","status":"public"},{"date_updated":"2022-01-06T06:50:50Z","status":"public","title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","year":"2014","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"user_id":"398","doi":"10.1109/DFT.2014.6962108","page":"177-184","language":[{"iso":"eng"}],"_id":"10764","publisher":"IEEE","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","citation":{"mla":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, IEEE, 2014, pp. 177–84, doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>.","bibtex":"@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2014}, pages={177–184} }","ama":"Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>. IEEE; 2014:177-184. doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>","ieee":"J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 2014, pp. 177–184.","apa":"Anwer, J., &#38; Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i> (pp. 177–184). IEEE. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>","short":"J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 177–84. IEEE, 2014. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>."},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T12:07:05Z"},{"date_created":"2019-07-10T12:10:16Z","type":"conference","department":[{"_id":"78"}],"publication":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","citation":{"chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani, and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” In <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)</i>, 163–68. IEEE, 2014. <a href=\"https://doi.org/10.1109/NANOARCH.2014.6880479\">https://doi.org/10.1109/NANOARCH.2014.6880479</a>.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168.","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)</i>. IEEE; 2014:163-168. doi:<a href=\"https://doi.org/10.1109/NANOARCH.2014.6880479\">10.1109/NANOARCH.2014.6880479</a>","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014, title={Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}, DOI={<a href=\"https://doi.org/10.1109/NANOARCH.2014.6880479\">10.1109/NANOARCH.2014.6880479</a>}, booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.” <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)</i>, IEEE, 2014, pp. 163–68, doi:<a href=\"https://doi.org/10.1109/NANOARCH.2014.6880479\">10.1109/NANOARCH.2014.6880479</a>.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., &#38; De Micheli, G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)</i> (pp. 163–168). IEEE. <a href=\"https://doi.org/10.1109/NANOARCH.2014.6880479\">https://doi.org/10.1109/NANOARCH.2014.6880479</a>","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection,” in <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)</i>, 2014, pp. 163–168."},"extern":"1","page":"163-168","language":[{"iso":"eng"}],"_id":"10773","publisher":"IEEE","user_id":"3118","doi":"10.1109/NANOARCH.2014.6880479","title":"Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection","status":"public","year":"2014","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","id":"61186"},{"first_name":"Pierre-Emmanuel","last_name":"Gaillardon","full_name":"Gaillardon, Pierre-Emmanuel"},{"full_name":"Yazdani, Majid","first_name":"Majid","last_name":"Yazdani"},{"first_name":"Giovanni","last_name":"De Micheli","full_name":"De Micheli, Giovanni"}],"date_updated":"2022-01-06T06:50:50Z"},{"doi":"10.1109/CIG.2014.6932863","user_id":"40778","page":"1-8","language":[{"iso":"eng"}],"_id":"13154","date_updated":"2022-01-06T06:51:29Z","year":"2014","status":"public","title":"Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go","author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-09-09T09:09:31Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication":"2014 IEEE Conference on Computational Intelligence and Games","citation":{"ama":"Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: <i>2014 IEEE Conference on Computational Intelligence and Games</i>. ; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>","bibtex":"@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}, DOI={<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>}, booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2014}, pages={1–8} }","mla":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>.","chicago":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” In <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 1–8, 2014. <a href=\"https://doi.org/10.1109/CIG.2014.6932863\">https://doi.org/10.1109/CIG.2014.6932863</a>.","short":"T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.","apa":"Graf, T., &#38; Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In <i>2014 IEEE Conference on Computational Intelligence and Games</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/CIG.2014.6932863\">https://doi.org/10.1109/CIG.2014.6932863</a>","ieee":"T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go,” in <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 2014, pp. 1–8."}},{"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}],"year":"2014","title":"Verschiebungen an der Grenze zwischen Hardware und Software","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"author":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"date_updated":"2023-09-26T13:32:49Z","publication_status":"published","file":[{"creator":"florida","date_created":"2018-03-20T07:29:58Z","date_updated":"2018-03-20T07:29:58Z","relation":"main_file","access_level":"closed","file_size":2848154,"file_name":"335-2014_plessl_automatismen.pdf","success":1,"content_type":"application/pdf","file_id":"1424"}],"date_created":"2017-10-17T12:41:57Z","type":"book_chapter","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"publication":"Logiken strukturbildender Prozesse: Automatismen","abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"page":"123-144","_id":"335","publisher":"Wilhelm Fink","ddc":["040"],"user_id":"15278","editor":[{"full_name":"Künsemöller, Jörn","first_name":"Jörn","last_name":"Künsemöller"},{"first_name":"Norber Otto","last_name":"Eke","full_name":"Eke, Norber Otto"},{"last_name":"Foit","first_name":"Lioba","full_name":"Foit, Lioba"},{"first_name":"Timo","last_name":"Kaerlein","full_name":"Kaerlein, Timo"}],"status":"public","has_accepted_license":"1","place":"Paderborn","file_date_updated":"2018-03-20T07:29:58Z","citation":{"ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014."},"quality_controlled":"1","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}]},{"status":"public","has_accepted_license":"1","publisher":"Springer International Publishing","_id":"388","page":"144-155","volume":8405,"ddc":["040"],"user_id":"15278","citation":{"apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }"},"file_date_updated":"2018-03-20T07:02:02Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","place":"Cham","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis","id":"30332"},{"last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"year":"2014","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","intvolume":"      8405","date_updated":"2023-09-26T13:34:08Z","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"doi":"10.1007/978-3-319-05960-0_13","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"date_created":"2017-10-17T12:42:07Z","file":[{"date_created":"2018-03-20T07:02:02Z","creator":"florida","content_type":"application/pdf","success":1,"file_id":"1387","access_level":"closed","file_size":330193,"file_name":"388-plessl14_arc.pdf","date_updated":"2018-03-20T07:02:02Z","relation":"main_file"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference"},{"_id":"363","publisher":"Elsevier","page":"911-919","volume":38,"user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1","citation":{"bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>"},"file_date_updated":"2018-03-20T07:20:31Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2013.12.001","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"}],"year":"2014","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","intvolume":"        38","date_updated":"2023-09-26T13:33:06Z","date_created":"2017-10-17T12:42:02Z","file":[{"date_updated":"2018-03-20T07:20:31Z","relation":"main_file","access_level":"closed","file_size":1499996,"file_name":"363-plessl13_micpro.pdf","content_type":"application/pdf","success":1,"file_id":"1408","creator":"florida","date_created":"2018-03-20T07:20:31Z"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","publication":"Microprocessors and Microsystems","issue":"8, Part B","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}]},{"citation":{"mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>."},"file_date_updated":"2018-03-20T07:14:20Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"quality_controlled":"1","_id":"377","publisher":"IEEE","page":"222-229","ddc":["040"],"user_id":"15278","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:05Z","file":[{"date_created":"2018-03-20T07:14:20Z","creator":"florida","content_type":"application/pdf","success":1,"file_id":"1397","date_updated":"2018-03-20T07:14:20Z","relation":"main_file","file_size":1003907,"access_level":"closed","file_name":"377-FCCM14.pdf"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["coldboot"],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","author":[{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"id":"3145","first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"}],"year":"2014","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","date_updated":"2023-09-26T13:33:50Z"},{"issue":"2","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"date_created":"2017-10-17T12:42:03Z","file":[{"content_type":"application/pdf","success":1,"file_id":"1406","date_updated":"2018-03-20T07:19:19Z","relation":"main_file","access_level":"closed","file_size":916052,"file_name":"365-plessl14_trets_01.pdf","date_created":"2018-03-20T07:19:19Z","creator":"florida"}],"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"type":"journal_article","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","last_name":"Lösch","id":"43646"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","intvolume":"         7","date_updated":"2023-09-26T13:33:31Z","language":[{"iso":"eng"}],"article_number":"13","doi":"10.1145/2617596","citation":{"mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014)."},"file_date_updated":"2018-03-20T07:19:19Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"quality_controlled":"1","status":"public","has_accepted_license":"1","publisher":"ACM","_id":"365","volume":7,"user_id":"15278","ddc":["040"]},{"user_id":"15278","ddc":["040"],"volume":34,"page":"60-71","_id":"328","publisher":"IEEE","has_accepted_license":"1","status":"public","quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"file_date_updated":"2018-03-20T07:31:40Z","citation":{"ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>"},"doi":"10.1109/MM.2013.110","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:32:31Z","intvolume":"        34","year":"2014","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"date_created":"2018-03-20T07:31:40Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1426","access_level":"closed","file_size":1877185,"file_name":"328-plessl14_micro_01.pdf","date_updated":"2018-03-20T07:31:40Z","relation":"main_file"}],"date_created":"2017-10-17T12:41:55Z","abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"publication":"IEEE Micro","issue":"1"},{"date_updated":"2023-09-26T13:35:40Z","author":[{"full_name":"C. Durelli, Gianluca","last_name":"C. Durelli","first_name":"Gianluca"},{"full_name":"Pogliani, Marcello","first_name":"Marcello","last_name":"Pogliani"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"last_name":"Riebler","first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961"},{"last_name":"Vaz","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332"},{"last_name":"D. Santambrogio","first_name":"Marco","full_name":"D. Santambrogio, Marco"},{"full_name":"Bolchini, Cristiana","last_name":"Bolchini","first_name":"Cristiana"}],"year":"2014","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","status":"public","doi":"10.1109/ISPA.2014.27","user_id":"15278","_id":"1778","publisher":"IEEE","language":[{"iso":"eng"}],"page":"142-149","project":[{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>","ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>."},"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2018-03-26T13:40:14Z"},{"abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:17Z","file":[{"access_level":"closed","file_size":557362,"file_name":"439-plessl14a_reconfig.pdf","date_updated":"2018-03-16T11:29:52Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"1353","creator":"florida","date_created":"2018-03-16T11:29:52Z"}],"date_updated":"2023-09-26T13:37:02Z","author":[{"full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis","id":"30332"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","year":"2014","doi":"10.1109/ReConFig.2014.7032509","language":[{"iso":"eng"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }"},"file_date_updated":"2018-03-16T11:29:52Z","has_accepted_license":"1","status":"public","user_id":"15278","ddc":["040"],"_id":"439","publisher":"IEEE","page":"1-8"},{"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032535","author":[{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Schmitz, Henning","last_name":"Schmitz","first_name":"Henning"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","year":"2014","date_updated":"2023-09-26T13:36:40Z","date_created":"2017-10-17T12:42:11Z","file":[{"creator":"florida","date_created":"2018-03-16T11:37:42Z","file_size":932852,"access_level":"closed","file_name":"406-ReConFig14.pdf","date_updated":"2018-03-16T11:37:42Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"1366"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"publisher":"IEEE","_id":"406","page":"1-8","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1","citation":{"bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>"},"file_date_updated":"2018-03-16T11:37:42Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"quality_controlled":"1"},{"citation":{"ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer; 2014. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>, Springer, 2014, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","apa":"C. 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