[{"file":[{"date_created":"2018-03-20T07:29:58Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1424","date_updated":"2018-03-20T07:29:58Z","relation":"main_file","file_size":2848154,"access_level":"closed","file_name":"335-2014_plessl_automatismen.pdf"}],"date_created":"2017-10-17T12:41:57Z","type":"book_chapter","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"publication":"Logiken strukturbildender Prozesse: Automatismen","abstract":[{"lang":"eng","text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf."}],"language":[{"iso":"ger"}],"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","title":"Verschiebungen an der Grenze zwischen Hardware und Software","year":"2014","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"author":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","id":"16153"}],"date_updated":"2023-09-26T13:32:49Z","publication_status":"published","place":"Paderborn","file_date_updated":"2018-03-20T07:29:58Z","citation":{"bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44."},"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"page":"123-144","publisher":"Wilhelm Fink","_id":"335","ddc":["040"],"user_id":"15278","editor":[{"full_name":"Künsemöller, Jörn","last_name":"Künsemöller","first_name":"Jörn"},{"full_name":"Eke, Norber Otto","last_name":"Eke","first_name":"Norber Otto"},{"last_name":"Foit","first_name":"Lioba","full_name":"Foit, Lioba"},{"first_name":"Timo","last_name":"Kaerlein","full_name":"Kaerlein, Timo"}],"status":"public","has_accepted_license":"1"},{"file_date_updated":"2018-03-20T07:02:02Z","citation":{"mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155."},"quality_controlled":"1","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"place":"Cham","status":"public","has_accepted_license":"1","page":"144-155","publisher":"Springer International Publishing","_id":"388","ddc":["040"],"user_id":"15278","volume":8405,"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"file":[{"file_id":"1387","content_type":"application/pdf","success":1,"file_name":"388-plessl14_arc.pdf","file_size":330193,"access_level":"closed","relation":"main_file","date_updated":"2018-03-20T07:02:02Z","date_created":"2018-03-20T07:02:02Z","creator":"florida"}],"date_created":"2017-10-17T12:42:07Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","year":"2014","author":[{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis","id":"30332"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"}],"date_updated":"2023-09-26T13:34:08Z","intvolume":"      8405","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/978-3-319-05960-0_13"},{"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"publication":"Microprocessors and Microsystems","issue":"8, Part B","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","date_created":"2017-10-17T12:42:02Z","file":[{"success":1,"content_type":"application/pdf","file_id":"1408","file_size":1499996,"access_level":"closed","file_name":"363-plessl13_micpro.pdf","date_updated":"2018-03-20T07:20:31Z","relation":"main_file","date_created":"2018-03-20T07:20:31Z","creator":"florida"}],"intvolume":"        38","date_updated":"2023-09-26T13:33:06Z","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"year":"2014","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","doi":"10.1016/j.micpro.2013.12.001","language":[{"iso":"eng"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"quality_controlled":"1","citation":{"chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>."},"file_date_updated":"2018-03-20T07:20:31Z","has_accepted_license":"1","status":"public","volume":38,"user_id":"15278","ddc":["040"],"_id":"363","publisher":"Elsevier","page":"911-919"},{"user_id":"15278","ddc":["040"],"publisher":"IEEE","_id":"377","page":"222-229","has_accepted_license":"1","status":"public","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>."},"file_date_updated":"2018-03-20T07:14:20Z","doi":"10.1109/FCCM.2014.67","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:33:50Z","author":[{"last_name":"Riebler","first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961"},{"id":"3145","first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","year":"2014","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["coldboot"],"type":"conference","date_created":"2017-10-17T12:42:05Z","file":[{"date_created":"2018-03-20T07:14:20Z","creator":"florida","file_id":"1397","success":1,"content_type":"application/pdf","relation":"main_file","date_updated":"2018-03-20T07:14:20Z","file_name":"377-FCCM14.pdf","access_level":"closed","file_size":1003907}],"abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)"},{"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"id":"43646","first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2023-09-26T13:33:31Z","intvolume":"         7","article_number":"13","language":[{"iso":"eng"}],"doi":"10.1145/2617596","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","issue":"2","abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"file":[{"date_created":"2018-03-20T07:19:19Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1406","date_updated":"2018-03-20T07:19:19Z","relation":"main_file","file_size":916052,"access_level":"closed","file_name":"365-plessl14_trets_01.pdf"}],"date_created":"2017-10-17T12:42:03Z","type":"journal_article","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"status":"public","has_accepted_license":"1","_id":"365","publisher":"ACM","user_id":"15278","ddc":["040"],"volume":7,"file_date_updated":"2018-03-20T07:19:19Z","citation":{"apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }"},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","date_created":"2017-10-17T12:41:55Z","file":[{"date_created":"2018-03-20T07:31:40Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1426","date_updated":"2018-03-20T07:31:40Z","relation":"main_file","file_size":1877185,"access_level":"closed","file_name":"328-plessl14_micro_01.pdf"}],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"issue":"1","publication":"IEEE Micro","doi":"10.1109/MM.2013.110","language":[{"iso":"eng"}],"intvolume":"        34","date_updated":"2023-09-26T13:32:31Z","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Ariane","last_name":"Keller","full_name":"Keller, Ariane"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"year":"2014","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1","citation":{"apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>","ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }"},"file_date_updated":"2018-03-20T07:31:40Z","volume":34,"ddc":["040"],"user_id":"15278","_id":"328","publisher":"IEEE","page":"60-71","has_accepted_license":"1","status":"public"},{"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","year":"2014","status":"public","author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"full_name":"Pogliani, Marcello","first_name":"Marcello","last_name":"Pogliani"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"},{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"last_name":"Vaz","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332"},{"full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio","first_name":"Marco"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"date_updated":"2023-09-26T13:35:40Z","page":"142-149","_id":"1778","publisher":"IEEE","language":[{"iso":"eng"}],"doi":"10.1109/ISPA.2014.27","user_id":"15278","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","citation":{"mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>","ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }"},"quality_controlled":"1","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2018-03-26T13:40:14Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"has_accepted_license":"1","status":"public","user_id":"15278","ddc":["040"],"_id":"439","publisher":"IEEE","page":"1-8","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>"},"file_date_updated":"2018-03-16T11:29:52Z","date_updated":"2023-09-26T13:37:02Z","author":[{"id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis"},{"last_name":"Riebler","first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961"},{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"year":"2014","title":"Deferring Accelerator Offloading Decisions to Application Runtime","doi":"10.1109/ReConFig.2014.7032509","language":[{"iso":"eng"}],"abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:17Z","file":[{"access_level":"closed","file_size":557362,"file_name":"439-plessl14a_reconfig.pdf","date_updated":"2018-03-16T11:29:52Z","relation":"main_file","content_type":"application/pdf","success":1,"file_id":"1353","creator":"florida","date_created":"2018-03-16T11:29:52Z"}]},{"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"file_id":"1366","success":1,"content_type":"application/pdf","file_name":"406-ReConFig14.pdf","access_level":"closed","file_size":932852,"relation":"main_file","date_updated":"2018-03-16T11:37:42Z","date_created":"2018-03-16T11:37:42Z","creator":"florida"}],"date_created":"2017-10-17T12:42:11Z","abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:36:40Z","year":"2014","title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","author":[{"last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"}],"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"file_date_updated":"2018-03-16T11:37:42Z","citation":{"bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>."},"user_id":"15278","ddc":["040"],"page":"1-8","_id":"406","publisher":"IEEE","has_accepted_license":"1","status":"public"},{"date_created":"2018-03-26T13:45:35Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","citation":{"short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., &#38; Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>","ieee":"G. C. Durelli <i>et al.</i>, “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>.","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer; 2014. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>, Springer, 2014, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>."},"quality_controlled":"1","project":[{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"publisher":"Springer","_id":"1780","language":[{"iso":"eng"}],"user_id":"15278","doi":"10.1007/978-3-319-05960-0_38","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","year":"2014","status":"public","author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"full_name":"Copolla, Marcello","first_name":"Marcello","last_name":"Copolla"},{"full_name":"Djafarian, Karim","last_name":"Djafarian","first_name":"Karim"},{"last_name":"Koranaros","first_name":"George","full_name":"Koranaros, George"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"full_name":"Paolino, Michele","first_name":"Michele","last_name":"Paolino"},{"first_name":"Oliver","last_name":"Pell","full_name":"Pell, Oliver"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"date_updated":"2023-09-26T13:36:20Z"},{"_id":"1779","publisher":"ACM","page":"65-70","volume":41,"user_id":"15278","status":"public","citation":{"ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, pp. 65–70, 2014, doi: <a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","apa":"Giefers, H., Plessl, C., &#38; Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>, <i>41</i>(5), 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i> 41, no. 5 (2014): 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>.","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>. 2014;41(5):65-70. doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>"},"quality_controlled":"1","language":[{"iso":"eng"}],"doi":"10.1145/2641361.2641372","author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","id":"158"}],"publication_identifier":{"issn":["0163-5964"]},"year":"2014","title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","intvolume":"        41","date_updated":"2023-09-26T13:35:58Z","date_created":"2018-03-26T13:42:34Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"type":"journal_article","keyword":["funding-maxup","tet_topic_hpc"],"publication":"ACM SIGARCH Computer Architecture News","issue":"5"},{"user_id":"3118","page":"249","_id":"11619","publisher":"Logos Verlag Berlin GmbH","language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2022-01-06T06:51:04Z","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","year":"2013","status":"public","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"publication_identifier":{"isbn":["978-3-8325-3530-8"]},"type":"dissertation","department":[{"_id":"78"}],"date_created":"2019-07-11T11:51:51Z","place":"Berlin","abstract":[{"lang":"eng","text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches."}],"citation":{"apa":"Kaufmann, P. (2013). <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH.","mla":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Logos Verlag Berlin GmbH, 2013.","ieee":"P. Kaufmann, <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","ama":"Kaufmann P. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.","chicago":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }"},"supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}]},{"date_created":"2018-03-26T14:48:53Z","department":[{"_id":"27"},{"_id":"78"}],"type":"conference","citation":{"short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/SIU.2013.6531530\">https://doi.org/10.1109/SIU.2013.6531530</a>.","apa":"Kasap, S., &#38; Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE. <a href=\"https://doi.org/10.1109/SIU.2013.6531530\">https://doi.org/10.1109/SIU.2013.6531530</a>","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>, 2013.","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>."},"publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","_id":"1786","publisher":"IEEE","user_id":"24135","doi":"10.1109/SIU.2013.6531530","author":[{"full_name":"Kasap, Server","last_name":"Kasap","first_name":"Server"},{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"}],"year":"2013","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","status":"public","date_updated":"2022-01-06T06:53:20Z"},{"status":"public","year":"2013","title":"Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices","author":[{"first_name":"Server","last_name":"Kasap","full_name":"Kasap, Server"},{"full_name":"Redif, Soydan","first_name":"Soydan","last_name":"Redif"}],"date_updated":"2022-01-06T06:53:23Z","intvolume":"        22","page":"522-536","_id":"1792","publisher":"IEEE","doi":"10.1109/TVLSI.2013.2248069","user_id":"24135","volume":22,"publication":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems","issue":"3","citation":{"apa":"Kasap, S., &#38; Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, <i>22</i>(3), 522–536. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>","ieee":"S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, pp. 522–536, 2013.","chicago":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i> 22, no. 3 (2013): 522–36. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>.","short":"S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>.","ama":"Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans on Very Large Scale Integration (VLSI) Systems</i>. 2013;22(3):522-536. doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>","bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }"},"date_created":"2018-03-26T15:15:03Z","type":"journal_article","department":[{"_id":"27"},{"_id":"78"}]},{"user_id":"477","page":"220","_id":"501","publisher":"Logos Verlag Berlin GmbH","status":"public","place":"Berlin","project":[{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"}],"citation":{"ieee":"M. Happe, <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","apa":"Happe, M. (2013). <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH.","chicago":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","mla":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","ama":"Happe M. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2013."},"supervisor":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2022-01-06T07:01:34Z","title":"Performance and thermal management on self-adaptive hybrid multi-cores","year":"2013","publication_identifier":{"isbn":["978-3-8325-3425-7"]},"author":[{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"}],"type":"dissertation","department":[{"_id":"78"}],"date_created":"2017-10-17T12:42:30Z","abstract":[{"text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. ","lang":"eng"}],"related_material":{"link":[{"relation":"confirmation","url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id="}]}},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:22:45Z","citation":{"bibtex":"@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8}, DOI={<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>}, number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110} }","ama":"Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. <i>International Journal of Real-time Image Processing</i>. 2013;8(1):95-110. doi:<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>","mla":"Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” <i>International Journal of Real-Time Image Processing</i>, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>.","short":"M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image Processing 8 (2013) 95–110.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” <i>International Journal of Real-Time Image Processing</i> 8, no. 1 (2013): 95–110. <a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">https://doi.org/doi:10.1007/s11554-011-0212-y</a>.","ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” <i>International Journal of Real-time Image Processing</i>, vol. 8, no. 1, pp. 95–110, 2013.","apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2013). A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. <i>International Journal of Real-Time Image Processing</i>, <i>8</i>(1), 95–110. <a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">https://doi.org/doi:10.1007/s11554-011-0212-y</a>"},"publication":"International Journal of Real-time Image Processing","issue":"1","volume":8,"doi":"doi:10.1007/s11554-011-0212-y","user_id":"398","_id":"10604","publisher":"Springer","language":[{"iso":"eng"}],"page":"95 - 110","intvolume":"         8","date_updated":"2022-01-06T06:50:47Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"year":"2013","title":"A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking","status":"public"},{"date_updated":"2022-01-06T06:50:48Z","title":"Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime","year":"2013","status":"public","author":[{"first_name":"Jahanzeb","last_name":"Anwer","full_name":"Anwer, Jahanzeb"},{"first_name":"Sebastian","last_name":"Meisner","full_name":"Meisner, Sebastian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"user_id":"3118","doi":"10.1109/ReConFig.2013.6732280","page":"1-6","_id":"10620","language":[{"iso":"eng"}],"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on","citation":{"ama":"Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>. ; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>","bibtex":"@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>.","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 1–6, 2013. <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>.","short":"J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.","apa":"Anwer, J., Meisner, S., &#38; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i>, 2013, pp. 1–6."},"keyword":["fault tolerant computing","field programmable gate arrays","logic design","reliability","BYU-LANL tool","DRM tool flow","FPGA based hardware designs","avionic application","device technologies","dynamic reliability management","fault-tolerant operation","hardware designs","reconfiguring reliability levels","space applications","Field programmable gate arrays","Hardware","Redundancy","Reliability engineering","Runtime","Tunneling magnetoresistance"],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T09:32:57Z"},{"author":[{"first_name":"Christian","last_name":"Bick","full_name":"Bick, Christian"}],"year":"2013","title":"Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner","status":"public","date_updated":"2022-01-06T06:50:48Z","publisher":"Paderborn University","_id":"10626","language":[{"iso":"eng"}],"user_id":"3118","citation":{"mla":"Bick, Christian. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University, 2013.","ama":"Bick C. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University; 2013.","bibtex":"@book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick, Christian}, year={2013} }","apa":"Bick, C. (2013). <i>Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Paderborn University.","ieee":"C. Bick, <i>Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Paderborn University, 2013.","chicago":"Bick, Christian. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University, 2013.","short":"C. Bick, Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner, Paderborn University, 2013."},"date_created":"2019-07-10T09:40:24Z","department":[{"_id":"78"}],"type":"bachelorsthesis"},{"date_updated":"2022-01-06T06:50:49Z","author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Nofen","first_name":"Barbara","full_name":"Nofen, Barbara"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"year":"2013","status":"public","title":"Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes","user_id":"3118","_id":"10634","language":[{"iso":"eng"}],"citation":{"chicago":"Boschmann, Alexander, Barbara Nofen, and Marco Platzner. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2013.","short":"A. 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