[{"date_created":"2018-03-26T13:42:34Z","type":"journal_article","keyword":["funding-maxup","tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"issue":"5","publication":"ACM SIGARCH Computer Architecture News","language":[{"iso":"eng"}],"doi":"10.1145/2641361.2641372","year":"2014","title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","publication_identifier":{"issn":["0163-5964"]},"author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"id":"158","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","first_name":"Jens"}],"date_updated":"2023-09-26T13:35:58Z","intvolume":"        41","citation":{"bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>. 2014;41(5):65-70. doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i> 41, no. 5 (2014): 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, pp. 65–70, 2014, doi: <a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","apa":"Giefers, H., Plessl, C., &#38; Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>, <i>41</i>(5), 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>"},"quality_controlled":"1","page":"65-70","_id":"1779","publisher":"ACM","user_id":"15278","volume":41,"status":"public"},{"place":"Berlin","date_created":"2019-07-11T11:51:51Z","type":"dissertation","department":[{"_id":"78"}],"supervisor":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"citation":{"short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.","ama":"Kaufmann P. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","chicago":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }","mla":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Logos Verlag Berlin GmbH, 2013.","apa":"Kaufmann, P. (2013). <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH.","ieee":"P. Kaufmann, <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013."},"abstract":[{"lang":"eng","text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches."}],"page":"249","_id":"11619","publisher":"Logos Verlag Berlin GmbH","language":[{"iso":"eng"}],"user_id":"3118","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","status":"public","year":"2013","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"}],"publication_identifier":{"isbn":["978-3-8325-3530-8"]},"date_updated":"2022-01-06T06:51:04Z","publication_status":"published"},{"type":"conference","department":[{"_id":"27"},{"_id":"78"}],"date_created":"2018-03-26T14:48:53Z","publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/SIU.2013.6531530\">https://doi.org/10.1109/SIU.2013.6531530</a>.","short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>, 2013.","apa":"Kasap, S., &#38; Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE. <a href=\"https://doi.org/10.1109/SIU.2013.6531530\">https://doi.org/10.1109/SIU.2013.6531530</a>","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” <i>Proc. IEEE Signal Processing and Communications Conf. (SUI)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/SIU.2013.6531530\">10.1109/SIU.2013.6531530</a>."},"doi":"10.1109/SIU.2013.6531530","user_id":"24135","publisher":"IEEE","_id":"1786","date_updated":"2022-01-06T06:53:20Z","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","year":"2013","status":"public","author":[{"first_name":"Server","last_name":"Kasap","full_name":"Kasap, Server"},{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"}]},{"author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"first_name":"Soydan","last_name":"Redif","full_name":"Redif, Soydan"}],"year":"2013","status":"public","title":"Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices","intvolume":"        22","date_updated":"2022-01-06T06:53:23Z","publisher":"IEEE","_id":"1792","page":"522-536","volume":22,"user_id":"24135","doi":"10.1109/TVLSI.2013.2248069","citation":{"bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }","ama":"Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans on Very Large Scale Integration (VLSI) Systems</i>. 2013;22(3):522-536. doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>.","chicago":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i> 22, no. 3 (2013): 522–36. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>.","short":"S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","ieee":"S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, pp. 522–536, 2013.","apa":"Kasap, S., &#38; Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, <i>22</i>(3), 522–536. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>"},"publication":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems","issue":"3","date_created":"2018-03-26T15:15:03Z","department":[{"_id":"27"},{"_id":"78"}],"type":"journal_article"},{"page":"220","_id":"501","publisher":"Logos Verlag Berlin GmbH","user_id":"477","status":"public","place":"Berlin","supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"citation":{"short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","chicago":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","ieee":"M. Happe, <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","apa":"Happe, M. (2013). <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","ama":"Happe M. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","mla":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Logos Verlag Berlin GmbH, 2013."},"project":[{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"}],"language":[{"iso":"eng"}],"title":"Performance and thermal management on self-adaptive hybrid multi-cores","year":"2013","publication_identifier":{"isbn":["978-3-8325-3425-7"]},"author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"}],"date_updated":"2022-01-06T07:01:34Z","publication_status":"published","date_created":"2017-10-17T12:42:30Z","type":"dissertation","department":[{"_id":"78"}],"abstract":[{"text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. ","lang":"eng"}],"related_material":{"link":[{"relation":"confirmation","url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id="}]}},{"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:45Z","issue":"1","publication":"International Journal of Real-time Image Processing","citation":{"short":"M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image Processing 8 (2013) 95–110.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” <i>International Journal of Real-Time Image Processing</i> 8, no. 1 (2013): 95–110. <a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">https://doi.org/doi:10.1007/s11554-011-0212-y</a>.","apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2013). A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. <i>International Journal of Real-Time Image Processing</i>, <i>8</i>(1), 95–110. <a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">https://doi.org/doi:10.1007/s11554-011-0212-y</a>","ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” <i>International Journal of Real-time Image Processing</i>, vol. 8, no. 1, pp. 95–110, 2013.","ama":"Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. <i>International Journal of Real-time Image Processing</i>. 2013;8(1):95-110. doi:<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>","bibtex":"@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8}, DOI={<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>}, number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110} }","mla":"Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” <i>International Journal of Real-Time Image Processing</i>, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:<a href=\"https://doi.org/doi:10.1007/s11554-011-0212-y\">doi:10.1007/s11554-011-0212-y</a>."},"doi":"doi:10.1007/s11554-011-0212-y","user_id":"398","volume":8,"page":"95 - 110","language":[{"iso":"eng"}],"_id":"10604","publisher":"Springer","date_updated":"2022-01-06T06:50:47Z","intvolume":"         8","status":"public","year":"2013","title":"A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}]},{"citation":{"bibtex":"@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }","ama":"Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>. ; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>.","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 1–6, 2013. <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>.","short":"J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i>, 2013, pp. 1–6.","apa":"Anwer, J., Meisner, S., &#38; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>"},"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on","date_created":"2019-07-10T09:32:57Z","department":[{"_id":"78"}],"type":"conference","keyword":["fault tolerant computing","field programmable gate arrays","logic design","reliability","BYU-LANL tool","DRM tool flow","FPGA based hardware designs","avionic application","device technologies","dynamic reliability management","fault-tolerant operation","hardware designs","reconfiguring reliability levels","space applications","Field programmable gate arrays","Hardware","Redundancy","Reliability engineering","Runtime","Tunneling magnetoresistance"],"author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"full_name":"Meisner, Sebastian","last_name":"Meisner","first_name":"Sebastian"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime","status":"public","year":"2013","date_updated":"2022-01-06T06:50:48Z","language":[{"iso":"eng"}],"_id":"10620","page":"1-6","user_id":"3118","doi":"10.1109/ReConFig.2013.6732280"},{"citation":{"mla":"Bick, Christian. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University, 2013.","bibtex":"@book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick, Christian}, year={2013} }","ama":"Bick C. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University; 2013.","ieee":"C. Bick, <i>Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Paderborn University, 2013.","apa":"Bick, C. (2013). <i>Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Paderborn University.","chicago":"Bick, Christian. <i>Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner</i>. Paderborn University, 2013.","short":"C. Bick, Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner, Paderborn University, 2013."},"date_created":"2019-07-10T09:40:24Z","type":"bachelorsthesis","department":[{"_id":"78"}],"year":"2013","title":"Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner","status":"public","author":[{"full_name":"Bick, Christian","first_name":"Christian","last_name":"Bick"}],"date_updated":"2022-01-06T06:50:48Z","_id":"10626","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"3118"},{"date_created":"2019-07-10T11:03:00Z","department":[{"_id":"78"}],"type":"conference","citation":{"ama":"Boschmann A, Nofen B, Platzner M. Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. In: <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2013.","bibtex":"@inproceedings{Boschmann_Nofen_Platzner_2013, title={Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Nofen, Barbara and Platzner, Marco}, year={2013} }","mla":"Boschmann, Alexander, et al. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2013.","short":"A. Boschmann, B. Nofen, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.","chicago":"Boschmann, Alexander, Barbara Nofen, and Marco Platzner. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2013.","apa":"Boschmann, A., Nofen, B., &#38; Platzner, M. (2013). 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