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IEEE. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>","ieee":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in <i>2013 14th Latin American Test Workshop-LATW</i>, 2013, pp. 1–6.","chicago":"Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In <i>2013 14th Latin American Test Workshop-LATW</i>, 1–6. IEEE, 2013. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>.","short":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6."},"publication":"2013 14th Latin American Test Workshop-LATW"},{"date_updated":"2022-01-06T06:51:40Z","title":"On Semeai Detection in Monte-Carlo Go.","year":"2013","status":"public","author":[{"full_name":"Graf, Tobias","last_name":"Graf","first_name":"Tobias"},{"last_name":"Schäfers","first_name":"Lars","full_name":"Schäfers, Lars"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"user_id":"398","_id":"13645","language":[{"iso":"eng"}],"publisher":"Springer","publication":"Proceedings of the International Conference on Computers and Games (CG)","citation":{"chicago":"Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer, 2013.","short":"T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.","apa":"Graf, T., Schäfers, L., &#38; Platzner, M. (2013). On Semeai Detection in Monte-Carlo Go. In <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer.","ieee":"T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go.,” in <i>Proceedings of the International Conference on Computers and Games (CG)</i>, 2013.","ama":"Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer; 2013.","bibtex":"@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers, Lars and Platzner, Marco}, year={2013} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” <i>Proceedings of the International Conference on Computers and Games (CG)</i>, Springer, 2013."},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:50:51Z"},{"author":[{"last_name":"Riebler","first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961"},{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"first_name":"Christoph","last_name":"Sorge","full_name":"Sorge, Christoph"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"year":"2013","title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","date_updated":"2023-09-26T13:37:35Z","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2013.6718394","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"date_created":"2017-10-17T12:42:35Z","file":[{"date_created":"2018-03-15T10:36:08Z","creator":"florida","success":1,"content_type":"application/pdf","file_id":"1294","date_updated":"2018-03-15T10:36:08Z","relation":"main_file","access_level":"closed","file_size":822680,"file_name":"528-plessl13_fpt.pdf"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["coldboot"],"status":"public","has_accepted_license":"1","publisher":"IEEE","_id":"528","page":"386-389","ddc":["040"],"user_id":"15278","citation":{"mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>."},"file_date_updated":"2018-03-15T10:36:08Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1"},{"status":"public","has_accepted_license":"1","publisher":"IEEE","_id":"505","ddc":["040"],"user_id":"15278","citation":{"ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., &#38; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>."},"file_date_updated":"2018-03-15T13:38:56Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"quality_controlled":"1","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Kling","first_name":"Peter","full_name":"Kling, Peter"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"first_name":"Friedhelm","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","id":"15523"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","year":"2013","date_updated":"2023-09-26T13:38:20Z","language":[{"iso":"eng"}],"doi":"10.1109/ISORC.2013.6913232","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"date_created":"2017-10-17T12:42:30Z","file":[{"file_id":"1308","success":1,"content_type":"application/pdf","file_name":"505-Plessl13_seus.pdf","file_size":1040834,"access_level":"closed","relation":"main_file","date_updated":"2018-03-15T13:38:56Z","date_created":"2018-03-15T13:38:56Z","creator":"florida"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference"},{"quality_controlled":"1","project":[{"grant_number":"01|H11004A","_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","citation":{"chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. Washington, DC, USA: IEEE Computer Society, 2013. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","apa":"Suess, T., Schoenrock, A., Meisner, S., &#38; Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 2013, pp. 64–73, doi: <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>. IEEE Computer Society; 2013:64-73. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, IEEE Computer Society, 2013, pp. 64–73, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>."},"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"place":"Washington, DC, USA","date_created":"2018-03-26T14:51:05Z","date_updated":"2023-09-26T13:38:05Z","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","status":"public","year":"2013","author":[{"full_name":"Suess, Tim","last_name":"Suess","first_name":"Tim"},{"first_name":"Andrew","last_name":"Schoenrock","full_name":"Schoenrock, Andrew"},{"full_name":"Meisner, Sebastian","last_name":"Meisner","first_name":"Sebastian"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"publication_identifier":{"isbn":["978-0-7695-4979-8"]},"doi":"10.1109/IPDPSW.2013.136","user_id":"15278","page":"64-73","_id":"1787","publisher":"IEEE Computer Society","language":[{"iso":"eng"}]},{"citation":{"mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2012, pp. 135–40, doi:<a href=\"https://doi.org/10.1109/FPT.2012.6412125\">10.1109/FPT.2012.6412125</a>.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={<a href=\"https://doi.org/10.1109/FPT.2012.6412125\">10.1109/FPT.2012.6412125</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2012:135-140. doi:<a href=\"https://doi.org/10.1109/FPT.2012.6412125\">10.1109/FPT.2012.6412125</a>","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2012, pp. 135–140.","apa":"Kasap, S., &#38; Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 135–140). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2012.6412125\">https://doi.org/10.1109/FPT.2012.6412125</a>","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 135–40. IEEE Computer Society, 2012. <a href=\"https://doi.org/10.1109/FPT.2012.6412125\">https://doi.org/10.1109/FPT.2012.6412125</a>."},"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","date_created":"2018-03-29T14:34:48Z","department":[{"_id":"27"},{"_id":"78"}],"type":"conference","author":[{"full_name":"Kasap, Server","last_name":"Kasap","first_name":"Server"},{"first_name":"Soydan","last_name":"Redif","full_name":"Redif, Soydan"}],"year":"2012","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","status":"public","date_updated":"2022-01-06T06:54:42Z","_id":"2097","publisher":"IEEE Computer Society","page":"135-140","doi":"10.1109/FPT.2012.6412125","user_id":"24135"},{"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","citation":{"short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In <i>Int. Architecture and Engineering Symp. (ARCHENG)</i>, 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in <i>Int. Architecture and Engineering Symp. (ARCHENG)</i>, 2012.","apa":"Kasap, S., &#38; Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In <i>Int. Architecture and Engineering Symp. (ARCHENG)</i>.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: <i>Int. Architecture and Engineering Symp. (ARCHENG)</i>. ; 2012.","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” <i>Int. Architecture and Engineering Symp. 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